JPS5847055B2 - Failure diagnosis method for information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure diagnosis method for an information processing apparatus, and specifically relates to a failure diagnosis method in which devices constituting the information processing apparatus are separated from each other during failure diagnosis.

Conventionally, as a method for separating devices during fault diagnosis, there is a method generally called a wraparound function. interface is logically separated, the effect that a write-type command issued from the central processing unit is about to have on the interface is temporarily stored in a register, and then the register is selected by a read-type command that is read out. The stored data is then sent back to the central processing unit.

In particular, the need for the wraparound function mentioned above was
To explain with reference to the multiprocessor system shown in the figure, the configuration of the multiprocessor system is as follows:
1 central processing unit 1, 2, 2 system control units 3, 4, 4 main memories 5, 6, 7,
8 and two input/output multiplexers 9 and 10, which are connected by a data bus as shown.

By the way, in the multiprocessor system described above, if one central processing unit 1 fails, for example, that central processing unit 1 is disconnected from the system and the other central processing unit 2. It is well known that the central processing unit 1 can be continued to operate only by the main memory, but on the other hand, the central processing unit 1 that has broken down during operation must be repaired.
Direct response from the system control unit)
Methods for diagnosing circuits in a central processing unit operated by: ■ Diagnosis by providing a wraparound function in the central processing unit; ■ Physically removing the interface scale and connecting a portable interface simulator in its place. There is a method of diagnosis.

However, method (■) above is by no means a desirable method because it requires a special interface simulator, a real system control unit, and main memory, and method (■) is not an effective method because it does not require the above. However, in order to realize the wraparound function, it is necessary to add a considerable amount of hardware. For example, when applied to the interface circuit shown in Figure 2, in addition to adding a control signal circuit part, it is necessary to add a considerable amount of hardware. A selector circuit is required to send back the 24 bits of the address field, 9 bits of the command field, and 72 bits of the data field as data to the central processing unit, which has the drawback of increasing the size of the entire node. Was.

Note that FIG. 2 shows an interface circuit 21 interposed between the central processing unit 1 and the system control unit 3 in FIG. the law of nature,
, L2 and the other to system control unit 3
Signal line L3. Control signal circuit 2 having L4
2, an address register 23 which inputs address information from the address conversion section of the central processing unit 1 through a signal line L5, and outputs it through a signal line L6;
The command register 24 inputs command information from the memory control circuit in the central processing unit 1 through the signal line L7 and outputs it through the signal line L8, and the data information from the main data bus of the central processing unit 1 is input through the signal line L9 and LIO. It is composed of a data register 25 that inputs data and outputs data through signal lines L1□ and L12.

Further, the signal line and L1□ are bidirectional transmission lines for reading read data from the system control unit 3 to the central processing unit 1.

Furthermore, 01 to G in the figure indicate gate circuits that control each signal line.

By the way, recently, a fault diagnosis device that uses a diagnostic bus has been developed, making it easy to diagnose most parts of the central processing unit, and also the system control unit and address/command registers. It became so.

However, the number of bits in the data register is too large, and even the method using the diagnostic bus requires a large number of selectors, which is not very effective.

This method was also ineffective against the need to simulate responses from main memory.

The present invention has been made in order to eliminate the above-mentioned drawbacks.The present invention has been made in order to eliminate the above-mentioned drawbacks.The present invention has been made in order to eliminate the above-mentioned drawbacks. This stand-alone signal is provided in the system control system as a central processing unit interface without any connection to conventional wrap-around mode address/command registers, data registers, or data transmission lines connected to these. It is designed to connect in response to operation requests between units.

An embodiment to which the present invention is applied will be described below with reference to FIG.

FIG. 3 shows a specific control signal circuit of the interface circuit (see FIG. 2) of the present invention, in which several types of signal lines are interposed between the central processing unit 1 and the system control unit 3.

The central processing unit 1 has n ports so that it can be commonly connected to a plurality of system control units, and in the illustrated case, the signal line on the central processing unit 1 side is the nth port. Indicates that it is connected.

Hereinafter, the input and output signal lines of the central processing unit 1 side and the output signal line to the system control unit 3 are LINTn? LPTONntLPToNn
1 and L 5tand alone, while the input signal line from the system control unit 3 is one LDIAcfio~a-LPINn 5LCONn
tLDXIPn and LD I NZ, fi, etc.

Also, regarding the input and output signal lines on the system control unit 3 side, LDIAC is used as the output signal line.
There are three lines, LPIN, LDA, LCON, LDXIP, and L, and there is LINT as the input signal INZ line.

Next, to describe the connection relationship of the signal lines mentioned above, the signal line LINTn and the signal line LINT are
A command is sent to the system control unit 3 from the HO) to transmit an operation request pulse INT which is output when requesting an operation to the main memory, etc., and unless this pulse INT is sent, the second Address register 23 and command register 2 as shown in the figure
4, and each signal line to the data address register 25 has no meaning to the system control unit 3.

Further, when the operation request pulse ■NT is received by the system control unit 3, the signal line LPIN and the signal line LPINn are connected to a response signal P in response to the operation request pulse ■NT.
This is a transmission line for sending IN.

This allows the memory control circuit (not shown) in the central processing unit 1 to send the next memory request to the system control unit 3.

Next, the signal line LDA1 and the signal line LDAn are transmission lines for transmitting the data ready signal DA to the central processing unit 1 through the system control unit 3 upon completion of the operation in response to the main memory operation request INT of the central processing unit 1 described above. be.

Here, if the command in FIG. 2 is of the read type, the data read from the main memory is set in the data register.

In addition, regardless of whether the command is a read or write command, if an abnormality (command parity error, etc.) is detected in the main memory/system control unit 3, the signal line LDI
4-bit information D via AC and signal line LDIACn
It is transmitted to the central processing unit 1 as an IAC.

Note that the 4-bit information indicates O if there is no abnormality.

Next, the signal line LCON and the signal line LcoNn are
A transmission line for transmitting communication pulses CON between the system control unit 3 and the central processing unit 1, and
The signal line L and the signal line XIP LDXIPn are connected to the system control unit 3.
This is a transmission line for transmitting an interrupt request signal DXIP to the central processing unit 1 from a subsequent input/output channel device (not shown).

When the system initialize button on the operator panel of the console is pressed, the signal lines LDINZ and LDINZn send the system initialize signal DINZ to the input/output multiplexer (not shown).
, and a transmission line for notifying the central processing unit 1 via the system control unit 3.

Further, the signal line LPTONn is a transmission line for transmitting the output of the pulse PTON of the configuration control register in the central processing unit 1, and specifically, the It connects to the

Finally, the signal line L5tandalone is a transmission path for the standalone signal SA obtained by specifying the standalone mode from within the central processing unit 1, and first inhibits the operation request signal INT described above, and also outputs the operation request signal pulse ■NTn. is delayed for a certain period of time, and then two pulses are generated, and when the stand-alone signal SA is generated, each pulse acts in place of the response signal PIN and the data ready signal DA. .

Further, the standalone signal SA is connected to the signal line LDI.
This forcibly sets the contents of AC8 to AC3 to O.

Regarding the logic elements shown between each signal line in FIG. 3, N1 to N represent NAND circuits, 11 to ■7 represent inverter circuits, 01 to 02 represent OR circuits that negate the input side, and DL represents a delay circuit.

The operation of the present invention configured as described above will be described below. In the stand-alone mode of the present invention, the central processing unit 1 has an entire main memory of 5°6.7, which is connected to a plurality of system control units 3. 8 (See Figure 1)
It is assumed that the data register is degenerated into a data register of an interface circuit (see FIG. 2).

First, when a command is issued from the central processing unit 1 to the write-type main memory, the memory control circuit within the central processing unit 1 operates in the same way as in a normal case, and writes data to a predetermined data register 25. The same address register 23 and command registers 2 and 4 are set with their respective address information and command information.

Next, an operation request pulse ■NT is sent from the central processing unit 1.
Although n is sent from the memory control circuit at a predetermined timing as in the normal case, the operation request pulse INT is not transmitted to the system control unit 3 because the operation mode is in the stand-alone mode.

Therefore, even if the interface scale of the system control unit 3 is connected, a write command issued from the central processing unit 1 in standalone mode cannot rewrite the contents of the main memory 5, 6, 7.8. (, the main memory 5, 6, 7
, 8 in a busy state, and furthermore, when the central processing unit 1 of a multiprocessor system fails, even if you run the diagnostic program in standalone mode with the cable physically connected to the system, the system will not be in operation. There are no negative effects.

The operation request pulse ■NTn is supplied to the delay circuit DL.
The response signal P is delayed by a certain period of time due to
INn and data ready signal DAn are generated.

Furthermore, since the mode is in stand-alone mode at this time, all bits of the 4-bit information DIAC are O.

This means that the response signal PINn and data ready signal DAn are sent from the interface 21 as if the operation request pulse NTn had been sent to the main memory and the operation indicated by the write command had completed normally. This means that the pulses are sent to the memory control section of the central processing unit 1, and the internal parts of the central processing unit 1 operate in response to each pulse.

Incidentally, when a read-type command is similarly generated from the central processing unit 1, at that time the central processing unit 1 sets address information and command information in the respective address registers 23 and command registers 24, but the data The contents of register 25 remain unchanged and are not changed.

Here, even if the operation request pulse NTn is generated, the operation request pulse INT of the system control unit 3 is not generated, and therefore the system control unit 3 and the main memories 5, 6, 7 are not generated as in the case of writing. , 8 will not be affected in any way.

Then, the response signal PINn and the data ready signal DAn are generated in the same way, and the main memo! J5
, 6°7.8, the same operation is performed within the central processing unit 1 as in the case where the data reading from 6°7.8 is completed normally.

Here, if the stand-alone mode is used, the main memories 5, 6, 7, 8 and the system control unit 3 send the data ready signal DA to the central processing unit 1 in response to the read type command. At the same time, the read data is set in the data register 25, but since the operation request pulse INT is not generated in this case, what is the main memory 5, 6, 7, 8 and the system control unit 3? It doesn't work either.

Therefore, the data register 25 still contains the data sent from the central processing unit 1 along with the previous write type command, and in response to the read type command, the data register 25 is stored as if it were the main memo 'J 5, 6, 7.
, 8 is sent to the central processing unit 1 as if it were data read out from .

That is, regardless of the contents of the address register 23, writing is always performed to the data register 25, and reading from the data register 25 is always performed, and from the perspective of the central processing unit 1, the related main memory It appears that all the addresses in the data register 25 have been degenerated.

The data register 25 described above has a 72-bit configuration, and there is actually a distinction between words at odd addresses and words at even addresses, and all addresses of all memory units connected to the end of this interface circuit are distinguished. Among these, odd addresses are degenerated to the right half of the data register 25, while even addresses are degenerated to the left half.

In other words, when the central processing unit 1 is in the stand-alone mode, the main memory is 0 for each interface of each system control unit 3.
It can be thought of as having a memory that has only two addresses, address 1 and address 1, and therefore the design of the diagnostic program becomes easy.

The basic operation of the present invention has been explained above, but
Next, we will discuss how to diagnose, for example, a central processing unit that has failed while the system is in operation.First, we will examine the failure of the central processing unit 1 in a multiprocessor system by physically connecting the interface scale to the system. By switching to the stand-alone mode, the stand-alone mode can be used when diagnosing a failure by logically separating the system from the system, and when the central processing unit 1 and system control unit 3 of the system are physically separated. may be used to diagnose the failure.

Note that in the case of diagnosing the system by logically separating it, the systems other than the failed central processing unit 1 are operating correctly and the entire system has already been reconfigured. No control signal is sent to the central processing unit 1.

Furthermore, while one central processing unit 1 in the system is out of order, the probability that other central processing units 1, system control units 3, etc. will be out of order is approximately equal to the square of the failure probability of one unit. Since it is small, the risk of other devices failing and erroneously sending control signals to the central processing unit 1 is considered to be virtually negligible.

Furthermore, in the case where diagnosis is performed by physically separating the system control unit 3, the system control unit 3 is not connected and no control signal is received from the outside.

In addition, in FIG. 3, the system control unit 3
and the interface circuit 21 are designed to become positive when the connection is broken. Therefore, if the cable between the system control unit 3 and the system control unit 3 is physically disconnected, other control signals including the response signal PIN becomes logically O, while all bits of the 4-bit information DIACo~3 indicating an error become 1.

Fault diagnosis for multiprocessor systems as described above is
First, if a failure occurs in the stand-alone mode control signal SA itself, the diagnostic program sets the stand-alone mode to protect the main memory, but in reality the main memory is not protected at all.

This means that a failure has occurred in two places: inside the central processing unit 1 and in the standalone mode control signal system, and the fact is that the failure occurs at a rate of about the square of the single failure rate. It only occurs with a negligible probability.

Therefore, the stand-alone mode can be diagnosed in the diagnostic program as follows.

That is, when the standalone mode is set, the central processing unit 1 issues a double read command to two different addresses, compares the results, and if set correctly, reads the data register regardless of the address. Since the stored contents are read, the two are always equal.

However, if the main memory operation in the stand-alone mode is not performed correctly, the two actually designated addresses will be compared, resulting in different contents.

Note that if the contents of the main memory are random, the probability that two addresses will have the same value by chance is 2-72>10-21 and can be ignored.

In that case, since the command erroneously sent to the main memory is a read command, a failure in the stand-alone mode signal system will not destroy the contents of the main memory.

Furthermore, in a method of checking the operation of the hardware of the central processing unit 1 by using the idle time of the central processing unit 1 during system operation, the waiting time until the central processing unit 1 completes the operation of the input/output device is By using the standalone mode mentioned above, the main memory 5 is
, 6, 7, and 8 is prohibited, but external control signals to the interface circuit 21 are blocked regarding interrupt requests from input/output devices and communication between the central processing unit 1. Therefore, each control signal is correctly sent to the central processing unit 1 even during operation check.
This makes it possible to protect the contents of the main memory during confirmation and to determine whether there is an interrupt request from the input/output device being confirmed. Even if the communication signal CON is sent from the communication terminal 1, the communication request signal will not be lost because the communication signal is not interrupted.

In the embodiment of the present invention shown in FIG. 3, a NAND circuit N3. N4 is used, but the NAND circuit N
It goes without saying that a NAND circuit may be connected to the input side of the delay circuit DL instead of 3j N4 to input the operation request pulse NTn and the stand-alone signal SA.

As described above, the fault diagnosis method for an information processing device according to the present invention includes providing hardware for generating a standalone mode in one of the devices constituting the information processing device, and further generating an operation request using this standalone signal. It is designed to be connected to the control signal line, and with the addition of a very small amount of hardware, it enables a better diagnosis method than the conventional wraparound function, and also allows for logical or physical separation between information processing devices. It is also possible to have a function for simulating normal responses from the main memory.

In addition, in the standalone mode mentioned above, since the control signal line that generates the operation request is connected, the control input signal from the outside is not blocked by the interface circuit, so the main memory is protected for operation confirmation tests while the system is running. It is also suitable as a means.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiprocessor system showing the general configuration of an information processing device, FIG. 2 is an interface circuit diagram thereof, and FIG. 3 is a specific circuit diagram in which the present invention is applied to an interface circuit. show. 1...Central processing unit, 3...System control unit), Lstand alone.
...Standalone signal line, LINT, INT
n...Operation request pulse signal line, LPIN, P
INn・・・Response signal line, LDA, D
Afi...Data ready signal line, DL...
...Delay circuit.

Claims (1)

[Claims] 1. In an information processing device having two operating modes, a normal mode and a diagnostic mode, an operation request signal is sent to an external device when in the normal mode, and the operation request signal is not sent when in the diagnostic mode. When an operation request to an external device is accepted while in the diagnostic mode, the operation request signal is delayed for a certain period of time so that the external device apparently responds to the operation request signal. an interface circuit comprising means for receiving the signal from the external device as a correctly responded signal and transmitting a control signal again to the inside of the information processing device, and when in the diagnostic mode state, the interface circuit 1. A failure diagnosis method for an information processing device, characterized in that a control input signal from an external control device is not cut off when all storage locations in an external device connected to the external device operate as if degenerated.