JP3531394B2 - Peripherals in half-duplex data transfer systems - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to control of a buffer which is storage means in a half-duplex data transfer system between a host computer and a peripheral device such as a printer. 2. Description of the Related Art In a receiving unidirectional data transfer system (as viewed from a peripheral device) typified by a Centronics or the like, a data output device with a mechanical operation such as a printer is connected to the data output device. Operating speed is significantly slower than that of a host computer. Therefore, when transferring data from the host computer to the printer,
Data buffering is performed to compensate for the difference in operation speed between the two. [0003] Normally, when sending data to a data output device including a printer, a host computer monitors time to see if a data transfer request has occurred from the data output device within a predetermined period, and operates the data output device. Is monitoring the health of Therefore, in order to avoid the occurrence of a timeout due to such time monitoring during normal operation, a peripheral device such as a printer, which operates at a much lower speed than the host machine, may be provided with a large-capacity buffer or a host machine. It is necessary to change the timeout condition by changing the program. However, it is not preferable to change such monitoring conditions for one peripheral device in a general-purpose computer. Therefore, in the prior art, Japanese Patent Laid-Open No. 62-198
As described in Japanese Patent Application Publication No. 926, a buffer is divided into a high-speed fetch area and a low-speed fetch area, and a data output device with a simple configuration that does not suffer from a timeout error of a host machine is provided. [0005] Even in a half-duplex data transfer system between a peripheral device standardized by IEEE Std 1284 and a host computer, the interface unit usually has a transmission buffer and a reception buffer, and the difference in operating speed between the host machine and the peripheral device. Is compensated. However, even in the case of a half-duplex data transfer system, even if the peripheral device operates at a low speed without greatly increasing the buffer capacity (memory cost) as described above. It is necessary to avoid the timeout error of the host machine in the normal operation, that is, to shorten the data transmission waiting time of the host machine due to the full buffer capacity. Therefore, in the present invention, IEEE Std
An object of the present invention is to provide a control method for shortening a data transmission waiting time of a host machine in a half-duplex data transfer system represented by 1284 between a host and a peripheral device. In order to solve the above problems, according to the present invention, an interface unit having a buffer for transmission and reception independently, a buffer in use for an interface control unit, and another buffer unit are provided. There is provided switching means for securing the used buffer as a free area of the used buffer. That is, the present invention relates to a host machine and its peripherals.
Used for half-duplex data transfer system with
FIFO buffer for storing data and received data
In a peripheral device having a storage means comprising
Data storage means for storing data, and received data
Receiving data storage means and storing the received data storing means
Detecting means for detecting the amount of data;
Depending on the result, the storage destination of the data is
Switching means for switching to transmission data storage means.
A peripheral device characterized by the following. In the interface unit of a peripheral device such as a printer, buffers for transmission and reception are provided independently of each other. When an empty space in the reception buffer is reduced or exhausted, the interface control unit transmits another unused transmission buffer. There is provided switching means for securing the buffer as a free area of the reception buffer. This makes it possible to temporarily secure extra buffer capacity, reduce the data transmission waiting time of the host machine when a large amount of data is transferred compared to the buffer capacity, and improve transfer efficiency. is there. An embodiment of the present invention will be described below. Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram of a data transfer system between a host machine 1 and a peripheral device 2. The host machine 1 and the peripheral device 2 are connected by a half-duplex bidirectional data bus 3. The peripheral device 2 includes a CPU 21, a RAM 22, a ROM 23, an interface unit 24, and an internal bus 25. The interface unit 24 includes a transmission buffer 241 and a reception buffer 242 serving as storage units, and an interface control unit 24.
Three. FIG. 2 is a specific configuration diagram of the interface unit 24 of the peripheral device 2.
FIFO (first in first out) transmission buffer 241, FIFO
O reception buffer 242, interface control unit 243
And the transmission buffer 241 and the reception buffer 242 respectively have detection means 2411 and 2421 for detecting the amount of stored data. CPU 21 and RAM 2 inside the peripheral device 2
2. The ROM 23, the interface unit 24, and the like are connected by an internal bus 25. The interface unit 24 interfaces the bidirectional data bus 3 and the internal bus 25, and includes a transmission buffer 241 and a reception buffer 24.
2 are provided independently of each other. The detection means 2411 of the transmission buffer 241 detects whether the stored data amount is equal to or larger than a predetermined amount set in advance.
The reception buffer 242 includes a detection unit 2421 as in the transmission buffer 241, and the interface control unit 243 includes a control unit that controls the detection units 2411 and 2421 and the selectors 244a to 244d. The data transfer device is an interface unit 24
And the transmission data storage means is a transmission buffer 241,
The reception data storage means corresponds to the reception buffer 242, and the switching means corresponds to the selectors 244a to 244d. The receiving buffer 24 is selected by the selector 244a.
2 or the transmission buffer 241 can be selected. The data from the reception buffer 242 or the transmission buffer 241 can be selected by the selector 244b, the reception data or the transmission data can be selected and input to the transmission buffer 241 by the selector 244c, and the data of the transmission buffer 241 can be selected by the selector 244d. Or output to the bidirectional data bus 3 is selected. Data transfer from the host machine 1 to the peripheral device 2 is performed through the reception buffer 242, and vice versa. Looking at the flow of data transfer taking reception as an example, the host machine 1 recognizes the state of the peripheral device 2 through a control line, and drives the data to the bidirectional data bus 3 when data reception is ready. Peripheral device 2
Latches the data by the change of the control line and
42, and when the next data is ready to be received, the previous control line is changed. Data reception is performed by repeating this series of operations. Normally, when data is written to the reception buffer 242, an interrupt is generated from the interface unit 24 to the CPU 21 of the peripheral device 2, and the CPU 2
1 takes in data. FIG. 3 shows the flow of data according to the present invention. Normally, data is stored in the reception buffer 242, and the CPU 21 reads the data. However, the reception buffer 24
When the detecting unit 2421 detects that the free space has run out (when the full data is stored in the reception buffer 242), the interface control unit 243 replaces the unused transmission buffer 241 with the free space in the reception buffer 242. And the subsequent received data is stored in the transmission buffer 2
41 is written. FIG. 2 shows an example using a selector, and FIG. 4 shows an example of a buffer control algorithm. When the data is transferred from the host machine 1, the selector 244a selects the receiving buffer 242, and the data is taken into the receiving buffer 242 (400). When the detecting means 2421 does not detect that the amount of data stored in the receiving buffer 242 is full, that is, when it is determined that there is a free area (401),
The data acquisition is repeated (400). When the data transfer from the host machine 1 continues and the receiving buffer 242 stores data that makes the receiving buffer 242 full, the detecting means 2421 detects the buffer full of the receiving buffer 242 (401). The selectors 244a to 244d are switched to use the buffer 241 for reception (410). The subsequent data is stored directly in the transmission buffer 241 via the selector 244c (411). Data acquisition is repeated until the detecting means 2411 detects that the transmission buffer 241 is full (411). When the detection means 2411 of the transmission buffer 241 detects that the transmission buffer 241 is full (412), there is no free space in the reception buffer 242, that is, the detection means 2421 detects again that the reception buffer 242 is full ( Until 413), the data is stored in the reception buffer 242 (400). If there is no free space in the reception buffer 242, the process waits until the stored data is read out by the CPU 21 of the peripheral device 2 (413). When the received data in the transmission buffer 241 is a CP
When the data is read out by the U21 and becomes empty (414), the interface control unit 243 switches the selectors 244a to 244d to switch the transmission buffer 24 storing the received data.
1 is restored for the original transmission (415). The selectors 244a to 244d are controlled by the interface control section 243 both at the time of writing and at the time of reading. In the above embodiment, reception is described, but the same operation is performed for transmission. Although the storage data amount detected by the detection means for detecting the storage data amount of the storage means is equal to or more than a predetermined amount, for example, full, the storage data amount of the storage means and the storage means are newly added. It may be detected whether or not the sum of the data amount to be stored is larger than the data amount that can be stored in the storage means. Further, for example, since the transmission data storage unit may be switched to reception, it may be unclear which data the storage unit is to store. In that case, it is necessary to provide a detecting means for detecting which data is to be stored in the storing means. In that case, new means may be provided, but buffer detecting means 2411, 242
It is also possible for 1 to have that function. As described above, according to the present invention, an extra buffer capacity can be temporarily secured, and data transmission by the host machine when a large amount of data transfer is performed compared to the buffer capacity. The waiting time can be reduced, and the efficiency of data transfer between the host and the peripheral device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a host machine and a peripheral device data transfer system. FIG. 2 is a specific configuration diagram of an interface unit of the peripheral device data transfer device of the present invention. FIG. 3 is an explanatory diagram of an example of a data flow in the peripheral device data transfer device of the present invention. FIG. 4 is an explanatory diagram of an example of a buffer control algorithm in the peripheral device data transfer device of the present invention. [Description of Signs] 1 host machine, 2 peripheral equipment, 21 CPU,
22 RAM, 23 ROM, 24 interface unit, 241 transmission buffer, 2411 transmission buffer detecting means, 242 reception buffer, 242
1 reception buffer detecting means, 243 interface control section, 244a-d selector, 25 peripheral device internal bus, 3 bidirectional data bus.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 3/12

Claims (1)

(57) [Claim 1] Used in a half-duplex data transfer system between a host machine and a peripheral device, having storage means comprising a FIFO buffer for storing transmission data and reception data. In the peripheral device, transmission data storage means for storing transmission data, reception data storage means for storing reception data , detection means for detecting the amount of data stored in the reception data storage means, and The data storage location
A peripheral device, comprising: switching means for switching from transmission data storage means to transmission data storage means .