JPH06110653A - Memory system and memory control method using the same - Google Patents

Abstract

PURPOSE:To provide the memory system which can precisely detect the capacity of data stored in a first-in first-out(FIFO) memory or the capacity of an free area. CONSTITUTION:The capacity of data stored in a FIFO memory 26 for reading/ writing data according to the FIFO operation can be calculated by subtracting the respective count values of input and output counters 46 and 48 by using a subtracter 49. A memory capacity judging device 28 to input the output of this subtracter 49 is provided with a comparator 50 and a register 52. A threshold value previously set by a CPU is stored in the register 52, current memory capacity data from the subtracter 49 are compared with the threshold value by the comparator 50 and this compared result is outputted to the CPU so that the CPU can recognize the memory capacity in the FIFO memory 26. The threshold value in the register 52 can be reloaded by the CPU, and the memory capacity can be more precisely judged by setting the threshold value to any desired value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system which performs a first-in first-out operation or a first-in first-out operation and a memory control method thereof.

[0002]

2. Description of the Related Art A first-in first-out memory (first-in first-out, hereinafter referred to as "FIFO") is a memory that outputs data in the order of input, and is used to transfer data between various systems. Various data such as image data, audio data, and control data can be considered as the data to be input / output. It is commonly used for data transfer between asynchronous systems with different operation speeds such as data transfer between processors and data communication between various systems.

For example, when a FIFO memory is used in the receiving system, the input data from the transmitting system side is sequentially F
It will be stored in the IFO memory. Then, at a certain timing of the CPU in this receiving system, a read command is issued to the FIFO memory, and the data is read from the FIFO memory in the order of input. Where CP
The timing at which the U issues a read command to the FIFO memory is when the data storage capacity in the FIFO memory reaches a certain value or when a time preset by the CPU is reached. Also, the CPU in the receiving system allows the transmitting system to XO that permits data transfer if there is a free area in the FIFO memory.
N is set to output XOFF which prohibits data transfer if there is no free area.

The CPU needs to know the data storage capacity in the FIFO memory when performing read / write control of the FIFO memory. Conventionally, the data storage capacity is FULL or HAL.
Any one of the three states of F and EMPTY was detected. If any of these three states is detected, for example, an interrupt signal is input to the CPU, and F
Reading and writing of data with respect to the IFO memory will be controlled.

[0005]

By the way, this type of memory needs to be used universally among various asynchronous systems. In this case, the writing speed to the FIFO memory depends on the transmitting system, and the reading speed is FI.
It depends on the data processing on the side where the FO memory is arranged. Thus, the read / write speed of the FIFO memory is FI
Depending on the system in which the FO memory is used, if only fixed memory capacity information can be obtained as in the conventional case, precise memory control in consideration of the difference in read / write speed is impossible.

Further, conventionally, since only the above-mentioned three kinds of states concerning the memory capacity can be detected, it is impossible to individually detect whether or not the particular memory capacity which is of interest is reached in the read / write control of the memory. Therefore, this also makes it impossible to perform precise memory control.

As described above, in the conventional device, due to the lack of data relating to the memory capacity, more precise data processing control for effectively utilizing the memory area in the FIFO memory while minimizing the involvement of the CPU. However, this kind of problem also occurs in the case of the first-in / last-out (first-in-last-out, hereinafter referred to as "FILO") memory.

In view of the above, the object of the present invention is to solve the above-mentioned conventional problems and to determine the data storage capacity of the memory or the remaining capacity of the empty area of the system for reading and writing data according to the first-in first-out operation or the first-in first-out operation. (EN) A memory system capable of recognizing according to the purpose of use and further enabling comparison with a memory capacity of interest individually, thereby providing a memory system capable of more precise data read / write control, and a memory control method using the same. Especially.

[0009]

A memory system according to the present invention comprises a memory for writing and reading data according to a first-in first-out operation or a first-in first-out operation, and a capacity or an empty area in which the data is stored in the memory. Memory capacity detection means for detecting the remaining capacity as memory capacity, storage means for rewritably storing an arbitrary threshold value to be compared with the memory capacity, and the memory capacity and the threshold value are compared, and the comparison is made. And a comparison means for outputting a result.

A memory control method according to the present invention has a control means for controlling the reading and writing of data from and to the memory of the memory system, and the control means stores the threshold value in the storage means in advance, In parallel with the subsequent reading and writing of data from and to the memory, the comparison means makes a comparison, and the data storage capacity or the free area capacity of the memory is determined by receiving a notification from the comparison means.

Another memory control method according to the present invention has control means for controlling the reading and writing of data from and to the memory of the memory system, and the control means monitors the memory capacity at which the reading and writing of data is performed. A threshold value corresponding to the memory capacity of interest is stored in the storage means at an appropriate timing, and it is determined whether or not the memory can be read and written based on the comparison result from the comparison means thereafter. Characterize.

[0012]

In the memory system according to the present invention, the capacity in which data is stored or the remaining capacity of the empty area is detected as the memory capacity by the memory capacity detecting means of the memory that writes and reads data according to the FIFO operation or the FILO operation. Is output. On the other hand, an arbitrary threshold value to be compared with the detected memory capacity is stored, and the memory capacity and the threshold value are compared with each other by the comparison means, and the result is compared with the desired threshold value. Therefore, it is possible to determine a wider memory capacity according to the applied system than the conventional fixed memory capacity information.

In the memory control method using this memory system, the control means stores the threshold value in the storage means in advance, and thereafter, the comparison means performs the comparison in parallel with the reading and writing of data from and to the memory. The control means can also start another process until receiving the notification from the comparison means. Then, by receiving the notification from the comparison means, the data storage capacity or the free area capacity of the memory can be recognized in relation to the threshold value, and the processing for the memory can be determined.

According to another memory control method of the present invention, the control means corresponds to the memory capacity of interest to the storage means at the timing at which the memory capacity of the memory where the data is read and written is to be monitored. Stores the threshold value. Then, based on the comparison result from the comparing means immediately after that, it is judged whether or not reading / writing from / to the memory is possible, and for example, data reading is started, or XON, XOFF can be output to the data transfer destination.

[0015]

EXAMPLE An example to which the present invention is applied will be described below.
A specific description will be given with reference to the drawings.

As shown in FIG. 2, the apparatus of this embodiment comprises a transmission system 10 and a reception system 20, and in the reception system 20, the memory capacity of the FIFO memory is parallel to the reading and writing of data from and into the FIFO memory. A memory system capable of recognizing (a capacity in which data is stored or a remaining capacity in an empty area) is provided.

In FIG. 2, the transmission system 10 transmits data to the reception system 20 side via the data transmission unit 12. The receiving system 20 is provided with a CPU 22 that controls the system 20 and a data receiving unit 24 that receives data from the data transmitting unit 12. Further, a FIFO line is provided in a bus line of the CPU 22.
The memory 26, the memory capacity determination device 28, the memory 30, the input / output device (I / O) 32, and the data transmission unit 34 are connected.

The FIFO memory 26 can be constituted by a FIFO dedicated memory or a combination of SRAM or DRAM and a FIFO controller. The FIFO memory 26 may be configured by software. In any case, the FIFO memory 26 writes the data from the data receiving unit 24 in the memory area according to the write signal. Further, based on the read command from the CPU 22, the data in the FIFO memory 26 can be read in the input order according to the read signal. In addition, FIFO
Details of the memory 26 will be described later.

The memory capacity determination device 28 inputs the current memory capacity output from the FIFO memory 26,
The memory capacity is determined by comparing with a threshold value preset by U22. Memory capacity determination device 2
The comparison result in 8 can be output to the CPU 22 as an interrupt signal. The details of the memory capacity determination device 28 will also be described later.

The memory 30 has, for example, a storage area in which an operation program of the CPU 22 is stored and a working area for executing various processes of the CPU 22. The input / output device 32 is, for example, a printer, and has a FIFO.
The read data from the memory 26 can be output.

The data transmission section 34 transmits the code data and the like output from the CPU 22 to the transmission system 10 side. The code data includes XOFF which means “prohibit data transmission” and XON which means “permit data transmission”. CPU22
Is based on the determination result from the memory capacity determination device 28,
The above XOFF and XON are output.

Next, details of the FIFO memory 26 and the memory capacity determination device 28 will be described with reference to FIG. The FIFO memory 26 is composed of a dual port RAM 40 and a FIFO control section in this embodiment. As this FIFO control unit, R
It has an input control logic 42 and an output control logic 44 that control the reading and writing of data to and from the AM 42. Further, an input counter 46, an output counter 48 and a subtractor 49 are provided in the FIFO control section, and these constitute memory capacity detecting means. The input control logic 42 is prohibited from writing when the memory capacity in the FIFO memory 26 reaches FULL and when a reset signal from the CPU 22 is input. The output control logic 44 has a memory capacity of E in the FIFO memory 26.
Data reading is prohibited when MPTY is reached and when a reset signal is input.

The subtractor 49 subtracts (input count value-output count value) by inputting the outputs of the input counter 46 and the output counter 58, and the FIFO memory 2
The current data storage capacity in 6 is calculated. here,
In this embodiment, the total memory capacity of the FIFO memory 26 is 1K.
It shall be a byte, and 10 bits shall be assigned to the address. The input counter 46 and the output counter 48 are configured by, for example, 10-bit binary counters and are reset to all "0" by a reset signal from the CPU 22. The output of the subtracter 49 which inputs the 10-bit input and output count value is also 10 bits, and the sign and the value of the 11th bit are not output.

The memory judging device 28 has a comparator 50 as a comparing means and a register 52 as a storing means. The output of the subtractor 49 is input to one input end of the comparator 50, and the output of the register 52 is input to the other input end. The data stored in the register 52 is an arbitrary threshold value of 10 bits set by the CPU 22 for comparison with the memory capacity. In this embodiment, the threshold value in the register 52 can be rewritten by the CPU 22. The comparator 50 determines, for example, whether or not the outputs of the subtractor 49 and the register 52 are the same as each other as a threshold value comparison operation. The output of the comparator 50 is sent to the CPU 22. It can also be used as an interrupt signal.

Next, specific operation contents of the memory capacity determination device 28 and operation contents of the CPU 22 based on the output will be described with reference to FIG.

FIG. 3 shows various setting modes of the threshold value written in the register 52. In the case of FIG. 9A, the data in the FIFO memory 26 is almost EMP.
The lower limit threshold (for example, the storage data capacity is 3 bytes) for the CPU to recognize that it has become TY, and the FIFO
C that the data in the memory 26 has become almost FULL
It is possible to set an upper limit threshold (for example, the storage data capacity is 1021 bytes) for the PU 22 to recognize, and an intermediate threshold M. The upper and lower thresholds shown in FIG. 9A may be fixed, and this point is the same as that of the conventional apparatus, but the characteristic of this embodiment is that the intermediate threshold value M Is that it can be set arbitrarily. The intermediate threshold value M can be determined in consideration of the data processing of the transmission system 10 and the reception system 20. For example, the CPU 22 can arbitrarily set based on the magnitude relationship between the writing speed and the reading speed.

The configuration of the memory capacity determination device 28 for realizing the operation of FIG. 3A is as shown in FIG. In this case, since three types of threshold values are required, the first
-Third comparators 50a-50c and corresponding first
~ Third registers 52a to 52c are provided. The current capacity data from the subtractor 49 is set to A, and each register 52a ...
When the threshold value stored in 52c is B, the comparators 50a to 50c can be configured as comparators that perform A = B comparison. The structure of the comparators 50a to 50c in this case is shown in FIG.

In the figure, both the current capacity data A and the threshold value B are, for example, 10-bit data, the current capacity data A is input to one input terminal of the adder 60, and the threshold value B is passed through the inverter 62. It is input to the other input terminal of the adder 60. The adder 60 and the inverter 62 realize the subtraction of (AB). That is, the adder 60 adds the signal obtained by inverting each bit of the threshold value B and the current capacity data A, and the carry function of the adder 60 adds "1" to the least significant bit (LSB). Is added, the complement of the threshold value B and the current capacity data A are added, and the subtraction of (AB) is realized. The output of the adder 60 is the least significant bit (LSB)
From the D0 output that becomes, the D that becomes the most significant bit (MSB)
Outputs of 10 bits up to 9 are obtained. The respective bit outputs D0 to D9 are input to the OR logic gate 64, and the OR logic result is input to the CPU 22 via the inverter 66.

When the current capacity data A and the threshold value B match, all the bit outputs of the adder 40 become "0", so the output of the OR logic gate 46 becomes "0", and the signal is It is inverted by the inverter 46 and becomes "1",
As a result, the CPU 22 is interrupted. On the other hand, when the current capacity data A and the threshold value B do not match, any one of the bit outputs D0 to D9 of the adder 60 is always "1", so the output of the OR logic gate 64 is also "1". Therefore, the output of the inverter 66 becomes "0" and the CPU 22 is not interrupted.

In the case of the operation shown in FIG.
Before data is read from or written to the O memory 26,
After the CPU 22 sets the threshold values in the registers 52a to 52c, the operation other than the operation to the FIFO memory 26 is started, and the comparison is performed by the comparators 50a to 50c in parallel with the subsequent data reading and writing to the FIFO memory 26, This is effective when the signals from the comparators 50a to 50c are input as interrupt signals. In particular, conventionally, when the memory capacity becomes half of the total memory capacity, the CPU 22 is interrupted and the CPU 22 causes the FIFO memory 26 to
It was necessary to start the reading process from the CPU, but by setting the intermediate threshold value M in FIG. 3A to a value higher than that, for example, the operating efficiency of the CPU 22 is improved, The overall processing efficiency can be improved.

Next, when the CPU 22 wants to monitor the memory capacity of the FIFO memory 26 in which data is read / written (including during reading / writing), the threshold value corresponding to the memory capacity of interest in the register 52 is set at any time. Store it,
Waiting for the comparison result from the comparator 50, the FIFO memory 26
3 (B) to 3 (E), regarding a preferred embodiment in the case of performing data processing for, for example, deciding whether to issue a data read command or deciding whether to output an XON or XOFF data code. And it demonstrates with reference to FIG. 6 and subsequent figures.

In the case of FIG. 3B, the threshold value corresponding to the memory capacity of interest is a value L having a relatively small memory capacity, and in the case of FIG. 3C, the threshold value is set. This is the case where the value is the value H, which has a relatively large memory capacity.

In the case shown in FIG. 3B, for example, the amount of data to be transferred from the transmission system 10 side is relatively large, and when there is a request, the CPU 22 has a relatively small memory capacity L. Is individually set in the register 52, and it is effective when it is desired to immediately determine whether or not the memory capacity is larger than the threshold value L. In the case of FIG. 3C, the memory area is effectively used and the memory capacity is F.
This is a case where it is desired to read data from the FIFO memory 26 only after the state where the data does not reach the ULL. In either case of (B) and (C) in the figure, the comparator 50 detects whether the current capacity data from the subtractor 49 is larger or smaller than the threshold L or H. There must be. FIGS. 6 and 7 show a configuration example of the comparator 50 in the case of FIGS. 3B and 3C.

FIG. 6 shows an example of the configuration when the comparator 50 makes the determination of A> B. In this case, the output of the adder 60 shown in FIG. 5 is 11 bits, and "1" is not added to the least significant bit. Threshold B
Data inverted by the inverter 42 and the input data A
When A and B are added, the most significant bit D10 of the adder 40 is always "1" when A> B. Therefore, the output D10 of the most significant bit itself can be used as a signal to the CPU 22. In general, when the subtraction is realized by using the adder, the complement is calculated and the least significant bit is carried. However, the output D10 of the most significant bit can determine A> B without carrying the carry. The circuit can be simplified.

FIG. 7 shows a configuration example in which the comparator 50 determines the case of A <B. In this case, the adder 60 and the inverter 62 shown in FIG. 5 may be used, the output of the adder 60 may be 11 bits, and the output D10 of the most significant bit may be inverted by the inverter 70 and input to the CPU 22. That is, the case of A <B means that the subtraction result of AB is negative, and in this case, the output of the most significant bit D10 of the adder 60 is always "0". Therefore, the output of the most significant bit D10 may be inverted and used as a signal to the CPU 22.

Even when the comparator 50 is constructed by either the type shown in FIG. 6 or the type shown in FIG.
After setting the threshold value corresponding to the memory capacity of interest, the output from the comparator 50 is awaited. And C
Immediately after the PU 22 inputs the comparison result from the comparator 50, it is possible to immediately determine whether or not to perform data processing on the FIFO memory 26, for example, a read command, XON or XOFF output.

FIG. 3D shows an example of determining whether the memory capacity of interest is between the upper limit threshold value H and the lower limit threshold value L. The range of the memory capacity of interest can be narrowed or widened by setting the upper and lower threshold values H and L to desired values. When the capacity is included, it is possible to control to write data to or read data from the FIFO memory 26.

The memory capacity determination device 28 in this case is as shown in FIG. That is, the two comparators 50a,
50b is provided, and a first register 52a for storing the upper limit threshold value H and a second register 52b for storing the lower limit threshold value L are provided correspondingly.
Further, an AND logic gate 80 for inputting two outputs of the two comparators 50a and 50b is provided, and an output of this gate 80 is inputted to the CPU 22. When the current capacity data output from the subtractor 49 is A, the comparator 50a outputs A <
The judgment of H is made, and the comparator 50b judges A> L. Therefore, the comparator 50a has the configuration shown in FIG. 7, while the comparator 50b has the configuration shown in FIG.

With this configuration, one comparator 50
In a, "1" is output only when A <H, and in the other comparator 50b, "1" is output only when A> L. Therefore, the AND logic gate 80 which inputs the outputs of the comparators 50a and 50b into two is established only when the outputs of the comparators 50a and 50b are both "1", that is, when L <A <H. When the output of the AND logic gate 80 is "1", the CPU 22 can recognize that the data capacity exists within the range of interest shown in FIG. It can be carried out.

In FIG. 7, the first register 50
the threshold L to a and the threshold H to the second register 50b.
Is stored and an OR logic gate is connected instead of the AND logic gate 80, it is possible to determine outside the range of interest in FIG. 3D, that is, A <L or A> H.

FIG. 3E shows a case where it is judged whether or not the data capacity of the empty area of the FIFO memory 26 is larger than the threshold value S corresponding to the memory capacity of interest. In this case, one of the data input to the comparator 50 must be a value obtained by subtracting the current memory capacity from the total memory capacity of the FIFO memory 26, not the current memory capacity data output from the subtractor 49. . Therefore, FIG.
In order to realize the operation shown in (E), a subtractor 90 and a register 92 as shown in FIG. 9 are added. The register 92 stores the total capacity of all memory areas of the FIFO memory 26 as 10-bit data. Then, the subtractor 90 subtracts the current memory capacity data from the subtractor 49 and the total capacity data from the register 92, and outputs the output to one input terminal of the comparator 50.

In the embodiment shown in FIG. 3E, the amount of data transferred from the transmission system 10 is the CPU 22.
If it is known in advance, the threshold value stored in the register 52 corresponds to the amount of data 10
By storing the bit data and comparing the data with the memory capacity of the empty area by the comparator 50, X
It is possible to immediately determine whether ON can be transmitted to the transmission system 10 side.

In the present invention, the memory capacity determination device 28
Although the memory capacity determination device 28 and the FIFO memory 26 are combined with each other in order to facilitate the mounting on the circuit board by reducing the wiring, it is possible to precisely determine the memory capacity by adding to the FIFO memory 26. It is preferable to fabricate them in one chip, or to combine only the FIFO control section of the FIFO memory 26 and the memory capacity determination device 28 into one chip. If the comparator 50 does not require minute comparison of the memory capacity in units of 1 byte, the lower several bits of the register 50 may be fixed to "0".

The present invention is not limited to the above-mentioned embodiments, but various modifications can be made within the scope of the gist of the present invention. In the above embodiment, the memory capacity determination device 28
Although the memory combined with is the FIFO memory 26, the present invention is not limited to this and can be applied to a first-in first-out (FILO) memory in which the reading order is determined.

[0045]

As described above, according to the present invention, it is possible to precisely determine the capacity in which the data of the memory for performing the first-in first-out operation or the first-in first-out operation or the remaining capacity of the empty area is stored. Therefore, the operating efficiency of the system can be improved and the effective use of the memory area can be realized by reducing the interruption of the control means that controls the memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment apparatus to which the present invention is applied.

FIG. 2 is a block diagram showing an overall configuration of a device according to an embodiment.

3A to 3E are schematic explanatory diagrams for explaining setting of threshold values stored in the register shown in FIG.

FIG. 4 is a configuration diagram of a memory capacity determination device that determines a memory capacity by setting a threshold value shown in FIG.

FIG. 5 is a block diagram showing a configuration example of a memory capacity determination device that determines whether or not the memory capacity data from the FIFO memory and a threshold value match.

FIG. 6 is a block diagram showing a configuration example of a memory capacity determination device that determines that the memory capacity data output from the FIFO memory is larger than a threshold value.

FIG. 7 is a block diagram showing a configuration example of a memory capacity determination device that determines that the memory capacity data output from the FIFO memory is smaller than a threshold value.

FIG. 8 is a block diagram showing a configuration example of a memory capacity determination device that determines that the memory capacity data output from the FIFO memory is between an upper limit threshold and a lower limit threshold.

FIG. 9 is a block diagram showing a configuration example of a memory capacity determination device that determines whether or not the memory capacity of an empty area of the FIFO memory is larger than a threshold value.

[Explanation of symbols]

 10 transmission system 20 reception system 22 CPU 26 FIFO memory 28 memory capacity determination device 34 data transmission unit 40 dual port RAM 46 input counter 48 output counter 49 subtractor 50 comparator 52 register

Claims (3)

[Claims] 1. A memory for writing and reading data according to a first-in first-out operation or a first-in first-out operation, and a memory capacity detecting means for detecting a capacity in which the data in the memory is stored or a remaining capacity of an empty area as a memory capacity. And a storage unit that rewritably stores an arbitrary threshold value to be compared with the memory capacity, and a comparison unit that compares the memory capacity and the threshold value and outputs the comparison result. Characteristic memory system. 2. The memory control method using the memory system according to claim 1, further comprising a control unit that controls reading and writing of data from and to the memory, the control unit preliminarily storing the threshold value in the storage unit. A value is stored, the reading and writing of data to and from the memory thereafter is performed in parallel with the comparison means, and the data storage capacity or free area capacity of the memory is determined by receiving a notification from the comparison means. A memory control method using the memory system according to claim 1. 3. The memory control method using the memory system according to claim 1, further comprising a control unit that controls reading and writing of data from and to the memory, wherein the control unit is configured to read and write data. Whether a threshold value corresponding to the memory capacity of interest is stored in the storage means at a timing at which the memory capacity should be monitored, and whether the memory can be read or written based on the comparison result from the comparison means thereafter. 2. The memory control method using the memory system according to claim 1, wherein