JPH0315941A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of overrun and underrun by detecting the imminence of the full state or the empty state of a FIFO (first-in first-out) memory and outputting the detected result to outside. CONSTITUTION:A first holding means 4 holding address information of the FIFO memory 2 which is almost the full state and a second holding means 5 holding address information of the FIFO memory which is almost the empty state are provided in addition to the FIFO memory 2. Then, an imminence detection means 6 detects the imminence of the full state or the empty state in the FIFO memory 2 based on address information of data which is last written among present accumulation data of the FIFO memory 2, and holding address information of the first and second holding means 4 and 5, and the detection means 6 outputs the detected result to outside. Thus, overrun and underrun can previously be prevented.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit incorporating a FIFO (first-in, first-out) memory in which data is written and read in a fixed order.
The present invention relates to technology that is effective when applied to I (large-scale integrated circuits).

[Prior art]

When data is transferred between multiple devices or functional blocks that have different data processing speeds or transfer speeds, FIFO memory or the like can be used as a buffer memory to absorb the differences in capabilities and speeds. .

FIFO memory includes, for example, a memory cell array in which a plurality of memory cells are arranged in a matrix, an address decoder for addressing the memory cells included in the memory cell array, and a write/read unit that performs write/read operations on the addressed memory cells. It further includes a read address counter and a write address counter for internally generating an access address. The read address counter increments the data read address and supplies it to the address decoder, and the write address counter sequentially increments the write address for each data write operation and supplies it to the address decoder. Each address counter is constituted by a ring counter or the like whose number of bits corresponds to the storage capacity of the memory cell array.

When the data is empty, the values of the read address counter and the write address counter match, and each time a write is performed, the value of the write address counter is incremented, and each time a read is performed, the value of the read address counter is incremented. Ru. The values of the read address counter and write address counter are always monitored internally, and if the values match during a write operation, a new write cannot be accepted. Inform devices and functional modules. If the two values match during a read operation, the data to be read no longer exists, and this state is notified to the device or functional module from which the data is read by means of an empty signal.

A semiconductor integrated circuit incorporating such a FIFO memory is the communication LSI. SCN68562 (DUSCC) is mentioned. According to this LSI, for example, an interrupt signal is output to the outside when the internal FIFO memory is full in receive mode, or when the internal FIFO memory is empty in transmit mode. .

still. An example of a document describing a communication LSI incorporating a FIFO memory is Japanese Patent Application No. 149027/1982.

[Problem to be solved by the invention]

However, in conventional devices, an interrupt signal is output when the FI is actually in a full state or an empty state.
Since the state of the FO memory is communicated to the outside, it takes a certain amount of time for full or empty interrupt processing to start, and as a result, even though the FIFO memory is full, the FIFO memory is A state in which data is attempted to be written to the FIFO memory (this is called an overrun), or conversely, a state in which data is attempted to be read from the FIFO memory even though the FIFO memory is in an empty state. A condition (this is called an "underrun") occurs.

When overbalance or underrun occurs, the data related to the overrun or underrun becomes invalid, so the CPU must perform predetermined interrupt processing such as rewriting or rereading data, which places a heavy burden on the CPU. ．． An object of the present invention is to provide a semiconductor integrated circuit that can prevent overruns and underruns.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in addition to the FIFO memory, a first holding means for holding address information near the full state of the FIFO memory, and a second holding means for holding address information near the empty state of the FIFO memory, and further ．． FI
Detecting the impending full state or empty state in the FIFO memory based on the address information of the last written data among the currently stored data in the FO memory and the address information held in the first and second holding means. A semiconductor integrated circuit is constructed by providing an urgency detection means for outputting the detection result to the outside.

Here, after the urgency detection means detects the impending state of the FIFO memory to be full or empty,
In order to be able to change the time it takes for the FIFO memory to become full or empty during the actual festival, the above step 1.
It is recommended that the contents held in the second holding means be rewritten from outside. Further, instead of each of the above-mentioned means, the semiconductor integrated circuit may be configured with a FIFO register that enables external output of information regarding the current amount of data stored in the FIFO memory.

[For production]

According to the above-mentioned means, the address information near the full state of the FIFO memory, the address information near the empty state of the FIFO memory, and the address information of the last written data among the currently accumulated data of the FIFO memory are used. Based on this, the impending full or empty state of the FIFO memory is detected, and the detection result is output to the outside.This accelerates the start of interrupt processing for the full or empty state, and It acts to prevent overruns and underruns from occurring in semiconductor integrated circuits.

In addition, if the above FIFO register is provided, this FIFO
The output information of the FO register makes it possible to grasp the current amount of data stored in the FIFO memory, and this works to prevent overruns and underruns from occurring, as in the case described above.

〔Example〕

FIG. 1 shows a semiconductor integrated circuit which is an embodiment of the present invention. The semiconductor integrated circuit shown in the figure has a built-in FIFO memory 2 in which data is written and read in a fixed order, and is configured as a communication LSI, although it is not particularly limited. Communication LSI 2 shown in Fig. 1
0 and 30 are not particularly limited, but the data transmission path 5o
The communication LSIs 20 and 30 are connected by a CPU (central processing unit) 10 and 30, and serial data is exchanged via this data transmission path 50. These CPUIs 0 and 30 are connected to each other, and various calculation processes in data communication are performed.

The communication LS 130 is a FIFO mail 11-! J2(
7) In addition, serial-parallel conversion circuit 1, FIFO register 3, overrun register 4, and underrun register 5
It also has an urgency detection means 6.

The FIFO memory 2 has two systems: a transmission FIFO memory section 2a that stores data from the CPU 40 during data transmission, and a reception FIFO memory section 2b that stores data fetched from the outside during data reception. has a department.

FIGS. 2 and 3 schematically show storage areas of the reception FIFO memory section 2b and transmission memory section 2a, respectively. As shown in the figure, both of the memory sections have a storage area for eight parallel data, for example, eight words, although this is not particularly limited, and the addresses of the storage areas are indicated by 21 to 28. Data is written to both memory sections in ascending order of address numbers. Also,
Data is read from both memory sections starting from address 21, and the stored data from address 22 onward is sequentially shifted in the direction of decreasing address numbers each time the storage area at address 21 becomes empty.

The serial-parallel conversion circuit 1 converts serial data input via the data transmission line 50 into parallel data and outputs it to the receiving FIFO memory section 2b, and also
It has a function of converting the data output from the transmission FIFO memory section 2a into serial data and outputting it to the data transmission path 50.

The FIFO register 3 has two systems of FIFO corresponding to a transmitting FIFO memory section 2a and a receiving FIFO memory section 2b.
Registers, namely transmit FIFO register 3a and receive FI
FO register 3b, and information regarding the current accumulated data amount in the transmitting FIFO memory section 2a and the receiving FIFO memory section 2b, for example, each FIFO memory section 2.
The address information of the last written data among the current accumulated data of a and 2b is held by each of the registers 3a and 3b. Note that the address information of the last written data among the current accumulated data in each FIFO memory section 2a, 2b can be easily detected from the output of the address counter in each FIFO memory section 2a, 2b.

The overrun register 4 is a register that holds address information when the receive FIFO memory section 2b in the FIFO memory 2 is in a nearly full state, and the underrun register 5 is a register that holds address information for the nearly full state of the receive FIFO memory section 2b in the FIFO memory 2.
This is a register that holds address information near the empty state of the IFO memory section 2a. The address information settings for the overrun register 4 and underrun register 5 are as follows:
This is performed by the CPU 40 via the internal data bus 7 and the external data bus 8 connected thereto.

The address information near the above full state is the above F
It refers to the address before the IFO memory 2 becomes full or empty, and is determined by taking into consideration the time until the CPU 40 starts interrupt processing regarding the full or empty state. Here, the first and second holding means in the present invention each perform the above-mentioned overrun registration.

Furthermore, the urgency detection means 6 detects the impending full state or empty state of the FIFO memory 2 based on the outputs of the FIFO register 3, overrun register 4, and underrun register 5, and outputs the detection result to the outside. Comparison of the output value of the transmit FIFO register 3a and the output value of the underrun register 5, and the comparison of the output value of the receive FIFO register 3a
It has a comparison circuit 6a that compares the output value of the register 3b and the output value of the overrun register 4, and an interrupt control circuit 6b that outputs a predetermined interrupt control signal based on the comparison result of the comparison circuit 6a. It is determined that

Here, when the comparison circuit 6a detects a match between the output value of the transmission FIFO register 3a and the output value of the underrun register 5, the interrupt control circuit 6b outputs the empty state impending interrupt signal 9, and the Comparison circuit 6a
When a match between the output value of the reception FIFO register 3b and the output value of the overrun register 4 is detected, the interrupt control circuit 6b outputs a full state impending interrupt signal 10. These interrupt signals 9 and 10 are
The CPU 40 learns of the impending full or empty state of the FIFO memory 2 by inputting this interrupt signal 9 or 10, and starts interrupt processing to deal with the full or empty state within a predetermined time. do.

Note that the communication LSI 20 is also configured in the same manner as described above.

Next, the operation of this embodiment will be explained.

Data transfer from the communication LSI 20 to the communication LSI 30 is performed as follows.

Serial data transmitted from the communication LSI 20 via the data transfer path 50 is sent to the serial-parallel conversion circuit 1.
is converted to parallel data by
The data are sequentially stored in the FO memory section 2b. Accordingly, the contents held in the reception FIFO register 3b are updated by the address information of the last written data among the currently accumulated data in the reception FIFO memory section 2b.

That is, as shown in FIG. 2, parallel data is written in order from address 21 of the reception FIFO memory section 2b, and the state in which data is written to the storage area at address 28 is called a full state (accumulated data is full). state), then
The contents held in the receive FIFO register 3b are the contents of the receive FIFO register 3b.
21.22,2 according to data writing to memory section 2b
3, etc. are updated.

On the other hand, the overrun register is preset by the CPU 40 with a value indicating address information near the full state of the reception FIFO memory section 2b, for example, address 26, and data accumulation in the reception FIFO memory section 2b progresses and the reception register 3b is retained. When the value and the value held in the overrun register 4 match, it is detected by the comparator circuit 6a, and the detection result is transmitted to the interrupt control circuit 6b. Then,
This interrupt control circuit 6b generates a full state imminent interrupt signal 1.
0 is generated and transmitted to CPU 40. CPU
40 learns from this interrupt signal 10 that the receive FIFO memory unit 2b is about to become full, and shifts to interrupt processing to deal with the full state. In this interrupt processing, the CPU 40 accesses the reception FIFO memory section 2b of the communication LSI 30 and reads the reception data. This data reading is performed in the order in which data is written to the reception FIFO memory section 2b. That is, the storage data at address 21 is read out first, and when the storage area at address 21 becomes empty, the storage data at address 22 is read out from address 21.
When the storage area at address 22 becomes empty, the storage data at address 23 is moved to address 22. Similarly, the data stored at address 24 is shifted to address 23, the data stored at address 25 is shifted to address 24, and the data stored at address 26 is shifted to address 25. Such a data shift is performed every time data is read from the receiving FIFO memory section 2b and the storage area at address 2 becomes empty.

In this way, the interrupt signal 10 can be sent to the overrun register 4 to the CPU 40 before the address information memory section 2b of the reception FIFO memory section 2b, which is close to the full state, actually becomes full. Receive FIF to
Reading of data in the O memory section 2b can be started. Here, the parallel data successive output speed from the reception FIFO memory section 2b is faster than the serial data transmission speed on the data transmission path 50, and therefore, as described above, the reception FIFO
By starting reading data in the receive FIFO memory section 2b before the memory section 2b becomes full, overruns can be prevented from occurring.

Next, data transfer from the communication LSI 30 to the communication LSI 20 will be explained.

CPU via external data path 8 and internal data bus 7
The parallel data transferred from 40 is sequentially written into the transmission FIFO memory section 2a. And this send FIFO
Send F every time parallel data is written to the memory section 2a.
The contents held in the IFO register 3a are updated by the address information of the last written data among the current seven resuscitation data in the transmission FIFO memory section 2b.

As shown in FIG.
The stored data at address a is read from address 21, as in the case of reading data from the reception FIFO memory section 2b, and each time the storage area at address 21 becomes empty, the stored data from address 22 onward is sequentially shifted. Ru. Along with this data shift, the contents held in the transmission FIFO register 3a are updated as 28, 27, 26, . . . .

On the other hand, the underrun register 5 is preset by the CPU 40 with a value indicating address information near the empty state of accumulated data in the transmission FIFO memory section 2a, for example, address 22, and data reading from the transmission FIFO memory section 2a progresses. When the value held in the transmission FIFO register 3a and the value held in the underrun register 5 match, it is detected by the comparison circuit 6a, and the detection result is sent to the interrupt control circuit 6.
transmitted to b. Then, this interrupt control circuit 6b generates an empty state impending interrupt 4a No. 9, which is
It is transmitted to PU40. The CPU 40 receives this interrupt signal 9.
As a result, the impending empty state of the transmission FIFO memory section 2a is known, and the process shifts to interrupt processing to deal with the empty state. In this interrupt processing, the CPU4
Data for transmission is transferred from 0 to the transmission FIFO memory section 2a, and is written into the transmission FIFO memory section 2a.

Note that the data read from the transmission FIFO memory section 2a is converted into serial data in the serial-parallel conversion circuit 1, and then sent to the communication LS via the data transmission path 50.
I20. The processing in this communication LSI 20 is similar to the data reception in the LSI 30 described above.

In this way, by causing the underrun register 5 to hold the address information near the empty address of the transmission FIFO memory section 2a, the interrupt signal 9 can be sent to the cPUh before the transmission FIFO memory section 2a becomes empty. This allows the sending FIF to be sent before the empty state.
Data writing to the O memory section 2a can be started. Here, the parallel data writing speed to the transmission FIFO memory section 2a is faster than the serial data transmission speed in the data transmission path 50, and therefore, as described above, the parallel data writing speed to the transmission FIFO memory section 2a is
By starting data writing to the transmission FIFO memory section 2a before the memory section 2a is in an empty state,
Underruns can be prevented from occurring.

According to the above embodiment, the following effects can be obtained.

(1) By causing the overrun register 4 to hold address information near the full state of the receiving FIFO memory section 2b, the interrupt signal 10 can be sent to the CPU 40 before the receiving FIFO memory section 2b reaches the full state. As a result, it is possible to start reading data in the reception FIFO memory section 2b before it becomes full, so that overruns can be prevented from occurring. Furthermore, by causing the underrun register 5 to hold address information near the empty state of the transmission FIFO memory section 2a, the transmission FIFO
Before the FO memory unit 2a becomes empty, the CPU 4
The interrupt signal 9 can be sent in response to 0, and data writing to the transmission FIFO memory section 2a can be started before it becomes empty, thereby making it possible to prevent the occurrence of an underrun.

If overruns and underruns can be prevented from occurring in this way, it is possible to avoid situations where data related to overruns and underruns become invalid, and to avoid performing predetermined interrupt processing such as rewriting or rereading data. The load on the CPU can be reduced.

(2) Also, unless an interrupt signal related to a full state or an empty state is generated from the interrupt control circuit 6, the CP
Even if U40 is caused to execute other arithmetic processing, the interrupt processing regarding the full state and empty state described above is not affected, so that the utilization efficiency of the CPU 40 can be improved.

(3) Furthermore, by making it possible to rewrite the contents held in the overrun register 4 and the underrun register 5 from outside the LSI 30, the FIFO memory 2 is actually stored after detecting the impending full state or empty state of the FIFO memory 2.
The time it takes for the memory 2 to reach a full state or an empty state can be changed from outside the LSI 30.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and can be variously modified without departing from the gist thereof.

For example, in the above embodiment, data is read from the FIFO memory 2 from address 2l, and when the storage area at address 21 becomes empty, the stored data from address 22 onward is sequentially shifted. ,F
Depending on the IFO memory, without shifting the data,
Some devices enable first-in, first-out data by controlling read and write addresses based on ring counter output. The present invention can also be applied when such a FIFO memory is used. When using such a FIFO memory, the address in the full state and the address in the empty state are not constant, so after reading data, the values held in the overrun register 4 and underrun register 5 are reset, and the next full state is set. Prepare for state and empty state interrupt processing. For example, in FIG. 2, the overrun register 4 holds a value indicating address 26,
When the value held in the overrun register 4 and the value held in the reception FIFO register 3b match, the data from addresses 21 to 26 will be read out. After reading this data, the write address control goes through one cycle and the address A state in which new data is written to 26 is a full state. Therefore, after reading the data, the overrun register 4 contains an address close to the full state, for example, address 2.
The value indicating 4 will be reset. In this way, each time data is read, the value held in the overrun register 4 is
Reset by 0.

Further, the value held in the FIFO register may be sampled at a predetermined period by the CPU. FIG. 4 shows an embodiment in this case.

The FIFO register 13 has two systems of FIFOs corresponding to a transmitting FIFO memory section 2a and a receiving FIFO memory section 2b.
It consists of an O register, that is, a transmit FIFO register 13a and a receive FIFO register 13b.
Information regarding the current amount of accumulated data in the memory section 2a and reception FIFO memory section 2b is stored in each FIFO register 1.
3a and 13b. Here, each FIF above
Information regarding the current amount of accumulated data in the O memory sections 2a and 2b includes the transmission FIFO memory section 2a and the receiving {;! F
Includes address information of the last written data among the current accumulated data in the IFO memory section 2b, and information on the number of accumulated data obtained based on the write address and read address in each FIFO memory section 2a, 2b. It will be done.

Each FIFO register 13a, ↓3b is connected to the CPU 40 by an internal data bus 7 and an external data bus 8, so that the content held in each register 13a, 13b can be grasped by the CPU 40.

In the above structure, the CPU 40 samples the value held in the transmission FIFO register 13a or the reception FIFO register 13b at a predetermined period, and stores the data in the transmission FIFO memory section 2a or the reception FIFO memory section 2b based on the sampling result. Determine whether the state is approaching an empty state or a full state. In this determination, if it is determined that the state is close to empty, the transmission F of the data transferred from the CPU 40 is
If writing to the IFO memory section 2a is performed and it is determined that the state is close to full in the above determination, the CP
Data is read from the reception FIFO memory 2b according to instructions from U40.

In this way, the contents held in the FIFO register 13 are transferred to the LSI 3
If configured to be able to output to the outside of 0, this FIFO
By sampling the contents held in the register 13 by the CPU 40, it is possible to start writing or reading data before the FIFO memory actually reaches the empty state or the full state. Therefore, overruns and underruns can be prevented from occurring, and the load on the CPU 40 can be reduced.

Note that the contents held in the FIFO register 13 may be output to the outside using a dedicated line and a dedicated external terminal instead of using the internal data bus 7.

Furthermore, in the above embodiment, the transmission FIFO memory section 2a and the reception
Although the description has been given of a device including a FIFO memory section 2b, a single FIFO memory section can also be used for both transmission and reception.

In the above explanation, the invention made by the present inventor was mainly applied to communication LSI, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and the present invention is not limited to this, and It can also be widely applied to data processing devices and the like. [Effects of the Invention] The present invention can be applied to at least conditions that prevent the occurrence of overruns and underruns in FIFO memories. [Effects of the Invention] A brief explanation is as follows.

In other words. By detecting the impending full or empty state of the FIFO memory before it actually becomes full or empty and outputting the detection results to the outside, overruns and underruns of the FIFO memory can be prevented. This has the effect that it can be prevented.

In addition, if the contents held in the first and second holding means can be rewritten externally, the impendingity detection means detects the impending empty state or full state of the FIFO memory, and then the FIFO memory actually becomes empty. You can arbitrarily change the state or the time it takes to reach the full state.

Furthermore, an FI that holds information regarding the current amount of data stored in the FIFO memory and enables external output of the held contents.
Even when an FO register is provided, the F
Overruns and underruns of the IFO memory can be prevented from occurring.

[Brief explanation of the drawing]

1 is a block diagram of an embodiment of the semiconductor integrated circuit according to the present invention, FIGS. 2 and 3 are explanatory diagrams schematically showing the storage area of the FIFO memory in the device of this embodiment, and FIG. It is an example block diagram. 2...FIFO memory. 3.13... FIFO register, 4... Overrun register, 5... Underrun register, 6... Imminence detection means. 20.30...
Communication LSI.

Claims (3)

[Claims] 1. FI where data is written and read in a fixed order
In a semiconductor integrated circuit equipped with an FO memory, the above FI
a first holding means for holding address information near a full state of the FIFO memory; a second holding means holding address information near an empty state of the FIFO memory;
Detecting the impending full state or empty state of the FIFO memory based on the address information of the last written data among the currently stored data of the FO memory and the address information held by the first and second holding means. , and an urgency detection means for outputting the detection result to the outside. 2. 2. The semiconductor integrated circuit according to claim 1, wherein the contents held in said first and second holding means are configured to be rewriteable from the outside. 3. FI where data is written and read in a fixed order
In a semiconductor integrated circuit equipped with an FO memory, the above FI
A semiconductor integrated circuit having a FIFO register that holds information regarding the current amount of data stored in an FO memory and allows the held contents to be output to the outside.