JPS6194142A - First-in/first-out type memory - Google Patents

Abstract

PURPOSE:To attain a first-in/first-out (FIFO) type memory of a high speed and large capacity by applying a system where data are written and read to the RAM addresses in the ascending order and therefore using a RAM in place of a transfer register. CONSTITUTION:The data supplied from outside via a signal line 105 are latched by an input register 17. Thus the data given from a control circuit 19 cannot be supplied and the data of the register 17 are written to a RAM11 via an address counter 12. Thus the input of data is possible again with a signal line 102. When a writing action is over, an up-down counter 14 is counted up. Then a maximum value detecting circuit 15 checks whether the buffer of the RAM11 is filled up or not. If the buffer is filled up, an input unable state is set. While the output on a signal line 106 is set under an unable state when it is decided by a minimum value detecting circuit that no data to be read out exists.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is applicable to first-in/first-in systems that require high speed and large capacity.
It relates to first-out (FIFO) type memory. - (Prior Art) FIFO type memorandum memory has conventionally been configured by providing multiple stages of transfer registers from input registers to output registers, as shown in Figure 2. In FIG. 2, 21 is an input register, 22 to 24 are transfer registers, 25 is an output register, and 26 is a control circuit.

In FIG. 2, when the contents of the input register 21 are empty, F
The IFO type memorandum becomes available and requests data from the outside. Here, the input data is input to the input register 21.
When the input strobe is input, the contents of the input data register 21 becomes full and input becomes impossible. When there is data in the input register 21, the data is transferred to the first-stage transfer register 22, and the contents of the input register 21 become empty again and the ninth data is requested. The data in the first stage transfer register 22 is transferred when the second stage transfer register 23 is empty, and the first stage transfer register 22 is empty and waits for the next data from the input register 21. .

By repeating the above operations and inputting data to the transfer register 22, the data is transferred to the output register 25. At this time, the FIFO type memory becomes ready for output and an external request is made. The data in the output register 25 is taken over by the output strop, and at the same time it is taken up, the data is transferred to the FIFO.
The shape memory becomes unable to output.

(Problem to be Solved by the Invention) In a FIFO memory that operates as described above, n stages of registers 22 to 24 are operated after data is set in input register 1 until data is output to output register 5. The disadvantage is that it takes a long time to go through the route. Furthermore, since the respective registers are connected in series, transfer control between the registers is complicated, making it unsuitable for increasing capacity.

An object of the present invention is to eliminate the above-mentioned drawbacks by adopting a method of writing and reading data to and from RAM addresses in ascending order using a write address and a read address. The purpose is to provide a complete store-out (FIFO) type memory.

(Means for Solving the Problems) The first-in/first-out memory according to the present invention includes an input register, an output register, a RAM, a write address counter, a read address counter, an up/down counter, and a minimum value detector. This configuration includes a circuit and a maximum value detection circuit.

The input register is used to latch data from the outside.

The output register is used to latch data to the outside.

The RAM is for storing data input to the input register.

The write address counter provides a write address to the RAM and is incremented each time a write is made.

The read address counter is used to give a read address of the RAM\ and count up each time it is read.

The up/down counter is for counting the difference in the number of writes/reads.

The minimum value detection circuit is for detecting the minimum value of the output of the up/down counter and inhibiting the read operation.

The maximum value detection circuit is for detecting the maximum value of the output of the up/down counter and inhibiting a write operation.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating one embodiment of a first-in/first-out (FIFO) type memory according to the present invention. In FIG. 1, 11 is a RAM 112 is a write address counter, 13 is a read counter, 14 is an up/down counter, 15 is a maximum value detection circuit, 16 is a minimum value detection circuit, 17 is an input register, 18 is an output register,
19 is a control circuit.

In FIG. 1, data input from the outside via a signal line 105 is latched into an input register 17 by an input strobe. When the data is latched, the control circuit 19
The data from will be in a state where it cannot be input. input register 1
The data on 7 is written to the RAM 11 at the address indicated by the write address counter 12. When this writing is performed, the signal line 102 becomes ready for input again.

When writing is completed, the up/down counter 14 counts up the write address. The value of the up/down counter 14 is used by the maximum value detection circuit 15 to detect whether data has been written to the full buffer capacity of RAMI i. RAMI
When it is detected that the contents of 1 are full, the control circuit 19 disables input on the signal line 105 and prohibits the input operation. Conversely, when the minimum value detection circuit 16 detects that there is no data stored in the RAMI 1 buffer and there is no data to be read, the value of the up/down counter 14 is changed to the value of the up/down counter 14 on the signal line 106 by the control circuit 19. Disables output and prohibits output operation.

If read data remains in RAMII, the data is read from the address indicated by the read address counter 13 at a timing that does not match the write operation, latched into the output register 18, and the output enable signal on the signal line 104 is enabled. state.

Data is not read out in the output enabled state. When the output is possible, data can be read to the outside. When the above data is read by the output strobe on the signal line 103, the output enable signal on the signal line 104 immediately changes to the disabled state and the next data read operation begins. When reading to the output register 18 is completed, the read address counter 15 counts up and the up/down counter 14 counts down. The up/down counter 14 performs up/down operations during the write operation and read operation described above, and counts the amount of data to be read onto the RAM 11.

(Effects of the Invention) As explained above, the present invention employs a method of writing and reading data to and from RAM addresses according to the write address and read address.
M can be used in place of a transfer register, and there is an effect that a high-speed, large-capacity FIFO type memory can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a FIFO type memory according to the present invention. FIG. 2 is a block diagram illustrating -f4J of a FI'FO type memory according to the prior art. 11...Tatami RAM 12-14...Counter 15...Maximum value detection circuit 16...Minimum value detection circuit 17.11.21-25...Register 19.26...
Furu control circuit

Claims (1)

[Claims] An input register for latching data from the outside, an output register for latching data to the outside,
a RAM for storing data input to the input register; a write address counter for providing a write address to the RAM and counting up each time a write is provided; and a write address counter for providing a read address to the RAM and for each read. A read address counter for counting up, an up/down counter for counting the difference between the number of writes/reads, and a minimum value for detecting the minimum value of the output of the up/down counter and prohibiting a read operation. A first-in/first-out type memory comprising: a detection circuit; and a maximum value detection circuit for detecting the maximum value of the output of the up-down counter and inhibiting a write operation.