JPS63245745A - Buffer storage controller - Google Patents

Abstract

PURPOSE:To speed up data reading by transferring the data of one block data with a fixed width following the one-block data to a buffer storage device. CONSTITUTION:In case of storing data in a buffer storage, data for one block (6 bytes) and following 8 bytes are transferred from a main storage device to store the data of 72 bytes continued in the main storage in the buffer storage. When the data in the main storage device are transferred to the buffer storage, the data are stored in data parts 107-109 of the buffer storage. When data corresponding to an address applied to an address register 101 exist in the buffer storage, the leading data are read out from the buffer storage data part 108 and the leading data in the succeeding block are simultaneously read out from the data part 109.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer storage control device, and more particularly to a buffer storage control device suitable for reading data spanning blocks on a buffer storage device in a single access. .

[Conventional technology]

A buffer storage device generally stores data on main memory in one
Data is held in block units, and when read from the buffer storage device, the data width is a fixed capacity of one block or less, and only one specific block can be accessed in one access to the buffer storage device.

Generally, an information processing device requires a large amount of data that straddles blocks.

Therefore, in the above-mentioned buffer storage device, it is necessary to access the buffer storage device twice.As a solution to this problem, for example, as described in Japanese Patent Application Laid-Open No. 54-8937,
By dividing the buffer memory into two and alternately allocating blocks in the main memory to the two buffer memories, it is possible to read data that spans between blocks in one access. Furthermore, as described in Japanese Patent Laid-Open No. 55-20826, by providing a next block management unit that manages whether the data of the next block is stored in the buffer memory, it is possible to cross blocks with one access to the buffer memory. It is now possible to read data.

[Problem that the invention seeks to solve]

The conventional technique described above has a problem in that if the next block is not in the buffer storage device, data must be transferred from the main storage device, and it takes a long time to complete the data.

An object of the present invention is to ensure that the data of the next block exists in the buffer storage device, and to read out data spanning blocks by accessing the buffer storage device once.

[Means for solving problems]

The purpose of the above is to transfer one block of data and the following fixed width data (the byte width transferred from backup storage to an arithmetic unit, etc.) to the buffer storage when transferring data from the main storage to the buffer storage. However, in the buffer storage device, this can be achieved by providing a small capacity buffer storage device with a constant width outside the block.

[Effect]

□ The present invention detects data reading that spans blocks on a buffer memory, and uses the detection information to read data from the buffer memory outside the block, thereby reading data by one access to the buffer memory. can be arranged.

〔Example〕

The present invention will be explained below with reference to FIG. 1, which is an embodiment of the present invention.

FIG. 1 shows an embodiment of a portion of a buffer storage controller that is relevant to the present invention. In FIG. 1, address register 1o1. Address array section 1o configuring buffer storage
5. Configure buffer storage, 6.

data sections 107, 108 and +09, comparator 110
, data select circuit 112, read data register 1
13 and 114, a shift circuit 115 and a data register 116 are shown.

In this example, the read data width of the buffer storage is 8 bytes, and one block is 64 bytes. Data portions +07 and 10B of the buffer storage are divided into two parts of the buffer storage, and are consecutively allocated in units of 8 bytes. The data section 109 of the buffer storage has a data width of 8 bytes, and exists at a rate of one per block of buffer storage. This relationship is shown in FIG. 2, and the buffer storage is capable of storing nine consecutive pieces of data (72 bytes) in the main memory.

Returning to FIG. 1, normal buffer storage access will be explained. Bits 20-25 of the address applied to address register 101 access buffer storage address array 105 and supply the stored address information to comparator ++0. On the other hand, the upper two bits (bits 26 to 2) are added by adding 1 to the pins 20 to 25 of the address register +0+ by the 3-pin adder 104 of bits 26 to 28.
7) is added to bits 2o to 27 to access the data section +07 of the buffer storage and read the data. Further, the data portion 10B of the buffer storage is accessed using pins 20 to 27 of the address register 101 to read data. As a result, 1 from the buffer storage data 51o7 and 1081C
Six bytes of data are read in one access, arbitrary eight bytes of data are aligned by the shift circuit 115, and the data is set in the data register 116.

The comparator 110 determines whether data corresponding to the address given to the address register 101 exists in the buffer memory, and the comparator 110 determines whether data corresponding to the address given to the address register 101 exists in the buffer memory. = 1; Valid), the stored address and the given address are compared and match.

Determine inconsistency.

If it is determined that they match, the data read from the data portions 107 and 108 of the buffer storage becomes valid because the data exists in the buffer storage. However, comparator 11
If the determination of 0 indicates a mismatch, it means that the data at the given address does not exist in the buffer storage, and a predetermined data transfer request is issued to the main memory. (Not shown) In the above buffer storage access, the maximum required 8-byte data is always obtained as long as the data is within one block of the buffer storage. However, when the required data straddles block boundaries as shown in FIG. 3, the data cannot be obtained by accessing the buffer memory - times.

In the present invention, the data portion 1 of the buffer storage has the size of the read data width, which is 1-block of the buffer storage.
By having 09, necessary data can be obtained in one access even if the data spans blocks.

1 from main memory when storing data in buffer memory
By transferring a block (64 bytes) and subsequent data (8 bytes), 72 consecutive bytes of data on the main memory are stored in the buffer memory.

Suppose that there is data in the main memory as shown in Figure 3 and the data is transferred to the buffer memory, the data is transferred to the data sections 107, 108 and 10 of the buffer memory as shown in Figure 2.
It is stored in 9.

Assuming that the address given to the address register 101 is as shown in FIG. 3 as "1 data required", if data exists on the buffer storage, the first data is stored in the buffer storage data section 108 in FIG. At the same time, the first data of the next block is read from the buffer storage data section 109. Here, the data is supplied to a block cross determination circuit 117 that determines whether bits 26 to 28 of the address register 101 are addresses at block boundaries. The judgment output is supplied to the data select circuit 112. The block cross judgment circuit 117 judges that the next data of the block is necessary (all pictographs 26-5-28 are 11
), the buffer storage data 109 is selected by the select circuit 112 and set in the read data register 113, the data is aligned by the shift circuit 115, and the data across blocks is set in the data register 116. .

〔Effect of the invention〕

According to the present invention, even when reading data across blocks on the buffer storage, the data can be obtained by accessing the buffer storage once, so that high-speed data reading can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a conceptual diagram of data stored in a buffer according to the present invention. FIG. 3 is an explanatory diagram showing block boundaries. 101... Address register, 105... Buffer storage address array, 107-109... Buffer storage data section, 110... Comparator, 112... Select circuit, 117... Block cross determination circuit, 115
,・,shift circuit. Figure 1 ffH Figure 2 nR Figure 3

Claims (1)

[Claims] 1. A buffer storage device comprising a data section for storing data in a main memory device in units of blocks and an address array section for storing address information on the main memory device for the data;
In a buffer storage control device comprising a shift circuit for aligning data read from the buffer storage device to the position of the first byte, By providing capacity buffer storage, a circuit for detecting whether data read from the buffer storage device crosses blocks of the buffer storage device, and a circuit for selecting data read from the buffer storage device, it is possible to cross blocks on the buffer storage device. A buffer storage control device characterized in that data can be obtained by accessing the buffer storage device once.