JPH01177661A - Data transferring device - Google Patents

Abstract

PURPOSE:To transmit data according to requests from many peripheral processing units by obtaining a means to refer to the contents of a vector table corresponding to an activation request and all pieces of information necessary for transferring the data from the contents. CONSTITUTION:When a data transfer controller (DTC) 2 recognizes a data transfer requesting signal 21, it calculates a first address (to indicate a storage place in a first memory 3) corresponding to a vector number 20 and reads a second address (to indicate the storage place in a second memory 4) corresponding to the vector number 20 from the first memory 3. Namely, at the time of obtaining a transferring source address, a transferring destination address, the number of transferred words, the word length of the data, and transfer information, first, the transfer information and the work length of the data are obtained, thereafter, the transferring source address, transferring destination address and number of transferred words are obtained, and the data are transferred. Thus, the data can be transferred according to the requests from many peripheral processing units by means of a few hardwares.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transfer device that transfers a large amount of data, and in particular, the present invention relates to a data transfer device that transfers a large amount of data. The present invention relates to a data transfer device equipped with a method and means that can support various data transfer formats.

[Conventional technology]

An example of a conventional data transfer device that can transfer large amounts of data is the Hitachi Microcomputer Data Book: 8.
/16-bit microcomputer peripheral LSI, Showa 6
September 0, as shown on pages 389 to 442.
MAC (DjrectMemory Access
In this conventional example, the address information of the data transfer source and the address information of the data transfer destination must always be stored in a register provided within the data transfer device. Furthermore, as the number of other processing devices requesting data transfer increases, the number of channels capable of data transfer must be increased.

[Problem to be solved by the invention]

The above conventional example requires many channels to transfer data in response to requests from a large number of peripheral processing devices, so hardware such as registers increases, making it impossible to obtain an inexpensive data transfer device. ).

According to the conventional example, in order to transfer data in response to requests from a large number of peripheral processing units, at least a transfer source address register that stores the address of the data transfer source and a transfer destination register that stores the address of the data transfer destination are required. Address registers and transfer word number registers for storing the number of data transfer words are required for the number of peripheral processing units requesting data transfer, resulting in an increase in hardware.

An object of the present invention is to provide a data transfer device that can transfer data in response to requests from a large number of peripheral processing devices with a small amount of hardware.

Another object of the present invention is to provide a data transfer device equipped with a method and means capable of supporting various data transfer formats when transferring data in response to requests from a large number of peripheral processing devices.

Another object of the present invention is to provide a data transfer device with a method and means capable of operating in response to interrupt requests from multiple peripheral processing devices.

Another object of the present invention is to provide a data transfer device that includes a method and means that do not update an interrupt vector table every time data is transferred.

Another object of the present invention is to provide a data transfer device in which an area for storing all information necessary for data transfer can be freely changed.

[Means to solve the problem]

The above purpose is to collect all information necessary for data transfer, i.e.
A transfer source address indicating the memory location where the data to be transferred is stored, a transfer destination address indicating the transfer destination memory location, the number of transfer words of the transfer data, the word length of the transfer data, and the number of transfer words. A storage device is provided for storing transfer information indicating means for obtaining the transfer source address and transfer destination address of the next data to be transferred when there is a plurality of data, and all information necessary for the data transfer is stored in the memory. A vector table is provided to store an address indicating where the data is stored in the device, and when there is a request to start data transfer, a means for referring to the contents of the vector table in response to the request to start data transfer is provided, and a means for referring to the contents of the vector table in response to the request for starting data transfer, and a means for starting the data transfer from the contents. This is achieved by providing a means to obtain all the necessary information.

In addition, when obtaining the transfer source address, transfer destination address, number of transfer words, word length of data to be transferred, and transfer information, first obtain the transfer information and word length of the data, and then obtain the transfer source address and transfer destination address. By obtaining the number of transferred words and transferring the data.

achieved.

Furthermore, it is provided with a means for temporarily storing the contents shown in the above-mentioned header table, and by storing the transfer source address, transfer destination address, and transfer word count status after the data transfer is completed in the storage device, it is possible to can be achieved.

[Effect]

When a plurality of interrupt requests are generated from a large number of peripheral processing devices, the data transfer device according to the present invention selects the request with the highest processing priority among the interrupt requests based on a predetermined priority criterion, and Determine whether the request is an interrupt request to guide a program that performs predetermined interrupt processing or a data transfer request to perform data transfer, and if it is a data transfer request, send a data transfer request signal. The address of the vector table is calculated from the vector number corresponding to , and the contents indicated by this address are read. Next, the storage device is accessed using this read content as an address, and first, when the word length of the data to be transferred and the number of words to be transferred are plural, the transfer source address and transfer destination address of the data to be transferred next are determined. Read the transfer information indicating the means to obtain the information. Next, the transfer source address indicating the memory location where the data to be transferred is stored is read. Next, the memory indicated by this transfer source address is accessed to obtain the data to be transferred. At this time, if the transfer information indicating the means to obtain the source address of the data to be transferred next instructs to update the source address, the data is transferred to the memory location where the source address is stored. Write the updated transfer source address according to the word length of the data.

Next, the transfer destination address indicating the memory location of the transfer destination is read. Next, the memory indicated by this transfer destination address is accessed and the data to be transferred is written. At this time, if the transfer information indicating the means to obtain the transfer destination address of the next data to be transferred instructs to update the transfer destination address, the data is transferred to the memory location where the transfer destination address is stored. Write the updated transfer destination address according to the word length of the data. Finally, read the number of words to be transferred and update the number of words to be transferred. The updated number of transferred words is written to the memory location where the number of transferred words was stored. Further, it is determined whether the updated number of transferred words is O or not, and if it is 0, the data transfer device itself issues an interrupt request, thereby completing the series of processing.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.

FIG. 1 shows the configuration of a data transfer device according to the present invention. It consists of an interrupt controller 1, a data transfer controller 2 (hereinafter referred to as DTC), a first memory 3, a second memory 4, an address bus 5, and a data bus 6.

The interrupt controller 1 receives a first interrupt request signal 10,
From among a plurality of interrupt request signals such as the second interrupt request signal 11, the interrupt controller 1 generates a vector number 20 corresponding to the highest priority interrupt request according to priority determination information in the interrupt controller 1.
Data request signal 2 according to information indicating whether or not to perform data transfer corresponding to the interrupt with the highest priority among
Generates 1. When the DTC 2 recognizes the data transfer request signal 21, it transfers the first address (
A second address (indicating a storage location in the second memory 4) corresponding to vector number 20 is read from the first memory 3. The second memory 4 stores information necessary for data transfer, and executes data transfer while reading and updating the information according to the second address. The first memory 3 is
A storage device that stores addresses (vector addresses) corresponding to vector numbers, and is used for data transfer as well as interrupt vector addresses for the central processing unit (not shown, hereinafter referred to as CPU), system vector addresses, and other It stores information such as programs and data. The second memory 4 is a storage device that stores data transfer information.
It is also used as a data area for the PU (not shown). In this embodiment, the first. Although two second memories are used, a single memory can also be shared. The address bus 5 and the data bus 6 are connected to the interrupt controller 1,
It is connected to a data transfer controller 2, a first memory 3, a second memory 4, a CPU, and various peripheral devices, and is used for data transfer.

Next, the registers built into the DTC2 will be explained.

The DTC 2 includes four registers shown in FIG. 2, and these registers store transfer control information for one channel. Transfer control information for a plurality of channels is stored in the memory 4, and when a transfer request occurs, register information corresponding to each channel is transferred from the memory 4 to a built-in register, and is saved in the memory 4 after the data transfer is completed.

FIG. 3(A) and FIG. 3(B) illustrate each register. The functions of each register are as follows.

(1) Transfer mode register (DMR) 100/16 bits Specifies the operation mode of DTC2. The function of each bit is as follows.

(a) S Z (bitl 5): Indicates the size of data transfer.

SZ=O: Bye 1 to transfer 5Z=1: Word (2 byes 1 to) transfer (b) SI (bjt14): Sets source address increment mode.

S = O: Do not increment.

5I=1: +1 if SZ, +2° if 5Z=4 (c) DI (bitl 3): Sets the increment l-mode of the destination address.

DI=O: Increment 1 to no.

DI=1: +1 if 5Z=O, +2° if 5Z=1 (2) Transfer source address register (DSR) 101...1
This is a register that specifies the 6-bit transfer source address. DMR10
When the SI pin of 0 is 1, 1 (when SZ=O(7)) or 2 (when SZ=1) is automatically added after one data transfer. When the SI bit is O, the address does not change.

(3) Transfer destination address register (DDR) 102...1
6 bits 1~ This is a register that specifies the transfer destination address.When DMRloo's DI bits 1~ are 1, 1 bit is set after one data transfer.
(if SZ=O) or 2 (if SZ=1),
It will be added automatically.

When DI pin 1- is 0, the address does not change.

(3) Transfer word count register (DCR) 103: This register specifies the number of 16-bit data transfers.

It is possible to specify 1 to 65536 times. If 0 is specified, 65536 is assumed. When one transfer is completed, it is automatically set to -1, and when the designated transfer is completed, it becomes 0. At this time, the DTC 2 generates an interrupt to the CPU (not shown). As the interrupt vector number, the same values (32 to 63) as for the normal interrupt for the cause that activated the DTC2 are used.

Although this embodiment has four registers, the number of registers can be reduced by transferring data from the memory 4 as needed. For example, since the transfer source address and transfer destination address are not used at the same time, internal registers can be shared by updating the memory contents each time they are updated.

That is, it is not essential whether or not these registers are built into the DTC2.

FIG. 4(A) shows the relationship between the vector table and register information of the DTC2. FIG. 4(B) shows details of the vector table of the DTC2, in which vector numbers 64 to 95 are used for data transfer control. Vector number is 1
The addresses are written in 0 base and the corresponding addresses are written in hexadecimal.

FIG. 5(A) shows an operation flowchart, and FIG. 5(B) shows an operation flowchart.
) indicates the flow of information on the data bus 6. Figure 5 (B)
The transfer source and transfer destination addresses indicated by the broken lines inside may not be updated depending on the transfer mode.

The operation will be explained in detail below using these drawings. D
TC2 is activated by an interrupt request signal. The distinction between a normal interrupt and a DTC interrupt is controlled by a DTC enable bit in the interrupt controller 1.

DTC2 receives the DTC interrupt and receives the interrupt vector number (6
4 to 95), reads the address storing register information for each channel from the vector table according to that number, and performs data transfer using the register information stored at that address.

Register information is updated every time data is transferred, and when the value of the transfer word count register becomes O, a normal interrupt (vector numbers 32 to 63) is generated to the CPU.

FIG. 6 shows the location of register information within memory 4. FIG.

Register information for each channel can be placed at any location on the memory (limited to even addresses within the O-base) by setting addresses in the vector table.

The procedure for using the data transfer device described above is as follows.

■Disable CPU interrupts.

(2) Set the transfer mode, transfer source address, transfer source address, and number of transfer words to the address indicated by the vector for the DTC factor.

■Set the corresponding interrupt level register of the interrupt controller and enable the DTC enable bit.

■Manipulate the corresponding Ilo register to enable interrupts.

■Enable the CPU to interrupt.

(2) Start of operation FIG. 7 shows the number of stages required for one data transfer by the DTC. The number of states in the figure is a value when register information is set on the built-in RAM of the LSI. When register information is set on external RAM, it is necessary to add 20+4XSI+4XDI to the number of states shown in the figure. Furthermore, the data in the figure does not include states for the interrupt controller to determine priorities.

〔Effect of the invention〕

According to the present invention, data can be transferred in response to requests from a large number of peripheral processing devices with a small amount of hardware. Further, according to the present invention, data transfer in various data transfer formats can be performed in response to requests from a large number of peripheral processing devices. Further, according to the present invention, data transfer can be performed in response to interrupt requests from a large number of peripheral processing devices.

Furthermore, according to the present invention, all the information necessary for data transfer can be stored in a large-capacity main memory that can be handled by the CPU as a normal data area, so that the amount of information required for data transfer depends on the number of peripheral processing units requesting data transfer. You can transfer data without having to do anything. Further, according to the present invention, data transfer can be performed without updating the interrupt vector table every time data is transferred. Furthermore, according to the present invention, by changing the contents of the vector table used for data transfer, it is possible to freely change the area that stores all the information necessary for data transfer.

[Brief explanation of the drawing]

Figure 1 is a diagram showing one embodiment of the present invention, Figure 2 is an explanatory diagram of a register, Figures 3 (A) and 3 (B) are diagrams showing its contents, and Figure 4 (A) is a diagram showing the contents. Relationship diagram between vector table and register information, Figure 4 (B) is a detailed diagram of the vector table, Figure 5
Figure (A) is a diagram showing an operation flowchart, Figure 5 (B)
6 is an explanatory diagram of the flow of data on the bus, FIG. 6 is an explanatory diagram of the arrangement of register information, and FIG. 7 is a diagram showing the number of states required for execution. 1...Interrupt controller, 2...Data transfer controller, 3...First memory, 4.Second memory, 5
...Address bus, 6...Data bus, 10...
1st interrupt request signal, 11...2nd interrupt request signal, 20...interrupt vector number, 21...data transfer request signal.

Claims (1)

[Claims] 1. A data transfer device that transfers data stored in a memory, which includes: a) first address information indicating the memory location where the data to be transferred is stored; and b) a transfer destination memory. c) the number of words to be transferred, d) the word length of the data to be transferred, and e) the data to be transferred next when the number of words to be transferred is multiple. A data transfer device that transfers data based on transfer information indicating a means for obtaining the first address information indicating a memory location and second address information indicating a transfer destination memory location; When a device startup request is received, the first address information and the A data transfer device that transfers data by obtaining the second address information, the number of transfer words, the word length of the data, and the transfer information. 2. The contents shown in the vector table set forth in claim 1 include the first address information, the second address information, the number of transfer words, the word length of the data, and the storage location of the transfer information. A data transfer device characterized in that the data transfer device is a memory address indicating a memory address. 3. The first address information, second address information, number of transfer words, data word length, and transfer information described in claim 1 are stored in a memory guided by the contents shown in the vector table. , when obtaining the first address information, the second address information, the number of transfer words, the word length of the data, and the transfer information, first obtain the transfer information and the word length of the data, and then obtain the transfer information and the word length of the data. A data transfer device characterized in that data is transferred by obtaining one address information, the second address information, and the number of transfer words. 4. Means for storing the first address information, the second address information, the number of transfer words, the word length of the data, and the contents shown in the vector table for guiding the storage destination of the transfer information, as set forth in claim 1. A data transfer device characterized by being equipped with.