JPH0458646A - Buffer management system - Google Patents

Abstract

PURPOSE:To improve the data transfer efficiency of a communication equipment by devising a buffer memory to be able to store a new reception data even when the buffer memory overflows. CONSTITUTION:When it is discriminated that a transmission reception buffer memory 3a overflows, a read address pointed out by a read pointer 17 is revised from a head address of an oldest packet awaiting processing into a head address of a succeeding packet. The revision processing is executed by adding a data length of an oldest packet awaiting processing to the read address. The oldest packet is aborted while not being read by a CPU 5. Since an idle area is formed by the oldest packet in the transmission reception buffer memory 3a, even when the transmission reception buffer memory 3a overflows, a new reception packet is written in the idle area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a buffer management system, and particularly to a management system for a logical ring buffer provided in a communication device that transfers data.

(Prior Art) Generally, a communication device such as a bridge device that transfers data between local area networks is provided with a logical ring buffer to store transmitted and received data. In this logical ring buffer, data is written/read repeatedly from the first storage position to the final storage position, and once the data has been stored to the final storage position, subsequent data is stored sequentially from the first storage position again. be done.

FIG. 3 shows a conventional communication device that uses such a logical ring buffer as a buffer for transmitting and receiving packets.

The communication device shown in FIG. 3 performs two-port packet transfer, and includes an input/output section la, an input/output control section 2a, a transmission/reception buffer memory 3a, and a transceiver 4 for the first boat.
a, and an input/output section tb for the second boat.

It is composed of an input/output control section 2b, a transmission/reception buffer memory 3b1, a transceiver 4b, a CPU 5, and a program storage memory 6.

In this communication device, first, the human output unit I receives a packet from the network corresponding to the first boat, and the received packet is stored in the transmission/reception buffer memory 3a by the input/output control unit 2a. At this time, the input/output control section 2a
An interrupt signal is sent to the CPU 5, thereby notifying the CPU 5 that the packet has been received.

The CPU 5 checks the transfer destination of the packet stored in the transmission/reception buffer memory 8a, and if it is a packet that should be transferred to the input/output section ib, reads the packet from the transmission/reception buffer memory 3a and transfers the packet to the transmission/reception buffer memory. Transfer to 3b. The packet is then transmitted to the network corresponding to the second boat via the input/output control section 2b and the input/output section la. On the other hand, if the destination of the packet is the first boat that received the packet, C
PU5 discards the packet.

In this manner, the CPU 5 reads out the packet stored in the buffer memory 3a and performs processing to send it from the transfer destination boat or processing to discard it. However, if the amount of received packet traffic increases,
The load on the CPU 5 becomes heavy, packets waiting to be processed by the CPU 5 are retained in the buffer memory 3a, and as a result, the buffer memory 3a may overflow.

In this case, all newly received packets will be discarded.

As described above, conventional methods have the disadvantage that when an overflow state occurs in the buffer memory 3a, all received packets are discarded until the CPU 5 executes packet processing and there is free space in the buffer memory 3a. Ta.

(Problems to be Solved by the Invention) Conventionally, there has been a drawback that when the buffer memory overflows, subsequent received data cannot be written to the buffer memory and is all discarded.

This invention was made in view of these points, and it is possible to store new received data in the buffer memory even when the buffer memory overflows.
An object of the present invention is to provide a buffer management method that can improve the data transfer efficiency of a communication device using a buffer memory.

[Structure of the Invention] (Means and Effects for Solving the Problems) A buffer management method according to the present invention includes a logical ring buffer memory in which writing/reading of data is repeatedly executed from a first storage position to a final storage position; write address instruction means for indicating a write address for writing data to the logical ring buffer memory; read address instruction means for indicating a read address for reading data from the logical ring buffer memory; and detecting means for detecting an overflow state of the logical ring buffer memory based on the comparison result; and a detecting means for detecting an overflow state of the logical ring buffer memory based on the comparison result; and means for updating the value of the read address of the read address instruction means so that the oldest data stored in the read address is discarded.

In this buffer management method, the logical ring buffer 7
After data is written to the final storage location in the memory, data is written again from the first storage location, so if the amount of data waiting to be processed increases in the logical ring buffer memory, the value of the write address will change to the value of the read address. approach.

Therefore, by comparing the write address and the read address, it is possible to detect the state of the logical ring buffer memory, that is, whether or not it is in an overflow state. When an overflow condition is detected, the value of the read address is updated, so the oldest data waiting to be processed specified by the read address is discarded without being read, and the logical ring buffer memory Free space will be created. This allows new data to be written into the free space.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an input/output control section 10 for realizing a buffer management method according to an embodiment of the present invention. This input/output control unit 1O corresponds to the input/output control unit 2a of the first port in the communication device shown in FIG. do.

This input/output control section 10 includes a transmitting circuit 11 as shown in the figure.
．． Serial-parallel conversion circuit 12, receive byte counter 13, transmit/receive FIFO/(buffer 14, buffer 7
It includes a control circuit 15, a write pointer 1B, a read pointer 17, and a comparator 18.

The transmitting circuit 11 transmits the packets temporarily stored in the transmitting/receiving FIFO buffer 14 to the network via the input/output unit 1a. The serial-parallel conversion circuit 12 is
Serial data received from the network via the input/output unit 1a is converted into parallel data. The receive byte counter 13 counts the data length of received packets.

Transmission and reception packets are temporarily stored in the transmission and reception FIFO buffer y14. The buffer control circuit 15 is
Transmission/reception FIFO buffer 14 and transmission/reception buffer memory 3
control data transfer between a.

The write pointer 16 indicates the write address for writing the next packet into the transmission/reception buffer memory 3a. The read pointer 17 is connected to the transmitting/receiving buffer memory 3a.
This indicates the read address for reading the next packet from CP in Figure 3.
It shows the oldest packet among the packets waiting to be processed that have not yet been processed by U5.

These write pointer I6 and read pointer 1
The value of 7 is controlled by the buffer control circuit 15.

Comparator 18 compares the values of write pointer 18 and read pointer 17 and notifies buffer control circuit 15 of the comparison result. That is, the comparator 18 generates a logic "1" level signal when the value of the write pointer 16 is greater than or equal to the value of the read pointer 17, and generates a logic "0" level signal when the value of the write pointer 16 is smaller than the value of the read pointer 17. Generates a level signal.

Next, with reference to the flowchart of FIG. 2, the management operation of the transmission/reception buffer memory 3a by the input/output control section 10 of FIG. 1 will be explained.

When a packet is received by the input/output unit 1a, the serial-parallel conversion circuit 12 converts the packet from serial data to parallel data, and the receive byte counter 13 counts the data length of the packet. Serial-parallel conversion circuit 1
The received packet output from 2 is sent to the transmit/receive FIFO buffer 14 with information indicating its data length added.
is stored in

Next, the packet is transferred from the transmitting/receiving FIFO buffer 14 to the transmitting/receiving buffer memory 3a, and the packet is
Write address (Pl) indicated by write pointer 16
) is stored in the storage position in the transmission/reception buffer memory 3a specified by (step AI).

Thereafter, the value of the write address (PL) indicated by the write pointer 16 is updated by the buffer control circuit 15 by the data length of the written packet.

Next, the value of the write address (PI) indicated by the write pointer 16 and the value of the read address (P2) indicated by the read pointer 17 are compared by the comparator 18.
) is greater than or equal to the value of the read address (P2) is determined by the buffer control circuit 15 (step A2). If the packet is written to the final storage position of the transmitting/receiving buffer memory 3a, then the beginning of the packet is written again. Since packet writing is executed from the storage location, as the number of packets waiting for processing by the CPU 5 increases in the transmission/reception buffer memory 3a, the value of the write address (PI) approaches the value of the read address (P2), and in the case of an overflow state, , the write address (pi) is greater than or equal to the read address (P2).

Therefore, in step A2, when the value of the write address (Pl) increases from a state smaller than the value of the read address (P2) and exceeds the value of the read address (P2), the transmitting/receiving buffer memory 3a is Determine an overflow condition.

This overflow condition can be recognized by the output signal of the comparator 18 changing from "0°" to "1".

In step A2, if it is determined that the transmission/reception buffer memory 3a is in an overflow state, the read address (P
The value of 2) is updated from the start address of the oldest packet waiting to be processed to the start address of the next packet (the next oldest packet after the oldest packet) (step A3). This updating process of the read address (P2) is performed by adding the data length (K) of the oldest packet waiting to be processed to the value of the read address (P2).
) is performed by adding.

In this way, by changing the read address (P2) from the value indicating the oldest packet waiting to be processed to the value indicating the next packet (the next oldest packet after the oldest packet), the next packet to be read by the CPU 5 is the next oldest packet after the oldest packet, so the oldest packet is discarded without being read by the CPU 5. Therefore, an empty area is created in the transmitting/receiving buffer memory 3a for the oldest packet, so even if the transmitting/receiving buffer memory 3a becomes overflowed, a new received packet can be written into the empty area.

In this case, the transmission/reception buffer memory 3a is determined to be in an overflow state when the write address (PI) exceeds the value of the read address (P2), but when the value of the write address (Pl) approaches the read address (P2), Then, when the difference becomes within a predetermined value, it may be determined that the reception buffer memory 3a is in an overflow state.

In addition, this buffer management method that creates free space by discarding the oldest packet when the transmitting/receiving buffer memory 3a overflows is not limited to a two-port communication device as shown in Fig. 3, but can be applied to even more input/output ports. It can be similarly applied to communication devices including the above.

[Effects of the Invention] As described above, according to the present invention, new received data can be stored in the buffer memory even when the buffer memory overflows, and data transfer in a communication device using the buffer memory is improved. It becomes possible to improve efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an input/output control device for realizing a buffer management method according to an embodiment of the present invention, and FIG. 2 is a buffer management operation of the input/output control device shown in FIG. 1. FIG. 3 is a flowchart for explaining the conventional buffer management operation. 3a... Transmission/reception buffer memory, IO... Input/output control device, 15... Buffer control circuit, 16.
...Write pointer, 17...Read pointer,
18... Comparator. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] a logical ring buffer memory in which writing/reading of data is repeatedly executed from a first storage position to a final storage position; a write address indicating means for indicating a write address for writing data to the logical ring buffer memory; read address instruction means for indicating a read address for reading data from the buffer memory; and detection means for comparing the write address and the read address and detecting an overflow state of the logical ring buffer memory based on the comparison result. , when the detection means detects an overflow state of the logical ring buffer memory, the value of the read address of the read address instruction means is updated so that the oldest data stored in the logical ring buffer is discarded. A buffer management method comprising means.