GB2325597A - Discarding cells when a buffer overflows - Google Patents

Abstract

A method for discarding a received cell for use in handling time sensitive data for an ATM NIC (Asynchronous Transfer Mode Network Interface Card) comprises the steps of: setting up the free buffer ring (100) which includes entries, each entry pointing to a data buffer by using a head pointer and a tail pointer; comparing the head pointer with the tail pointer (102), both pointers residing in the free buffer ring, if cells that require a real-time service are received (101) in the ATM NIC; storing the received cells in a buffer designated by the tail pointer (104) if the value of the head pointer does not match the value of the tail pointer; increasing the value of the head pointer by 1 (103), discarding an oldest cell and storing the received cell in the data buffer designated by the tail pointer (104) if the head pointer matches the tail pointer; and increasing the value of the tail pointer by 1 (105).

Description

METHOD FOR DISCARDING ATM CELLS FOR USE IN AN ATM NIC The present invention relates to an Asynchronous Transfer Mode Network interface Card; and, more particularly, to a method for discarding received ATM cells in the event that an overflow occurs at a re-organization buffer while the Asynchronous Transfer Mode Network Interface Card is under a real-time operation.

An ATM (Asynchronous Transfer Mode) is a fast, cell switching technology based on a fixed length 53-byte cell which combines the best advantages of both circuit switching (for constant bit rate services such as voice and image) and packet switching (for variable bit rate services such as data and video). By definition, a message is dissolved into a number of cells to be transmitted from a sender, and at a receiver side, the message is recovered by a reorganization process.

The ATM communications scheme incorporates a concept of a layered structure. Fig. 1 illustrates a conceptual diagram of a general ATM protocol reference model representing the layered structure. A B-ISDN (Broadband ISDN) protocol reference model consists of three well-defined planes, i.e., a management plane, a control plane and a user plane.

The management plane includes two types of functions called a layer management and a plane management. All the management functions which relate to the whole system are located in the plane management. No layered structure is used within this plane. The layer management has a layered structure. it performs the management functions relating to resources and parameters residing in its protocol entities.

The control plane is responsible for call control and connection control functions. These are all signaling functions which are necessary to set up, supervise and release a call or a connection.

The user plane provides for a transfer of user information. All associated mechanisms like flow control or recovery from errors are included.

The protocol of the control plane and the user plane includes higher layers, an AAL (ATM Adaptation Layer), an ATM layer and a physical layer as shown in Table 1.

[Table 1]

LAYER SUB-LAYER | FUNCTIONS Higher layers l Higher layer functions ATM adaptation l Convergence(CS) Convergence layer | sub-layer Segmentation and Segmentation and Reassembly(SAR) Reassembly ATM layer General flow control and cell header processing, etc.

Physical layer Transmission Cell rate convergence(TC) decoupling, HEC sequence processing, etc. Physical media Bit timing

As shown in Table 1, the ATM communications scheme has vertically hierarchical layers such as the physical layer, the ATM layer, the AAL and the higher layer. The AAL breaks down into a SAR (Segmentation and Reassembly) sublayer and a CS (Convergence Sublayer). The physical layer is divided into a PM (Physical medium) sublayer and a TS (Transmission Convergence) sublayer.

Services provided for users can be classified as shown in table 2.

[Table 2]

Service Time- Bit rate Connection Service type relation mode example between source and destination Class A Required Constant Connection- CBR video oriented Class B Required Variable Connection- VBR video oriented Class C Not Variable Connection- Connection required oriented oriented data Class D Not Variable Connection- Connection required less less data An AAL protocol corresponding to the services enlisted in Table 2 are classified into an AAL 1 to an AAL 5 as shown in Table 3.

[Table 3]

ALL Type Major functions Type 1 Support class A service of CBR Type 2 Support class B service of Real-time, VBR Types 3/4 Support classes C and D service of VBR Type 5 Support high-speed service The AALs shown in Table 3 can be horizontally categorized into the AAl 1, AAL 2, AAL 3/4 and ALL 5.

Meanwhile, connecting a user terminal to the ATM network will require an ATM NIC (Network Interface Card) and appropriate software. The user terminal linked with an ATM network incorporates a NIC (network interface card) driver controls the ATM NIC and performs functions of the higher layer in conformity to a pre-defined protocol. Specifically, the NIC driver allocates and releases buffers in a memory within the NIC to transmit and receive packets, updates control variables and handles various interrupts, wherein the packet refers to a bundle of data in a prescribed format but not necessarily matching the cell of the ATM scheme.

When receiving cells, the NIC temporarily stores the incoming cells in a buffer, e.g., a reorganization buffer, in an incoming order before performing the reorganization process. An overflow may occur at the reorganization buffer in the event that the reorganization buffer is full and is not able to accept incoming cells furthermore since the size of the reorganization buffer is limited.

On the other hand, cells derived from some messages requiring a real-time process are extremely vulnerable to a transmission delay and a process delay. Longer delay makes the cells less important especially in the time-sensitive data. Should the overflow occurs, cells that cannot be contained in the reorganization buffer must be discarded, and, therefore, there is a need for deciding on which cell to discard. Yet, it is more desirable from the time-relation perspective, that the cells arrived earlier be lost rather than the cells arrived latter be lost.

It is, therefore, a primary object of the present invention to provide a method for discarding a received ATM cell in the event that the overflow occurs at the reorganization buffer while the ATM NIC is under a real-time operation, in order to improve the QoS.

In accordance with the present invention, there is provided a method for discarding a received cell for use in handling time sensitive data for an ATM NIC (Asynchronous Transfer Mode Network Interface Card), wherein the ATM NIC, under the control of a host system, converts messages from a user into cells suitable for ATM-based communications, and in reverse, recovers original messages by reorganizing received cells in the receive data buffers which stores the received cells and pointed to by an entry of a free buffer ring, the method comprises the steps of: setting up the free buffer ring which includes entries, each entry pointing to a data buffer by using a head pointer and a tail pointer; comparing the head pointer with the tail pointer, both pointers residing in the free buffer ring, if cells that require a real-time service are received in the ATM NIC; storing the received cells in a buffer designated by the tail pointer if the value of the head pointer does not match the value of the tail pointer; increasing the value of the head pointer by 1, discarding an oldest cell and storing the received cell in the data buffer designated by the tail pointer if the head pointer matches the tail pointer; and increasing the value of the tail pointer by 1.

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given with reference to the accompanying drawings, in which: Fig. 1 is a conceptual diagram of a B-ISDN protocol reference model; Fig. 2 presents a functional block diagram of a typical ATM NIC; Fig. 3 describes a data format processed in the ATM NIC shown in Fig. 2; Fig. 4 illustrates rings and buffers for providing a real time connection in accordance with the present invention; and Fig. 5 depicts a flow of the inventive method of discarding ATM cells.

Hereafter, a preferred embodiment of the present invention is described in detail in parallel with the attached drawings.

Referring to Fig. 2, there is illustrated an exemplary ATM NIC (Network Interface Card) to which the present invention applies.

A host system 10 links itself with the ATM NIC 20 to exchange data with another host system. The host system 10 may be a workstation or a personal computer, and the ATM NIC 20 usually is a card or a board inserted in the workstation or the personal computer. An I/O bus (S bus 30 in the preferred embodiment) links the host system to the ATM NIC 20.

The host system 10 is equipped with, to a minimum, an application program 11, a NIC driver 12, a memory 13, a processor 14 and a bus controller 15.

The application program 11, typically a group of software, runs to provide interactive services for users. It requests the NIC driver 12, also a group of software, to provide ATM communication services for users. Upon the request from the NIC driver 12, the ATM NIC sets up tables and rings (shown in Fig. 3), and updates various data in the tables.

The NIC driver 12 performs direct control over the ATM NIC 20.

The memory 13 contains itself buffers such as descriptor rings, completion rings and data buffers.

The processor 14 holds the responsibility for the operation of the host system 10.

The bus controller 15 performs control over the S bus 30.

The ATM NIC 20, as shown in Fig. 2, includes an AAL processor 21, a line adapter 22, a transceiver 23, a control RAM 25, an EPROM 26, a local slave bus 27 and a local memory bus 28, etc. The ATM NIC 20 is in charge of functions corresponding to the physical layer, the ATM layer and the AAL layer of the ATM communications scheme.

The AAL processor 21 provides complete encapsulation and termination of AAL 5 and has limited support for AAL 3/4. The AAL processor 21 is connected to the control RAM 25 via the local memory bus 28, and to the EPROM 26 via the local slave bus 27. The EPROM 26 is also connected to the line adapter 22 via the local slave bus 27. In addition, the AAL processor 21 has direct access to the memory 13 of the host system 10 via the S bus 30, and reads/writes data from/to the control RAM 25. The processor 14 in the host system 10 can also read/write data from/to the control RAM 25.

The line adapter 22 plus the transceiver 23 provides SONET (Synchronous Optical Network)/ATM interface transceiver for transporting ATM cells over the SONET.

The control memory 25 set up by the host system 10 to initialize the AAL processor 21.

The EPROM 26 is read by the host system 10 during power up and is used for the ATM NIC identification and configuration.

Upon request from the application program 11, the NIC driver provides the application program with an ATM-related services by controlling the ATM NIC 20. For example, when the application program stores some messages in the host memory 11 and requests the messages to be transmitted, the NIC driver requests the AAL processor 21 to transmit through the S bus 30.

The AAL processor 21 reads the messages stored in the memory 13 by a certain volume, e.g., 48 bytes, so as to fragment the messages into ATM cells in conformity to an ATM protocol format and delivers the cells to the line adapter 22 which is operating according to protocol of at the physical layer 24. The line adapter 22 maps the ATM cells onto a STS3c format (155.52 Mbps) of the SONET. The transceiver 23 transforms the STS-3c formatted serial data into optical signals and sends the optical signals to an ATM network (not shown) through a fiber-optic cable.

Considering the case the ATM NIC 20 receives optical signals from the ATM network, the optical signals received through the transceiver 23 are split into the ATM cells to be fed to the AAL processor 21 at the line adapter 22. The AAL processor 21 peels off headers and payloads from the ATM cells and merges the payloads together to recover the original messages. Upon the completion of the recovery, the AAL processor 21 informs the host system 10 of the completion by way of an interrupt. Upon the receipt of the interrupt, the NIC driver 12 passes the recovered messages to the application program.

Close look at the mechanism of data exchange between the upper layer and the AAL processor will now be taken with reference to Fig. 3.

Data to be exchanged between the host system 10 and the AAL processor 20 are stored in the memory 13 and the control RAM 25, respectively. More specifically, a transmit descriptor ring1 a transmit completion ring and transmit data buffers, which are used in transmission, are stored in the memory 13; and a receive data buffer, a receive completion ring and two free buffer rings, which are used in receipt, are stored in the control memory 25. In the control RAM 25, a bandwidth allocation table and a transmit DMA (Direct Memory Access) state table, which are used in transmission, are stored, and a receive DMA state table which is used in receipt are stored.

The number of the transmit descriptor ring is 255, and thus, is able to accommodate 255 VCs (virtual channels) . Each ring has 256 entries, in which the numbers depends on the designer's choice. Each entry which is composed of 4 words (1 word corresponds to 32 bits) designates one transmit data buffer. For example, a first transmit description ring is used for a voice channel; a second transmit description ring is used for a video channel; a third transmit description ring is used for a TCP/IP channel, etc.

Word 3 of the descriptor ring indicates the tail of AAL 5; word 2 designates a 4-byte ATM header; word 1 is a buffer pointer which points to the start position of the transmit data buffer; and word 0 represents a control field, a packet length and a buffer length. Referring more to word 0, bit 31 in the word 0 is an OWN bit. When a packet to be transmitted is queued and set by the host, the AAL processor gains access to the packet. Upon the completion of the transmission, the OWN bit becomes reset for the access from the host system 10.

Bit 30 and 29 of word 0 designate a start and a last buffer, respectively, in case a plurality of buffers are used for transmitting packets. Bit 27 represents an AAL type; bits 26 to 16 represent the packet length; and bits 15 to 0 indicate the buffer length. The maximum size of the buffer is 64K.

The transmit descriptor represents buffers in the memory 13 which holds packets to be transmitted.

The transmit data buffers keep data waiting for transmission, Upon the completion of preparation for transmission, the AAL processor 21 tries access to the data to send.

Meanwhile, the transmit completion ring holds 256 entries. Each entry, consisting of 4 words, indicates the completion of one packet. Bit 31 of word 0 out of the 4 words, is an OWN bit. The AAL processor 21 has the privilege of access to the transmit completion ring if the OWN bit is set to 1; and the host system 10 has the privilege of access if the OWN bit is set to 0. Bits 30 to 8 of word 0 are reserved for future definition, bit 7 to 0 indicate an index of the bandwidth allocation table.

The receive free buffer ring consists of 2 rings, the first and the second, each for indicating different size free buffers, each ring consisting of 256 entries. Each of the entries in the receive free buffer ring points to a vacant buffer in the receive data buffer. The host system 10 stores pointers of empty buffers in the receive free buffer ring.

The first buffer ring designates 8k byte buffers used in TCP/IP communications, the second buffer ring designates 48 byte buffers used in a CBR (Constant Bit rate) services.

Therefore, virtual channels for the CBR services utilizes the buffers designated by the second free buffer ring; and virtual channels for the TCP/IP communications utilizes the buffers designated by the first free buffer ring.

The entries of each free buffer ring have 4-word length.

Bit 31 of word 0 is an OwN bit, which is set if the entries are owned by the AAL processor 21 and is reset if owned by the host system 10. Bits 30 to 28 are reserved, and bits 27 to 0 are used in indicating a start point of the buffers. At an initialization stage, the receive data buffers are organized to have various sizes, minimum of 48 bytes to maximum of 64k bytes, by 16 byte interval, whereas the sizes of the buffers designated by one free buffer ring are equal.

The receive completion ring consists of 256 number of entries, each entry having 4-word size. Entries in the receive completion ring points to a buffer which is full with received data. Word 0 is used in indicating the packet length; word 1 is for indicating a pointer of a 28 bit start buffer; and word 2 is for indicating a 4 byte ATM header. Bit 31 of word 0 is an OWN bit, which is set if the entries are owned by the AAL processor 21 and is reset if owned by the host system 10. Bit 30 is a packet overflow bit which indicates an overflow occurred in the receive data buffer while receiving packets. Bit 29 contains information on a CRC condition, which signals the host system 10 of an error occurred in an AAL 5 packet. Bits 21 to 11 indicates a receipt of congestion cells, and bits 10 to 0 indicate the packet length.

The receive completion ring includes a pointer of the received packets stored in the host system 10. The host system 10, upon receipt of the interrupt from the AAL processor 21, scans the receive completion ring, and then, process the entries of which the OWN bit is reset.

Meanwhile, the control RAM 25 includes the bandwidth allocation table, the transmit DMA state table and the receive DNA state table, as shown in Fig. 3. The tables are accessed by both the AAL processor 21 and the host system 10.

The bandwidth allocation table has 4,800 entries, each entry consisting of 1 byte. The transmit DMA state table has 255 DMA entries, each entry consisting of 8 words. The receive DMA state table is used in receiving and has 1,024 DMA entries, each entry consisting of 8 words.

The bandwidth allocation table allocates bandwidth to the 255 number of transmit descriptor ring by allocating 0 to 255 indices to each 8-bit entry. Among the indices, "0" suggests that a null cell be under transmission. The bandwidth allocation table is set up at the initialization stage. The bandwidth allocation table has a pointer for designating the transmit DMA state table. The AAL processor 21 has access to, at the initialization stage, the tables, and transmits data stored in the transmit descriptor ring designated by the indices of the bandwidth allocation table.

The transmit DMA state table has 255 number of bandwidth allocation DMA entries, each DMA entry consisting of 8 words and designating the transmit data buffers. Among the 8 words constituting the DMA entry, words 0, 1, 2 and 7 are duplicated after the transmit descriptor ring: word 0 represents the control field, packet length and buffer length; word 1 indicates a pointer of a current buffer; word 2 designates the ATM header; and word 7 represents the tail of the AAL 5. Word 3 is designed to be written only by the host system 10. Bit 31 of word 3 is a BWG ON bit: data are transmitted according to the bandwidth allocation table if the BWG~ON is "0"; and only null cells are transmitted if the BWG~ON is "1". Bits 31 to 12 of word 4 are DVMA addresses, wherein the DVMA address points the position of current entry in the transmit descriptor ring. Word 6 is used for estimating a CRC incorporated in the AAL 5 packet.

The receive state table consists of 1,024 receive DMA entries, each entry consisting of 8 words. Bit 31 of word 0 becomes set when a DMA channel is activated; bits 21 to 11 are used as an EFCN (Explicit Forward Congestion Notification) cell counter; and bits 10 to 0 represents the packet length.

Word 1 indicates the current buffer pointer; word 2 indicates the start buffer pointer; and word 3 indicates the AAL packet length. A VC~ON bit of word 4 becomes set in the course of the packet reorganization, but if the VC~ON bit is reset, the AAL processor 21 discards the received cells of the corresponding VC. A buffer type bit represents whether the corresponding buffer belongs to the first or the second free buffer ring.

The mechanism that packets are transmitted and received will now be described in detail.

The transmit data buffer is in the memory 13, the maximum size of the transmit data buffer being 64k bytes. If the packets waiting for transmission are ready for the transmission at the host system 10, the ATM NIC 20 transmits the packets in sequence. The transmitted packets are stored in a receive memory in the memory 13 after the receipt. Upon the receipt, two different sizes of buffers, a large one and a small one, are involved with a view to an effective use of buffer resources, each are designated by the first free buffer ring and the second free buffer ring, respectively.

First, the application program 11 of the host system 10 stores the data waiting for transmission in the transmit data buffer, and set up a transmit buffer ring by writing the pointers of the buffers in the transmit descriptor ring. The OWN bit of corresponding entries in the transmit descriptor ring is set, which means the host system passes the handling of the packets to the AAL processor 21.

The AAL processor 21 processes the data stored in the transmit data buffer according to the transmit DMA state table which is designated by the indices of the bandwidth allocation table while scanning the bandwidth allocation table, wherein in the transmit state table, entry data of the transmit descriptor ring have already been copied. Accordingly, the AAL processor 21 retrieves the data by a unit of 48 bytes from the transmit data buffer which is designated by the pointer of the transmit state table and transmits the data.

Accordingly, if the 48 byte payloads are transmitted, the AAL processor 21 updates registers therein (not shown) and processes the subsequent entry of the transmit DMA state table designated by the subsequent entry of the bandwidth allocation table. Once the AAL processor 21 returns access back to the transmit DMA state table while scanning the bandwidth allocation table in turn, it does not access the transmit descriptor ring but accesses the transmit DMA state table, wherein the transmit DMA state table has been updated with pointers of the transmit data buffer designating the cells to be transmitted next.

When the transmission of data with respect to one transmit data buffer is completed, the AAL processor 21 copies the data in the next entry of the transmit descriptor ring to the transmit DMA state table and continues to process. More specifically, an entry of the transmit descriptor ring points out one transmit data buffer. If the packets waiting for transmission claims 5 buffers, 5 transmit descriptor ring entries are needed to accommodate the packets. In this case, if there is generated a remnant of 16 bytes because the first 'buffer cannot cover the packets, the AAL processor 21 handles the 16 bytes, updates the DMA state table and fetches the 32 bytes from the second buffer to make 48 byte units.

If the process of data with respect to the last buffer among the buffers that shares data of one packet is completed, an EOF (End of packet) process begins. In the EOF process, in case conforming to the AAL 5 type, for example, filling pads and generating an AAL5 tail are performed.

As described above, if a process with respective to a packet is completed, the AAL processor 21 clears the OWN bit of the transmit descriptor ring entry allocated to the processed packet, generates the transmit completion ring entry, and finally, sends the interrupt to the host system 10.

An OWN bit and an bandwidth allocation index are recorded in the transmit completion ring. The bandwidth allocation index is used for the host system to reuse the memory of the processed packet.

On the other hand, the receipt process can be described as follows. One entry of the receive DMA table is allocated according to the 10-bit VCI of received ATM cell. An entry in the receive DMA table corresponds one-by-one to one entry in the two receive buffer ring.

If the received cell is the first cell of the corresponding VCI, the DMA entry indicates that which free buffer will be used to store the received cell. For example, it is determined whether the buffer to be allocated to the entry which is designated by the VCI belong to the first free buffer or the second free buffer, and then, the first free buffer ring is accessed for the address in the free buffer is copied to the DMA entry. Consequently, the first received cell is stored in the buffer designated by the corresponding DMA entry.

In case the subsequent cell incoming through the same VCI with the previous VCI used is received, the receive free buffer ring is not accessed, instead, the 48 bytes are stored in the buffer designated by the DMA entry.

If the next cell incoming through a different VCI from the previous VCI is received, the corresponding DMA entry is accessed, and a free buffer start address is fetched from the receive free buffer ring, and then, the ATM cell is stored in the corresponding buffer.

When repetitive operation described above completes the receipt of a packet, the AAL processor 21 stores the packet in the receive completion ring and generates the interrupt to inform the host system. Then, the OWN bit of the receive descriptor ring and the OWN bit of the receive completion ring are reset so that the privilege is handed over to the host system 10.

The aforementioned ATM NIC has been implemented with the transmit and receive data buffers in the memory 10. The transmit and receive data buffers, on the other hand, can sit in the memory within the ATM NIC, and additionally, the control data format for use in the control of transmission and receipt may have a variety of forms.

Hereinafter, with the aforementioned ATM NIC in mind, the preferred embodiment will now be described in detail.

Referring to Fig. 4, the entries of the free buffer ring 43 are designated by the tail pointer 41 and the head pointer 42. The entries of the free buffer ring 43 holds the start addresses to each of the buffers 44-1 - 44-6. The head pointer 42 designates the entries of the buffer which stores the first received cell; and the tail pointer 41 designates the entries of the buffer which can store a newly received cell.

The state that the values of the head pointer 42 and the tail pointer 41 match is regarded as the overflow. If the overflow occurs, the value of the head pointer is increased so as to discard the first received cells, and newly arrived cells are stored in the address designated by the tail pointer. That is to say, a cell undergone a long time delay is discarded, instead, a newly arrived cells can be accepted.

structure.

Fig. 5 illustrates a sequence chart showing the inventive operation. Referring to Fig. 5, if a real-time call set-up is established, the free buffer rings are set up. The free buffer ring have a plurality of entries, each entry holding the address of free buffer. The entries of the free buffer ring are pointed out by the head pointer and the tail pointer.

The head pointer designates the first entry and the tail pointer designates an entry to store a currently received cell, the value of the tail pointer increases as the cells arrives.

The ATM NIC receives cells of packet k at step 101, then compares the values of the head pointer and the tail pointer at step 102.

If the values of the head pointer and the tail pointer match, i.e., the overflow occurs, the value of the head pointer is increased by one at step 103, and a newly arrived cell is stored in the buffer directed to by the tail pointer at step 104. While this manipulation occurs, the data having been stored in the buffer directed to by the entry of the head pointer is lost, but on the other hand, the newly received cell can be stored.

If the overflow is not determined to occur at step 102, the received cell can be stored in the buffer designated by the tail pointer at step 104, and then, the value of the tail pointer is increased by 1 at step 105.

As described above, in accordance with the inventive method, cells can be effectively discarded. That is to say, in the event that the overflow occurs in the re-fabrication buffer, cells undergone a long time delay can be discarded, instead, newly arrived cells can be accepted by managing packet data by using a ring structure.

While the present invention has been described with respect to the preferred embodiments, other modifications and variations may be made without departing from the scope of the present invention as set forth in the following claims.

Claims (5)

Claims:

1. A method for discarding a received cell for use in handling time sensitive data for an ATM NIC (Asynchronous Transfer Mode Network Interface Card), wherein the ATM NIC, under the control of a host system, converts messages from a user into cells suitable for ATM-based communications, and in reverse, recovers original messages by reorganizing received cells in the receive data buffers which stores the received cells and pointed to by an entry of a free buffer ring, the method comprises the steps of: setting up the free buffer ring which includes entries, each entry pointing to a data buffer by using a head pointer and a tail pointer; comparing the head pointer with the tail pointer, both pointers residing in the free buffer ring, if cells that require a real-time service are received in the ATM NIC; storing the received cells in a buffer designated by the tail pointer if the value of the head pointer does not match the value of the tail pointer; increasing the value of the head pointer by 1, discarding an oldest cell and storing the received cell in the data buffer designated by the tail pointer if the head pointer matches the tail pointer; and increasing the value of the tail pointer by 1.

2. A method for discarding a received cell in the event that an overflow occurs at a buffer in such a manner that a first stored cell is discarded in order to accommodate a space for a newly arrived cell, wherein the buffer is a memory device that receives and stores incoming data thereto in a sequential manner and the overflow refers to a state that the buffer is full, and thus, cannot receive no more incoming cells thereto.

3. The method of claim 2, wherein the features of said cells are defined by the ATM (Asynchronous Transfer Mode) communication architecture.

4. The method of claim 3, wherein said cells contain information requiring a real-time handling.

5. A method substantially as herein described with reference to or as shown in figure 5 of the accompanying drawings.