JP3190214B2 - Data transmission / reception system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission / reception system for transmitting / receiving data between a plurality of communication devices in word units.

[0002]

2. Description of the Related Art Conventionally, a system as shown in FIG.
That is, a system is known in which two communication devices 10 and 20 are connected to each other by a bus 30 and data is transmitted and received between the communication devices 10 and 20 in word units via the bus 30.

In the system shown in FIG. 8, for example, when performing data transmission (data transfer) in word units from the communication device 10 to the communication device 20, first, a read pointer register (hereinafter referred to as RP) is transmitted from the data transmission register file 11. Data (word data) at the address specified by the register 12 is read and transmitted to the communication device 20 via the path 31 of the bus 30.

[0004] The data transmitted from the communication device 10 to the communication device 20 is guided to a data reception register file 21 and an error detection circuit 23 in the communication device 20. The error detection circuit 23 performs an error detection operation (reception error detection operation) for detecting the presence or absence of an error in the data (reception data).
I do. If no data error is detected, the data is stored in the data reception register file 21.
Is written to. On the other hand, if an error in the data is detected, the data must be retransmitted. As a method for enabling this data retransmission, the following two methods have conventionally been used.
One was known.

In the first method, each time an error detection operation is performed by the error detection circuit 23 in the communication device 20, the error detection result is notified to the communication device 10 via the path 33 of the bus 30, and In 10, every time this error detection result is received, the presence or absence of a data error is checked, and if no data error is found, the data transmission register file (in the next cycle) is advanced (by advancing the value of the RP register 12). 1
When the next data is transmitted from 1 and there is a data error, the same data is transmitted again from the data transmission register file 11 in the next cycle (by not advancing the value of the RP register 12). .

In the second method, data is continuously transmitted from the communication device 10 to the communication device 20 while normally advancing the value of the RP register 12 unconditionally. When a data error is detected by the error detection circuit 23, the communication device 10 is notified of an error detection result indicating that there is an error after a predetermined cycle, so that the value of the RP register 12 at that time is , The address (order) of the data in which the error has occurred is specified, and transmission is performed again from the data at that address.

[0007]

However, in the first method, the communication device 10 transmits the next data until the error detection result is notified from the communication device 20 (the presence or absence of a data error is confirmed). However, there is a problem that the data transfer performance is low because the data transfer cannot be performed.

In the second method, when (1) the transfer operation of the communication device 10 and the reception operation (reception error detection operation) of the communication device 20 are asynchronous, (2) data is received by the communication device 20 There is a problem that it cannot be applied if the cycle of reading into the register file 21 is not constant.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to read data from a receiving communication device even when a transfer operation of a transmitting communication device and a receiving operation of a receiving communication device are asynchronous. Even if the cycle is not constant, the transmitting communication device can continuously transfer data without waiting for the reception error detection result at the receiving communication device. Is to provide a data transmission / reception system that can determine the order of retransmission and perform retransmission.

Another object of the present invention is to guarantee that data that may be retransmitted is left in the transmitting communication device, and that an error in data received by the receiving communication device is detected. It is an object of the present invention to provide a data transmission / reception system capable of reliably retransmitting the data when the data is transmitted.

Still another object of the present invention is to provide a data transmission / reception that can prevent retransmission of the same data from being repeated more than a predetermined number of times and avoid locking of a bus between communication devices due to retransmission of the same data. It is to provide a system.

[0012]

A data transmission / reception system according to a first aspect of the present invention stores data transmitted from a first communication device to a second communication device in a predetermined unit. A data transmission storage means provided in the first communication device and a read position of the data transmission storage means, and each time a predetermined unit of data is read from the storage means, the next data Read pointer means for updating a read position for reading; buffer storage means for temporarily holding data read from the data transmission storage means and outputting the data to the second communication device in a first-in first-out manner; A data receiving storage device provided in the second communication device for storing data output from the buffer storage device to the second communication device as reception data; It is intended to designate a writing position of the credit storage unit, the each time data is written to the storage means, and write pointer means for updating the write position for the next data writing, the second from the buffer storage means
Error detecting means for detecting the presence or absence of an error in the data output to the communication device, and, when a data error is detected by the error detecting means, a read corresponding to the write position indicated by the write pointer means at that time Resending control means for setting a position in the read pointer means and causing resending from data at the read position in the data transmission storage means designated by the read pointer means. .

[0013] In such a configuration, the predetermined unit in the first communication device and the data transmission operation of a predetermined unit in the (transmission side communication apparatus) side, a second communication apparatus (reception side communication apparatus) side
Even if the data receiving operation of the second communication device is performed asynchronously and the data reading cycle of the second communication device is not constant,
The buffer storage means provided between the data transmission storage means of the first communication device and the data reception storage means of the second communication device allows data transmission and reception (data transfer) of the first and second communication devices. ) Speed differences are absorbed.

Further, even in a system in which the data transmission operation of the first communication device and the data reception operation of the first communication device are performed asynchronously as described above, the first communication Even if the device performs continuous data transfer without waiting for the result of detection of the reception error from the second communication device, if an error of the data received by the second communication device is detected by the error detection means, At this time, the read position (the position in the data transmission storage unit where the data was written) corresponding to the write position indicated by the write pointer unit (that is, the write position in the data reception storage unit where the data is to be written) is determined. Is set in the read pointer means by the retransmission control means, the order of the erroneous data is determined, and the data transmission storage designated by the read pointer means is set. Since retransmitted from the data read position within the stage are performed, it is possible to correct data retransmission.

A data transmission / reception system according to a second aspect of the present invention is the data transmission / reception system according to the first aspect, wherein a third communication device for transmitting data to the first communication device is added. The write pointer means (first write pointer means) for designating the write position of the data transmission storage means, and the write positions of the write pointer means (first write pointer means) and the data reception storage means are designated. The write position indicated by the write pointer means (second write pointer means) is monitored, and a new retransmission-possible data stored in the data transmission storage means is stored in the data transmission storage means. Write control means for stopping the writing of new data.

In such a configuration, the write control means includes first write pointer means (write pointer means for designating a write position of the data transmission storage means on the first communication device side) and second write pointer means. Light pointer means (second
The write position indicated by the write pointer unit for designating the write position of the data receiving storage unit of the communication device is monitored. As a result of this monitoring, the write control means proceeds to write the data sent from the third communication device into the data transmission storage means, and the write position indicated by the first write pointer means is changed to the second write pointer means. If there is a possibility that the writing position indicated by (3) may be sent around, the writing of new data from the third communication device is temporarily stopped (waited). This prevents new data from being written from the third communication device into the storage location of the data that may be retransmitted and stored in the storage unit for data transmission. Is stored in the data transmission storage means.

A data transmission / reception system according to a third aspect of the present invention is the data transmission / reception system according to the first or second aspect, wherein the retransmission number counter counts the number of times retransmission of the same data is continuously performed. Means for updating the read position indicated by the read pointer means to point to the next data position and stopping retransmission when the number of retransmissions counted by the retransmission number counter means is equal to or more than a predetermined number. Is further provided.

In such a configuration, the number of times retransmission of the same data is continuously performed is counted by the retransmission number counter. The retransmission stopping means monitors the count value (the number of retransmissions) of the retransmission counter means, and when the count exceeds a predetermined number, retransmission is considered to be useless and the read position indicated by the read pointer means is read. By updating the data to point to the position of the next data, a predetermined number of erroneous data is discarded, retransmission is stopped, and transmission from the next data is performed. Thereby, for example, not due to an error at the time of transmission, but due to errors due to defects in the data itself, retransmission of the same data is repeatedly performed many times,
A bus lock between the first communication device and the second communication device can be avoided.

A data transmission / reception system according to a fourth aspect of the present invention is the data transmission / reception system according to the first or second aspect, wherein the retransmission number counter counts the number of times the same data has been continuously retransmitted. Means for detecting the occurrence of a data error by the error detection means when the number of retransmissions counted by the retransmission number counter means is equal to or greater than a predetermined number; Means for updating the write position indicated by ()) to indicate the position of the next data and stopping retransmission.

In such a configuration, even if an error in the received data is detected by the error detection means, if the number of retransmissions is equal to or more than a predetermined number, that is, the error of the same data is detected continuously for a predetermined number of times or more. In this case, the error is masked so that the error cannot be seen from the first communication device, so that control is performed so that further retransmission is not performed. Further, since the write position indicated by the write pointer means (second write pointer means) is updated so as to point to the position of the next data, data having a predetermined number of errors is discarded, and the data from the next data is discarded. Switch to transmission. As a result, the same data is retransmitted many times,
Bus lock between the first communication device and the second communication device can be avoided.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram of a data transmitting / receiving system according to a first embodiment of the present invention.

In FIG. 1, reference numerals 100 and 200 denote communication devices that operate asynchronously with each other, and reference numeral 300 denotes communication devices 100 and 2.
This is a bus for connecting between 00. Communication device 10
Data 0 and 200 are transmitted and received in word units via the bus 300. Here, for the sake of simplicity, it is assumed that communication device 100 has a data transmission function and communication device 200 has a data reception function, but the other way around, the communication device 100 may have both functions.

The communication device 100 includes a data transmission register file 101, a read pointer register (hereinafter referred to as an RP).
, A retransmission control circuit 103, and a buffer register file 104.

The data transmission register file 101 is
This is for storing data to be transmitted to the communication device 200. The RP register 102 indicates a storage position (read address) in the register file 101 of data to be read from the data transmission register file 101. The RP register 102 has an increment function of incrementing the content thereof by one each time data is output (read) in word units from the data transmission register file 101.

The retransmission control circuit 103 stores the address sent from the communication device 200 when the error detection result indicating the presence of an error is received from the communication device 200 in the RP register 1.
02 is set to perform retransmission from the data at that address.

The buffer register file 104 temporarily holds data output from the data transmission register file 101 in word units, and outputs the data in a first-in first-out (FIFO) manner in synchronization with the reception operation of the communication device 2. It is for doing.

The communication device 200 includes a data reception register file 201, a write pointer register (hereinafter, WP).
202, an error detection circuit 203, and an address transmission circuit 204.

The data reception register file 201 is
Communication device 100 (internal buffer register file 104)
This is for storing data transmitted in word units from. It is assumed that the data reception register file 201 in this embodiment has the same size as the data transmission register file 101 in the communication device 100.

The WP register 202 stores the data received from the communication device 100 in the data reception register file 20.
1 storage destination (write destination) address (write address)
It shows. The WP register 202 has an increment function of incrementing the content by one each time data is stored in the data reception register file 201 in word units. That is, the contents of the WP register 202 are updated in the same direction as the RP register 102 in the communication device 100.

The error detection circuit 203 checks the data received from the communication device 200 for errors. If there is an error, the error detection circuit 203 outputs an error detection result indicating the error to the communication device 100.
(The retransmission control circuit 103 therein). The error detection result of the error detection circuit 203 is also used to prohibit the value of the WP register 202 from being incremented.

The address transmission circuit 204 transmits the address (write address) indicated by the WP register 202 to the communication device 1
00 (the retransmission control circuit 103 therein). The bus 300 includes a path 301 provided for data transfer (data transmission) from the communication device 100 (the buffer register file 104 therein) to the communication device 200, and the communication device 20.
0 (the address transmission circuit 204 therein) to the communication device 100
From the communication device 200 (in which the error detection circuit 203 is provided) to the communication device 100.
The path 303 is provided for the notification of the error detection result. Note that it is also possible to use a bidirectional path instead of the paths 301 and 302, and perform data transmission and address (error data address) transmission using the same path.
In this case, the address may be transmitted together with the error detection notification only when the error detection circuit 203 detects a reception error.

Next, the operation of the configuration shown in FIG. 1 will be described. First, when transmitting data in word units from the communication device 100 to the communication device 200, the communication device 100
Data transmission register file 1 indicated by register 102
01 (word data) is read out and FIFO
Then, the value (read address) of the RP register 102 is incremented by one. The data transmitted from the data transmission register file 101 to the buffer register file 104 is held in the register file 104.

In this embodiment, the communication devices 100 and 20
0 operates asynchronously, and includes a data transmission operation (operation for reading data from the data transmission register file 101) in the communication device 100 and a data reception operation (data reception register file 201) in the communication device 200.
Operation of writing data to) is not synchronized. The buffer register file 104 absorbs the asynchronous operation of data transmission / reception (input / output) of the communication devices 100 and 200.

That is, in the communication device 200, the communication device 100
Performs a receiving operation asynchronously with the data reading operation (data transmitting operation) from the data transmitting register file 101, and the data previously input from the buffer register file 104 (in the communication device 100) at that time. Of the bus 300 (data transfer path) 30
1 to receive.

Error detection circuit 203 in communication device 200
Checks for errors in the data received by the communication device 200. If no error in the received data is detected, the received data is written to the data reception register file 201 indicated by the WP register 202,
Then, the value of the WP register 202 (write address)
Is incremented by one.

Here, assuming that the initial values of the registers 102 and 202 are both "0",
Since the value of 202 is incremented by one each time one word of data is transmitted / received, the values of registers 102 and 2 are increased.
02 has the same address value for the same data.

On the other hand, the error detection circuit 2 in the communication device 200
03, if an error in the received data is detected,
Although the received data is written to the data reception register file 201 indicated by the WP register 202, the increment operation of the WP register 202 performed after the writing is suppressed.

The WP register 2 before the increment
02 is provided, and the increment operation of the WP register 202 is performed as usual.
The content of the save register may be loaded (written back) into the WP register 202 in response to the error detection of the error detection circuit 203. In addition, a configuration may be adopted in which data writing itself to the data reception register file 201 is suppressed in accordance with the error detection of the error detection circuit 203. The point is that the address at which the received data in which the error was detected should be written to the data reception register file 201 is W.
What is necessary is just to have the structure held in the P register 202.

When an error in the received data is detected by the error detection circuit 203, the fact is notified from the error detection circuit 203 to the retransmission control circuit 103 in the communication device 100 via the path 303 of the bus 300. Is done.

The address indicated by the WP register 202 is sent to the retransmission control circuit 103 from the address transmission circuit 204 in the communication device 200 via the path 302 of the bus 300.

Retransmission control circuit 103 in communication apparatus 100
When the error detection is notified from the error detection circuit 203 in the communication device 200, the address transmitted from the address transmission circuit 204 in the communication device 200, that is, the WP when the error detection circuit 203 detects the error. Register 202
Is set in the RP register 102 and all the contents of the buffer register file 104 are cleared.

As is apparent from the above description, when an error in the received data is detected by the error detection circuit 203, the data reception in the communication device 200 to which the data would have been written if the data was correct. Destination address of the register file 201 for the RP register 10
It will be set to 2. This address corresponds to the received data, that is, the data reception register file 1 in which the data in which the error was detected by the error detection circuit 203 was stored.
Matches the address 01.

Therefore, in the communication device 100, the error detection circuit 203 in the communication device 200 starts from the data in the data transmission register file 101 specified by the address set in the RP register 102 by the retransmission control circuit 103.
Is transmitted again from the data in which the error has been detected.

As described above, according to this embodiment, by providing the buffer register file 104 between the data transmission register file 101 in the communication device 100 and the data reception register file 201 in the communication device 200, Transfer (Transmission) Operation of Communication Device 100 and Communication Device 20
Since the receiving operation of 0 (receiving error detecting operation) can be performed asynchronously, the data transfer performance is high. Moreover, the WP register 10
2, that is, the write destination address of the data received by the communication device 200 in the data reception register file 201 is matched with the address of the data transmission register file 101 in which the data is stored. (Error detection circuit 203) detects the error in the received data, the WP register 102
The address indicated by RP register 10 in communication device 100
2 and the transmission is performed again from the data of the address, so that the error is detected although the transfer operation of the communication device 100 and the reception operation of the communication device 200 are performed asynchronously. Retransmission from data can be performed reliably.

However, in this embodiment, the data transmission register file 101 is used as a ring buffer,
Before all the data stored in the register file 101 is received by the communication device 200 through the buffer register file 104 without error, for example, subsequent transmission data transferred from another communication device is stored in the register file 1.
When the method of storing data at a position subsequent to 01 is applied, data that may be retransmitted due to newly stored data may be lost from the data transmission register file 101.

A second embodiment capable of guaranteeing that data that can be retransmitted is left in the data reception register file of the transmitting communication apparatus will be described with reference to the drawings. [Second Embodiment] FIG. 2 is a block diagram of a data transmission / reception system according to a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The system of FIG. 2 is different from the system of FIG. 1 in that a communication device 110 is used instead of the communication device 100, and a communication device 400 for transmitting data to the communication device 110 is provided. That is. The communication devices 400 and 110 are connected by a bus 500.

The communication device 110 is the communication device 10 shown in FIG.
0, the data transmission register file 101, R
In addition to a P register 102, a retransmission control circuit 103 and a buffer register file 104, a WP register (write pointer register) 111 and a write control circuit 1
12 and an error detection circuit 113.

The WP register 111 stores the data received from the communication device 400 in the data reception register file 20.
1 storage destination (write destination) address (write address)
It shows. The contents of the WP register 111 are as follows:
Each time data is stored in the data transmission register file 101 in word units, the content is incremented by one. WP register 111
Is equal to the initial value of the RP register 102,
It is assumed to be “0”.

The write control circuit 112 compares the address (for example, the most significant bit) from the address transmission circuit 204 in the communication device 200 with the address of the WP register 111 (for example, the two most significant bits). The writing (data transfer) from the communication device 400 to the (data transmission register file 101) is controlled in accordance with the comparison result.

The error detection circuit 113 checks the presence or absence of an error in the data sent from the communication device 400 and, if there is an error, notifies the communication device 400 of an error detection result indicating the error.

Next, an outline of the operation of the configuration shown in FIG. 2 will be described. First, in this embodiment, the data transmission register file 101 in the communication device 110 and the data reception register file 201 in the communication device 200 are used as ring buffers. In this case, the communication device 1
The registers 102 and 111 in the register 10 are incremented by one each time a read / write operation of data (one word data) for the data transmission register file 101 is performed. "Cleared. Similarly, the register 202 in the communication device 200 is incremented by one each time a data write operation is performed on the data reception register file 201, and when the value reaches the maximum value, is cleared to "0" at the next increment.

Now, in order to guarantee that data that may be retransmitted is left in the data receiving register file 101 in the communication device 110, of the data stored in the register file 101, It is sufficient that data not received is not rewritten by new transmission data transferred from the communication device 400. For this purpose, the address of the WP register 111 in the communication device 110 needs to be updated too much and the address indicated by the WP register 202 in the communication device 200 does not have to be a round delay (one cycle delay).

This control is performed by the write control circuit 112 in the communication device 110. That is, the write control circuit 112
Transmits the most significant bit (MSB) of the address indicated by the WP register 202 in the communication device 200 to the path 30 of the bus 300.
2 through the MSB side of the address indicated by the WP register 111 in the communication device 110 (upper 2 bits).
Bit), the data transfer from the communication device 400 is controlled so that the address indicated by the WP register 111 does not delay the address indicated by the WP register 202.

Details of the control by the write control circuit 112 will be described with reference to FIG. In FIG. 3, arrows indicated by reference numerals 3a and 3b indicate communication devices 110 and 20.
It shows the progress of the address indicated by the WP registers 111 and 202 in 0.

(A) First, in the initial state, the communication device 200
The MSB (of the indicated address) of the WP register 202 is 0B (the last B indicates that it is expressed in binary).
When the MSB of the WP register 202 is 0B, that is, when the data of the address of MSB = 0B is received on the communication device 200 side, the write control circuit 112 sets the WP register 111 of the communication device 110 Until the two bits (upper two bits) on the MSB side (of the indicated address) become 11B, data transfer from the communication device 400 is permitted,
The data transferred from the communication device 400 is written into the data transmission register file 101 (specified by the WP register 111) (see FIG. 3A).

When the two bits on the MSB side of the WP register 111 become 11B, the write control circuit 112
Causes the data transfer (data reception) from the communication device 400 to be temporarily stopped.

(B) Transmission from the data transmission register file 101 in the communication device 110 to the communication device 200 (performed through the buffer register file 104) while the data transfer from the communication device 400 is suspended. When the MSB of the WP register 202 becomes 1B, the write control circuit 112 permits the data transfer from the communication device 400 again until the two bits on the MSB side of the WP register 111 become 01B. , The communication device 40
The data transferred from 0 is written to the data transmission register file 101 (specified by the WP register 111) (see FIG. 3B).

When the two bits on the MSB side of the WP register 111 become 01B, the write control circuit 112
Causes the data transfer (data reception) from the communication device 400 to be temporarily stopped.

(C) Transmission from the data transmission register file 101 in the communication device 110 to the communication device 200 (performed through the buffer register file 104) while the data transfer from the communication device 400 is suspended. When the MSB of the WP register 202 becomes 0B, the write control circuit 112 permits the data transfer from the communication device 400 again until the two bits on the MSB side of the WP register 111 become 11B. , The communication device 40
The data transferred from 0 is written to the data transmission register file 101 (specified by the WP register 111) (see FIG. 3C).

When the two bits on the MSB side of the WP register 111 become 11B, the write control circuit 112
Causes the data transfer (data reception) from the communication device 400 to be temporarily stopped.

Thereafter, the write control circuit 112 repeats the above controls (b) and (c). The WP register 111 is controlled by a series of control operations of the write control circuit 112 described above.
Can be set so that the address indicated by the WP register 202 does not delay the address indicated by the WP register 202, that is, the address indicated by the WP register 111 changes the address indicated by the WP register 202 (the data transmission register used as the ring data buffer). The data transmission register file 101 can prevent the data from being overtaken for more than one round (of the file 101), and may transmit data that may be retransmitted.
Can be guaranteed to leave.

In this embodiment, the routes 301, 3
It is also possible to perform data transmission and address (error data address) transmission using the same path using a bidirectional path instead of 02, but only the MSB of the address is
It is necessary to provide a dedicated path so that the write control circuit 112 can always refer to it.

In this embodiment, the write control circuit 1
12 is such that the address indicated by the WP register 111 does not delay the address indicated by the WP register 202 in the circuit.
The two bits on the MSB side of the address indicated by the WP register 111 and the MSB of the address indicated by the WP register 202 are monitored to control the suspension / permission of data transfer from the communication device 400 to the communication device 110. However, the present invention is not limited to this, and the number of bits on the MSB side to be monitored may be further increased to control the suspension / permission of data transfer in smaller units than in this embodiment. However, if the number is increased too much, the suspension / permission of data transfer frequently occurs.

In the first and second embodiments described above,
When the error detection circuit 203 detects an error in the received data, the data is always retransmitted. However, in the case of an error caused by a defect in the data itself, retransmission of the same data is repeated endlessly, and a bus lock between the communication devices may occur.

The third to sixth embodiments in which the number of retransmissions of the same data is limited will be described in order with reference to the drawings. [Third Embodiment] FIG. 4 is a block diagram of a data transmitting / receiving system according to a third embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The system shown in FIG. 4 uses a communication device 120 instead of the communication device 100 of the system shown in FIG. This communication apparatus 120 is different from communication apparatus 100 in FIG. 1 in that retransmission control circuit 123 having save register 121 is used instead of retransmission control circuit 103, and retransmission number counter 124 and retransmission stop circuit 125 It is added.

Save register 12 in retransmission control circuit 123
Reference numeral 1 is for holding the content of the WP register 202 (address of the previous error data) at the time when the error of the received data was notified from the error detection circuit 203 last time.

The retransmission control circuit 123
3 receives the notification of the error in the received data, the address of the current error data sent from the address transmission circuit 204 at that time (the WP register 202 at the time of the current error notification).
Is compared with the address of the previous error data held in the save register 121.

If the address of the current error data and the address of the previous error data match, the retransmission control circuit 123 determines that retransmission of the same data is to be repeated, Is incremented by one. If the address of the current error data does not match the address of the previous error data, the retransmission control circuit 123 determines that the same data is not retransmitted, and sets the retransmission number counter 124 to “0”. clear.

When the retransmission control circuit 123 operates the retransmission number counter 124, the retransmission control circuit 123 updates the content of the save register 121 to the address of the current error data and sets the address in the RP register 102. In the case of an address match, the save register 121 need not be updated.

The retransmission stop circuit 125 monitors the count value of the retransmission counter 124 and does not perform any special processing as long as the value is smaller than a predetermined reference value (predetermined number) N. In this case, transmission is performed again from the data of the address set in the RP register 102 by the retransmission control circuit 123 (that is, data in which a reception error has been detected).

On the other hand, when the count value of the retransmission number counter 124 is equal to or more than the predetermined number N, that is, when an error of the same data is detected N times consecutively, the retransmission stop circuit 125 Is determined to be useless, and R
The contents of the P register 102 are incremented by one. In this case, retransmission of data for which an error has been detected consecutively N times is not performed, the data is discarded, and transmission from the next data is performed. [Fourth Embodiment] FIG. 5 is a block diagram showing a data transmission / reception system according to a fourth embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

The system shown in FIG. 5 uses a communication device 130 instead of the communication device 110 of the system shown in FIG. The communication device 130 is different from the communication device 110 in FIG. 2 in that a retransmission control circuit 123 having a save register 121 is used instead of the retransmission control circuit 103, similarly to the communication device 120 in FIG. Retransmission counter 1
24 and the retransmission stop circuit 125 are added.
The operations of the retransmission control circuit 123, the retransmission number counter 124, and the retransmission stop circuit 125 in the communication device 130 are as follows.
The same as in the communication device 120 in FIG. 4 described above, the number of retransmissions of the same data is limited by the communication device 130. [Fifth Embodiment] FIG. 6 is a block diagram of a data transmission / reception system according to a fifth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The system of FIG. 6 uses a communication device 220 instead of the communication device 200 of the system of FIG. This communication device 220 is different from the communication device 200 in FIG. 1 in that a continuous retransmission detection circuit 223 having a save register 221, a retransmission number counter 224, a retransmission stop circuit 2
25 and an output gate 226 for permitting / prohibiting error detection notification from the error detection circuit 203 to the retransmission control circuit 103 in the communication device 100 has been added.

The save register 221 in the continuous retransmission detection circuit 223 holds the contents of the WP register 202 (the address of the previous error data) when the error detection circuit 203 previously detected an error in the received data. It is for.

When the error detection circuit 203 detects an error in the received data, the continuous retransmission detection circuit
The address indicated by the P register 202 (the address of the current error data) is compared with the address of the previous error data held in the save register 221.

If the address of the current error data and the address of the previous error data match, the continuous retransmission detection circuit 223 determines that retransmission of the same data is to be repeated. Increment the content by one. If the address of the current error data does not match the address of the previous error data, the continuous retransmission detection circuit 223 determines that the same data is not retransmitted, and sets the retransmission number counter 224 to “0”. "clear.

When the retransmission counter 224 is operated, the continuous retransmission detection circuit 223 updates the content of the save register 221 to the address of the current error data. In the case of an address match, the save register 221 need not be updated.

The retransmission stop circuit 225 monitors the count value of the retransmission number counter 224. If the count value is smaller than the predetermined number N, the output gate 226 is set to the output enable state, and the error detection circuit 203 Is transmitted to the retransmission control circuit 103 of the communication device 100. In this case, transmission is performed again from the data in which the reception error is detected.

On the other hand, when the count value of the retransmission number counter 224 is equal to or more than the predetermined number N, that is, when an error of the same data is detected N times consecutively, the retransmission stop circuit 225 Is determined to be useless, the output gate 226 is set to the output disable state, and the error detection notification from the error detection circuit 203 is sent to the communication device 100.
Is not transmitted to the retransmission control circuit 103. At the same time, the retransmission stop circuit 225 increments the content of the current WP register 202 by one, and updates the address of the data reception register file 201 in which the data in which the reception error has been detected is to be written to the address of the next data.

As described above, when an error of the same data is detected N times in a row, the communication apparatus 100 does not retransmit the data in which the error was detected N times in a row, and the communication apparatus 220 The same transmission processing as in the normal state where no data error is detected is performed. On the communication device 220 side, data in which an error is detected N times consecutively is discarded, and processing for reading the next data from the buffer register file 104 to the data receiving register file 201 is performed. [Sixth Embodiment] FIG. 7 is a block diagram of a data transmission / reception system according to a sixth embodiment of the present invention.

The system of FIG. 7 uses a communication device 220 of FIG. 6 instead of the communication device 200 of the system of FIG. Therefore, the operation of communication device 220 in the system of FIG. 7 is the same as that of communication device 220 in the system of FIG. 6, and the number of retransmissions of the same data is limited by communication device 220.

In the first to sixth embodiments described above,
Although the description has been made assuming that the initial values of the RP register 102 and the WP register 202 are both “0”, the present invention is not limited to this, and the values need not always be the same.
However, when the initial values of the RP register 102 and the WP register 202 are different, the address is transmitted from the address transmission circuit 204 as an address to be set in the RP register 102 for retransmission due to error detection of received data (the The address cannot be used as it is, and it is necessary to adjust (increase or decrease) only the difference between the initial values.

[0085]

As described above in detail, according to the present invention, the data transmission storage means of the transmitting communication device (first communication device) and the data receiving storage device of the receiving communication device (second communication device). A transfer operation (transmission operation) from the data transmission storage unit (to the buffer storage unit) and a reception side (from the buffer storage unit) in the transmission-side communication device are performed by the buffer storage unit provided between the storage unit and the storage unit. Even when the receiving operation to the data receiving storage means in the communication device can be performed asynchronously and the subsequent data is transferred without waiting for the reception error detection result from the receiving communication device in the transmitting communication device, the receiving side When an error in the received data is detected by the communication device, the order of the data in which the error has occurred is determined from the write position in the data receiving storage unit in which the data is to be written, and the data is retransmitted. It can be carried out.

As described above, since the data can be continuously transferred in the transmitting communication device without waiting for the result of the reception error detection in the receiving communication device, the data transfer performance is improved. Further, according to the present invention, while permitting the transmitting communication device to continuously perform data transfer without waiting for a reception error detection result at the receiving communication device, the data transmitting and receiving device in the transmitting communication device is not required. Stopping the writing of new data for transmission to the storage location of the data that is likely to be retransmitted and stored in the storage means, thereby transmitting the data that is likely to be retransmitted to the transmitting side. Since it can be guaranteed that the data is left in the device, when an error in the data received by the receiving communication device is detected, the data can be reliably retransmitted.

Further, according to the present invention, since retransmission of the same data is detected more than a predetermined number of times and the retransmission is prevented from being performed more than once, the retransmission of the same data is repeated. Bus lock between the communication devices due to this can be avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data transmission / reception system according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a data transmission / reception system according to a second embodiment of the present invention.

FIG. 3 is a diagram for explaining a control operation of a write control circuit 112 in FIG. 2;

FIG. 4 is a block diagram of a data transmission / reception system according to a third embodiment of the present invention.

FIG. 5 is a block diagram of a data transmission / reception system according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a data transmission / reception system according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram of a data transmission / reception system according to a sixth embodiment of the present invention.

FIG. 8 is a block diagram of a conventional data transmission / reception system.

[Explanation of symbols]

100, 110, 120, 130 ... communication device (first communication device), 101 ... data transmission register file (data transmission storage means), 102 ... RP register (read pointer register, read pointer means), 103, 1
23 ... retransmission control circuit, 104 ... buffer register file (buffer storage means), 111 ... WP register (write pointer register, first write pointer means), 112
... Write control circuit, 121, 221 Save register, 12
4, 224: retransmission counter, 125, 225: retransmission stop circuit, 200, 220: communication device (second communication device), 201: data reception register file (data receiving storage means), 202: WP register ( Write pointer register, write pointer means, second write pointer means), 113, 203 ... error detection circuit, 204 ...
Address transmission circuit, 223... Continuous retransmission detection circuit, 226
... the output gate.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 1/16 G06F 13/00 351 H04L 13/00 H04L 29/00

Claims (5)

(57) [Claims] 1. A data transmission / reception system in which data transmitted from a first communication device in a predetermined unit is received by a second communication device, wherein the first data for storing transmission data to the second communication device is stored in the first communication device. Data transmission storage means provided in the communication device, and read pointer means for designating a read position of the data transmission storage means, each time data in a predetermined unit is read from the storage means. Read pointer means for updating the read position for the next data read, and temporarily storing data read from the data transmission storage means and outputting the data to the second communication device in a first-in first-out manner. Buffer storage means; and the second storage means for storing data output from the buffer storage means to the second communication device as reception data.
And a write pointer means for designating a write position of the data receiving storage means. Each time data is written to the storage means, the next data writing operation is performed. Write pointer means for updating the write position, error detection means for detecting the presence or absence of an error in data output from the buffer storage means to the second communication device, and a data error by the error detection means. Is detected, a read position corresponding to the write position indicated by the write pointer means at that time is set in the read pointer means, and the read position in the data transmission storage means specified by the read pointer means is set. A data transmission / reception system comprising retransmission control means for causing retransmission from data. 2. The communication device according to claim 1, further comprising first to third communication devices, wherein the data transmitted from the third communication device in a predetermined unit is transmitted to the first communication device.
A data transmission / reception system that receives data at the communication device and transmits the data to the second communication device, wherein the data transmitted from the third communication device is stored as transmission data to the second communication device. And a first write pointer unit for designating a write position of the data transmission storage unit, wherein each time data is written to the storage unit, the next data is stored in the storage unit. a first write pointer means for updating the write position for writing, a read pointer means for specifying the read position of the data transmission storing means, data of a predetermined unit <br/> from the storage means A read pointer for updating the read position for reading the next data every time the data is read; Buffer storage means for temporarily storing output data and outputting the data to the second communication device in a first-in first-out manner; and data output from the buffer storage device to the second communication device as reception data Said second for storing
And a second write pointer means for designating a write position of the data receiving storage means, wherein each time data is written to the storage means, Second write pointer means for updating the write position for writing; error detection means for detecting the presence or absence of an error in data output from the buffer storage means to the second communication device; When a data error is detected by the error detection means, a read position corresponding to the write position indicated by the second write pointer means at that time is set in the read pointer means, and the data designated by the read pointer means is set. Retransmission control means for performing retransmission from the data at the read position in the transmission storage means; and the first and second write pointer means Is monitored, and new data is written from the third communication device to the storage position of the data that is likely to be retransmitted stored in the storage unit for data transmission. A data transmission / reception system, comprising: write control means for suspending data transmission. 3. A retransmission number counter means for counting the number of times retransmission of the same data is continuously performed, and said read pointer when the number of retransmissions counted by said retransmission number counter means becomes a predetermined number or more. 3. The data transmission / reception system according to claim 1, further comprising means for updating the read position indicated by the means to indicate the position of the next data and stopping retransmission. 4. A retransmission number counter means for counting the number of times retransmission of the same data is successively performed, and said error is detected when the number of retransmission times counted by said retransmission number counter means exceeds a predetermined number. Means for masking the detection of a data error by the detection means, updating the write position indicated by the write pointer means to indicate the position of the next data, and stopping the retransmission. The data transmission / reception system according to claim 1, wherein 5. A retransmission number counter for counting the number of times retransmission of the same data is continuously performed, and an error when the number of retransmissions counted by the retransmission number counter exceeds a predetermined number. Means for masking the detection of a data error by the detection means, updating the write position indicated by the second write pointer means to point to the next data position, and suspending the retransmission. The data transmission / reception system according to claim 2, wherein: