JPH05241985A - Input/output controller - Google Patents

Abstract

PURPOSE:To provide an input/output controller to delete only block data in which an error occurs as the input/output controller which controls plural input/ output devices. CONSTITUTION:This controller is provided with an error detection circuit 7 which detects an error in reception, FIFO memory 4 which buffets received data and an output bit from the error detection circuit 7 simultaneously, and a means which decides the effectiveness/ineffectiveness of data by the value of each output bit when the data is read out from the FIFO memory 4. Thereby, only the block data in which the error occurs can be deleted even when plural pieces of block data are stored in one FIFO memory 4, and another block data can be processed, which prevents one error from being affected on another data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device for controlling an input / output device using block data such as packets.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional input / output control device. In the figure, reference numeral 1 denotes the entire input / output control device. Reference numeral 2 denotes an input / output device controlled by the input / output control device 1 (a plurality of devices are connected by a bus, but only one is shown in the figure),
Reference numeral 3 is an input / output bus, 4a is a FIFO (first in first out) memory for storing data received from the input / output device 2, 5 is a flow of received data, 6 is a write signal of received data 5, and 7 is received. An error detection circuit for performing an error check of the data 5, 8a is an error signal output when an error is detected by the error detection circuit 7, and 9 is a FIFO.
Empty signal of memory 4a, 10 is FIFO memory 4
Data read from a, 11 is the FIFO memory 4a
A data read signal to, 12 is a microprocessor for controlling the whole.

Next, the operation will be described. I / O device 2
Starts packet transfer at an arbitrary timing. This packet transfer is performed by synchronizing the unit data 5 with the write signal 6 and sending it to the input / output bus 3 for the capacity of the packet. On the other hand, the FIFO memory 4a in the input / output control device 1 unconditionally writes the data 5 at that time when the write signal 6 is output. At the same time, the error detection circuit 7 checks the validity of the data 5 at that time.
When an error is detected, the error signal 8a is output.

However, since the input / output device 2 transfers data in bursts, writing to the FIFO memory 4a continues even if the error signal 8a is output.
When the transmission of one packet is completed, the input / output device 2
Transfers a new packet at an arbitrary timing. Therefore, a plurality of packets can be stored in the FIFO memory 4a. As a result, the normally received packet and the packet in which the error has occurred are mixedly stored in the FIFO memory 4a.

On the other hand, the microprocessor 12 periodically monitors the state of the FIFO memory 4a, and if it finds that one or more packets are received in the FIFO memory 4a, it reads the packets one by one and performs the processing. . However, when the error signal 8a is output from the error detection circuit 7, reading from the FIFO memory 4a is not performed and all the data stored in the FIFO memory 4a is discarded. The reason for this is that it is not possible to determine how much of the data stored in the FIFO memory 4a is normally received data.

[0006]

Since the conventional input / output control device as described above is constructed and operates as described above,
When an error occurs in the reception of one packet, all the packets in the FIFO memory must be discarded, and it is necessary to handle the error with a plurality of packets. Also, the error related to one packet is the error of the other packet. There were problems such as causing the

The present invention has been made in order to solve such a problem, and provides an input / output control device capable of discarding only a packet in which an error has occurred and normally processing a packet in which no error has occurred. It is an object.

[0008]

In the input / output control device according to the present invention, when a packet is received and written in the FIFO memory, the error signal from the error detection circuit is also written in the FIFO memory at the same time. As a prior art somewhat related to the present invention, there is an interprocessor data transfer system disclosed in Japanese Patent Laid-Open No. 62-206657.

[0009]

In the present invention, the received packet is FI
By reading from the FO memory and checking the bit corresponding to the error signal, it is possible to judge the validity of the data and distinguish whether the packet is valid or invalid.

[0010]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 shows the entire input / output control device. Two
Is an input / output device controlled by the input / output control device 1 (a plurality of devices are connected by a bus, but only one is shown in the figure). 3 is a connection between the input / output control device 1 and the input / output device 2. The input / output bus 4 is an F for storing data received from the input / output device 2.
IFO (first in first out) memory, 5 is a flow of received data, 6 is a write signal of the received data 5, 7 is an error detection circuit for performing an error check of the received data 5, and 8 is an error in the error detection circuit 7. Error signal output when is detected, 9 is an Empty signal indicating the state of the FIFO memory 4, 10 is data read from the FIFO memory 4, 11 is a data read signal to the FIFO memory 4, and 12 is the whole It is a controlling microprocessor.

FIG. 2 is a diagram showing a packet storage state of the FIFO memory 4 shown in FIG. 1. In the figure, 41 is an error check bit indicating whether or not an error has occurred in the stored packet.

Next, the operation will be described. I / O device 2
Starts packet transfer at an arbitrary timing. This packet transfer is performed by synchronizing the unit data 5 with the write signal 6 and sending it to the input / output bus 3 for the capacity of the packet. On the other hand, the FIFO memory 4 in the input / output control device 1 unconditionally writes the data 5 at that time when the write signal 6 is output. At the same time, the error detection circuit 7 checks the validity of the data 5 at that time. When an error is detected, the error signal 8 is output.

This error signal 8 is connected to the input data of the FIFO memory 4, and is written in the error check bit 41 of the FIFO memory 4 by the write signal 6 in the same manner as the above-mentioned data 5. Further, since the input / output device 2 transfers the data in a burst, even if an error occurs, the writing to the FIFO memory 4 is continued with the writing of the error signal 8.

When transmission of one packet is completed, the input / output device 2 transfers a new packet at an arbitrary timing. Therefore, the FIFO memory 4 can store a plurality of packets and the error signal 8 at that time. As a result, the normally received packet and the packet in which the error has occurred are mixedly stored in the FIFO memory 4.

On the other hand, the microprocessor 12 periodically monitors the Empty signal 9 of the FIFO memory 4,
When it is found that one or more packets are stored in the FO memory 4, the packets are read one by one and the processing is performed. However, if the error check bit 41 of the read data 10 is significant, the data for that packet is discarded. If there are still packets in the FIFO memory 4, the packets are sequentially read and the error check bit 41 corresponding to the error signal of the data is checked. If this is not significant, the packets are sequentially processed as normal packets.

[0016]

As described above, according to the present invention, a packet in which an error has occurred and a normal packet can be distinguished and processed, and the range of the error can be minimized, and a highly reliable device can be obtained. There is an effect that is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a packet storage state of the FIFO memory 4 shown in FIG.

FIG. 3 is a block diagram showing a conventional device.

[Explanation of symbols]

 1 I / O control device 2 I / O device 3 I / O bus 4 FIFO memory 7 Error detection circuit 8 Error signal 41 Error check bit

Claims (1)

[Claims] 1. An input / output control device for controlling a plurality of input / output devices, a receiving circuit for receiving data transmitted from the input / output device, an error detection circuit for detecting an error during reception, received data, and A FIFO (first-in-first-out) that simultaneously buffers output bits from the error detection circuit
First out) memory, and an input / output control device comprising means for judging validity / invalidity of each of the data by the value of each output bit when reading data from the FIFO memory.