JP2002007312A - Information input/output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information input/output device capable of inputting/ outputting with respect to the packet of a variable length. SOLUTION: This information input/output device is provided with a packet input side FIFO 1 for storing a packet inputted from a system side, area 2 for storing packet delimiter information for storing the breakpoint information of the packet, packet output side FIFO 3 and/or 5 for storing an adjusting packet, microcomputer 7 for generating the adjusting packet by reading out the packet stored in the packet input side FIFO 1 and adjusting the size of the packet and for writing the adjusting packet into the packet output side FIFO 3 and/or 5, and packet delimiter information read circuit 8 and/or 9 for reading the adjusting packet out of the packet output side FIFO 3 and/or 5 on the basis of the breakpoint information of the adjusting packet and outputting the adjusting packet to the 1394 interface side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information input / output device for inputting / outputting a packet between an external interface and an information processing device, for example.

[0002]

2. Description of the Related Art Conventionally, I as an external interface
EEE1394 standard interface (hereinafter 139)
4 interfaces. ) Input / output a packet to an information processing system (hereinafter, referred to as a system) that performs predetermined signal processing. 139 from the system side
4 when outputting a packet on the interface, the timing of the packet output from the system side and 139
It is conceivable that the timing of the packet output on the four interfaces is different.

Conversely, when a packet is input from the 1394 interface to the system, the timing of a packet input from the 1394 interface may be different from the timing of a packet input to the system.

In consideration of such a case, a FIFO (First I / O) is provided between the system and the external interface.
In general, the timing is controlled by using the n first out memory.

In this FIFO control, a single-stage FIFO that handles only the input / output of fixed-length packets is arranged between the 1394 interface side and the system side, which are input / output systems at different timings. Only the timing was controlled using a microcomputer (hereinafter referred to as a microcomputer) or hardware.

[0006]

The above-mentioned conventional FIF
In the control of O, the size of the packet is a fixed length, and since the size of the packet is determined, it is possible to output the data to the 1394 interface or the system using a hardware circuit for each fixed length packet. It was possible.

However, if the originally input packet has a variable length, a microcomputer or a hardware circuit is used to find a break of the packet when reading out from the FIFO and output the packet to the 1394 interface or the system for each packet. In this case, an additional process of searching for a packet break by analyzing packet data is required, and the process for this is complicated (Japanese Patent Laid-Open Nos. Hei 6-243672 and Hei 8-305220). ,
See JP-A-11-98098).

Therefore, the present invention has been made in view of such a point, and an object of the present invention is to provide an information input / output device capable of easily inputting / outputting a variable-length packet.

[0009]

The information input / output device of the present invention is applied to an information input / output device for inputting / outputting a packet between one side and the other side.

In particular, the information input / output device of the present invention is provided on one side and has a first storage area for storing a packet input from one side or a predetermined adjustment packet input from the other side. , A first storage means having a second storage area for storing break information of a packet or an adjustment packet, and an adjustment packet input from one side or input from the other side, provided on the other side. A second storage unit having a third storage area for storing a packet to be stored, a fourth storage area for storing adjustment packets or information on a break between packets, and a first storage unit or a second storage unit. Control means for reading out the stored packet, adjusting the size of the packet if necessary, generating an adjustment packet, and writing the adjustment packet to the second storage means or the first storage means; Based on the separated first information modification packet, in which a reading means for outputting the other side or one side reads the adjustment packet from the second memory means or the first memory means.

Therefore, according to the present invention, the following operations are performed. The first storage area of the first storage means stores a packet input from one side. The second storage area stores information on a break point of the packet.

A third storage area of the second storage means stores the adjustment packet processed by the control means. The fourth storage area stores information on a break between packets.

[0013] The control means may be a first storage means.
The packet stored in the storage area is read out and the size of the packet is adjusted to generate an adjustment packet, or the stored packet is read out as it is, and the adjustment packet or the packet read out as it is is stored in the second storage. In addition to writing the packet delimiter information stored in the second storage area and generating the packet delimiter information, the packet delimiter information is written to the fourth storage area.

As described above, the first and the second sides are respectively provided on the input side and the output side.
And the second storage means are provided, and the packet is transferred from the input side to the output side using data transfer by the control means.

[0015] Then, the reading means reads the adjustment packet from the second storage means and outputs it to the other side based on the break information of the adjustment packet. When the input and the output are switched, the other side is the input side, and one side is the output side.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The information input / output device according to the present embodiment maintains an area for storing packet break information separately from a FIFO area for storing packets.
The packet is processed using a microcomputer or the like, and even if the size of the packet changes, the FIFO is
, One packet at a time.

The information input / output device according to the present embodiment will be described below. FIG. 1 is a diagram showing a configuration of a system to which the information input / output device of the present embodiment is applied. In the system shown in FIG. 1, the rightward arrow in the figure shows a case where a packet input from the system side is processed by the microcomputer and transmitted to the 1394 interface. Conversely, the leftward arrow in the figure indicates a case where the packet received from the 1394 interface side is processed by the microcomputer and supplied to the system side. Here, the former first embodiment will be described first. In FIG. 1, the number of FIFOs is two on the 1394 interface side and one on the system side.
An example will be described.

Referring to FIG. 1, a case will be described in which a 1394 header is added by a microcomputer to a packet (data only) input from the system side at the timing of the system, and the packet is transmitted on the 1394 interface.

The information input / output device of the present embodiment is provided on the system side and stores an input-side FIFO 1 for storing a packet input from the system side, and an area for storing packet boundary information for storing packet boundary information. 2 is provided.

Further, the information input / output device of the present embodiment
An output side F provided on the 1394 interface side for storing an adjustment packet processed by a microcomputer described later.
It comprises an IFO 3 and a packet break information storage area 4 for storing packet break information.

The packet delimiter information storage area 4 is an area for storing packet delimiter information indicating whether the corresponding data in the output FIFO 3 is the beginning of a packet, the middle of a packet, or the end of a packet. .

The information input / output device according to the present embodiment
An output side F provided on the 1394 interface side for storing an adjustment packet processed by a microcomputer described later.
It comprises an IFO 5 and a packet break information storage area 6 for storing packet break information.

Areas 4 and 6 for storing packet break information
Is an area for storing packet delimiter information indicating whether corresponding data in the output FIFOs 3 and 5 is at the beginning of a packet, in the middle of a packet, or at the end of a packet.

Further, the information input / output device of the present embodiment
A packet stored in the input side FIFO 1 is read out, the size of the packet is adjusted to generate an adjustment packet, and the adjustment packet is output to the output side FIFO 3 and / or the output side FIFO.
In addition to writing to the FO5, the packet separator information stored in the packet separator information storage area 2 is read to generate adjusted packet separator information, and the adjusted packet separator information is stored in the packet separator information storage area 4 and And / or a microcomputer 7 for writing to the packet break information storage area 6.

Further, the information input / output device of the present embodiment
Output FIF based on the adjustment packet delimiter information
A packet delimiter information read circuit 8 and / or a packet delimiter information read circuit 9 for reading out the adjustment packet from the O3 and / or the output FIFO 5 and outputting it to the 1394 interface side.

The information input / output device according to the present embodiment thus configured operates as follows.

The input FIFO 1 stores a packet input from the system. The packet separator information storage area 2 stores packet separator information.

The packet is sent from the system to the input FIFO.
At the time of entering the packet, a mark indicating the head of the packet and a mark indicating the end of the packet are automatically added to the head of the packet, and this information is stored in the packet separation information storage area 2. You. Note that no mark is placed in the middle of the packet.

FIG. 3A shows a state of a packet input from the system and stored in the input FIFO. FIG.
4A, an arrow 4 shown as packet delimiter information 41;
2, 43, 44, 45, 46, and 47 are packets 48, 4 stored in the packet separation information storage area 2.
These marks indicate the divisions of 9, 50, 51, and 52.

In FIG. 3A, the mark indicating the head of the packet and the mark indicating the end are shown as being the same, but the present invention is not limited to this, and the mark indicating the head of the packet may be distinguished from the mark indicating the end. As described above, various methods are conceivable for marking each of the beginning, the middle, and the end of the packet, but any method may be used as long as the delimitation of the packet is known.

The output FIFO 3 stores an adjustment packet processed by a microcomputer described later. The packet delimiter information storage area 4 stores packet delimiter information.

The output FIFO 5 stores an adjustment packet processed by a microcomputer described later. The packet separator information storage area 6 stores packet separator information.

The microcomputer 7 reads out the packet stored in the input FIFO 1 and adjusts the size of the packet to generate an adjustment packet, or reads out the stored packet as it is to read the adjustment packet or read it out as it is. The output packet is written into the output FIFO 3 and / or the output FIFO 5, and the packet delimiter information stored in the packet delimiter information storage area 2 is read to generate adjusted packet delimiter information.
The adjusted packet break information is stored in the packet break information storage area 4 and / or the packet break information storage area 6
Write to. Also, after checking the data of the packet read from the input FIFO 1 with the microcomputer 7 or without checking using the DMA transfer, the output FIFO is directly used.
3 and / or the output FIFO 5.

In FIG. 3B, the packets are processed by the microcomputer 7 and the adjusted packets 67, 68, 69 and 70 are output as the output FIFO3 and / or the output FIFO5.
2 shows the state of the packet stored in. In FIG. 3B,
Arrows 62, 63, and 6 shown as packet separation information 61
4, 65 and 66 are marks indicating the breaks of the adjustment packets 67, 68, 69 and 70 stored in the packet break information storage area 4 and / or the packet break information storage area 6. The contents of the adjustment packet will be described later.

As described above, the FI on each of the input side and the output side
An FO is prepared, data is transferred by the microcomputer 7, and DMA (Direct Memory Access) is additionally provided.
s) Transfer the packet from input FIFO 1 to output FIFO 3 and / or output FIFO 5 using transfer.

Then, the packet delimiter information reading circuits 8 and 9 read out the adjustment packet from the output FIFO 3 and / or the output FIFO 5 based on the delimiter information of the adjustment packet and output it to the 1394 interface.

In FIG. 1, two output FIs are used.
Although the example in which the FOs 3 and 5 are provided is shown, the invention is not limited thereto, and a plurality of input FIFOs 1 and output FIFOs 3 and 5 may be provided. In addition, any side can select an arbitrary number of FIFOs, so that packets can be distributed to each FIFO according to the type of the packet. Further, one FIFO may be provided on each side.

Next, processing that can be performed by the microcomputer 7 will be described. First, the microcomputer 7 reads data from an arbitrary input FIFO 1. Here, the unit of data read is 1 quadlet (4 bytes), but the present invention is not limited to this.

Second, by referring to the delimiter information storage area 2 of an arbitrary input FIFO 1, it is recognized whether the next data to be read is the beginning, middle or end of the packet.

Third, reading of data from an arbitrary input FIFO 1 or arbitrary output F of arbitrary data.
The data is written to the IFO 3 and / or the output FIFO 5, and any delimiter information of the data is written to the packet delimiter information storage area 4 and / or the packet delimiter information storage area 6.

Next, processing that can be performed using DMA transfer will be described. The following processing is performed by a DAM controller (not shown).

First, data of an arbitrary input FIFO 1 is transferred to an arbitrary output FIFO 3 and / or an output FIFO 5 with an arbitrary transfer amount.

The following processes can be combined as optional functions that can be specified at the time of transfer.

Second, the head packet information is added to the earliest data that has been DMA-transferred by the output FIFO 3 and / or the output FIFO 5.

Third, the end packet information is added by the output FIFO 3 and / or the output FIFO 5 to the last data transferred by DMA.

Fourth, the packet delimiter information of the input FIFO 1 is copied as it is to the output FIFO 3 and / or the output FIFO 5 together with the data.

Fifth, a transfer amount larger than one packet of the input FIFO 1 is set, and when the end of the packet comes,
Thereafter, arbitrary data is inserted until the set transfer amount is reached. By this process, the variable-length packet can also be set to a fixed length.

Sixth, when a transfer amount larger than one packet of the input FIFO 1 is specified and the end of the packet comes,
Stop the DMA transfer. Further, when the end of the packet comes, in a mode in which the DMA transfer is not completed, a plurality of packets can be collectively DMA-transferred by setting a transfer amount larger than one packet. At this time, control is performed by adding break information to be written to the output FIFO only at the beginning and / or end of the collectively transferred packets, or by copying the packet break information of the transfer source FIFO as it is. Thus, it is possible to determine whether the packets transferred together are handled as one packet or divided and handled.

Seventh, by referring to the information in the delimiter information storage area 2, it is recognized whether the next data to be read is the beginning, the middle, or the end of the packet.

By performing the data transfer and the DMA transfer by the microcomputer 7 in combination as described above,
For example, the packet can be processed as shown in FIG.

FIG. 2 is a diagram showing an example of packet processing. In FIG. 2A, a packet 20 input to the microcomputer and the DMA controller has packet delimiter information 2
1, the microcomputer read data 24 read from the input side FIFO 1 by the microcomputer 7 and a DMA (not shown) at the time of DMA transfer.
DM read from input FIFO1 by controller
A read data 25.

Then, the microcomputer 7 sets the output FIFO 3
And / or header 3 of the packet in the output FIFO 5
Write 4 In FIG. 2B, the microcomputer and the DMA
The packet 30 indicating the adjustment packet 38 output from the controller is divided by arrows 32 and 33 as indicated by packet delimiter information 31. The microcomputer additional data 34 added by the microcomputer 7 and the microcomputer read data 24 7, the DMA transfer data 36 obtained by reading the DMA read data 25 by a DMA controller (not shown) at the time of the DMA transfer, and the DMA transfer added by the DMA controller (not shown) at the time of the DMA transfer. It has optional additional data 37.

That is, at the time of output, the microcomputer 7 adds the microcomputer additional data 34 to the foremost data as packet head information. This uses the processing of the third microcomputer described above.

Next, at the beginning of the input side FIFO1, for example, 4
The byte (not limited to this, for example, 4 bytes here) is read by the microcomputer 7, changed to a certain value, and the microcomputer replacement data 35 is written to the output FIFO3 and / or the output FIFO5. This uses the processing of the first and third microcomputers described above.

Then, the remaining data remaining in the input FIFO 1 is DMA-transferred by a DMA controller (not shown). At this time, a transfer amount larger than one packet is designated, and when the end information of the packet comes, a mode in which the DMA transfer is stopped, a mode in which arbitrary data is inserted until a predetermined transfer amount is reached, and a mode in which the DMA transfer is terminated. As a switch for switching between a mode for inputting information, for example, IC
Make sure to set the control bit. As a result, the DMA transfer data 36 is transferred from the input side to the output side.
After MA transfer, arbitrary data is added as DMA transfer optional additional data 37.

In this way, the above-described operation is repeated for one packet of the input-side FIFO 1, and the output-side FIFO 1
FIG. 3B shows an example of packet processing when the packet is transferred to O3 and / or the output side FIFO5. In the input-side FIFO 40 shown in FIG. 3A, relatively short packets 49 and 52 are input from the system side at a rate of one out of three packets.

On the other hand, the output-side IF shown in FIG.
In O60, after the DMA transfer, the relatively long DMA transfer optional additional data 64d is inserted, so that the output side FIFO
3 and / or the output FIFO 5 have the same size packet. Also, the short packets 49, 52
During the DMA transfer, the data does not need to be replaced by the microcomputer, and is not replaced.

The adjustment packet 67 includes the microcomputer additional data 62a, the microcomputer replacement data 62b,
Transfer data 62c and DMA transfer optional additional data 62d
And The adjustment packet 68 has microcomputer additional data 63a, microcomputer replacement data 63b, DMA transfer data 63c, and DMA transfer optional additional data 63d. The adjustment packet 69 has microcomputer additional data 64a, DMA transfer data 64c, and DMA transfer optional additional data 64d. Adjustment packet 70
Has microcomputer additional data 65a, microcomputer replacement data 65b, DMA transfer data 65c, and DMA transfer optional additional data 65d.

For example, as described above, data transfer by the microcomputer 7 and D by the DMA controller (not shown)
It is possible to process a packet in combination with MA transfer. These are merely examples, and various types of packets can be processed by combining the above-described processes.

Further, even if the size of the packet changes due to the processing of the packet, the packet delimiter information storage area 4 and / or the output FIFO 3 and / or the output FIFO 5 of the output FIFO 5 can be used.
Alternatively, since the packet separation information is stored in the packet separation information storage area 6, the packet separation information reading circuit 8 and / or the packet separation information reading circuit 9 shown in FIG. It is possible to output at the timing of the 1394 interface for each packet.

The functions of the packet delimiter information reading circuit indicated by 8, 9 and 10 in FIG. 1 include the following in addition to the above. On the system side, there is a timing at which the system processes the packet. Therefore, a packet must be input to the system at that timing. Its timing depends on the input from the port, etc.
The read circuit can be known in some way.

Also, on the 1394 interface side,
There are timings when the packet may be output and timings when the packet must not be output. The reading circuit can also know this by some method such as viewing information of a cycle start packet on the 1394 format or a signal on the bus.

Next, a description will be given of a second embodiment in which a packet received from the 1394 interface side indicated by an arrow pointing to the left in the figure is processed by the microcomputer and supplied to the system side.

In this case, instead of the packet delimiter information reading circuits 8 and 9 on the 1394 interface side shown in FIG. Performs processing for the flow.

Here, at the time of input from the 1394 interface side, the packet delimiter information reading circuits 8 and 9 are invalidated by, for example, a switch, and the packet is passed. Process. Note that 1394
At the time of output to the interface side, the packet delimiter information readout circuit 10 is similarly invalidated, and the packet delimiter information readout circuits 8 and 9 are activated.

Thus, the packet input from the 1394 interface is stored in the output FIFO 3 and / or the output FIFO 5, and the packet delimiter information storage area 4 and / or the packet delimiter information of the output FIFO 3 and / or the output FIFO 5 are stored. The packet delimiter information is stored in the storage area 6, and the packet is processed using the microcomputer 7 and the DMA transfer to generate an adjustment packet.
The adjustment packet is stored in the input FIFO 1 and the input FI
The packet delimiter information is stored in the packet delimiter information storage area 2 of the FO1, and the packet delimiter information reading circuit 1
Using 0, it is possible to output at the system timing for each packet based on this delimiter information.

[0067]

The information input / output device according to the present invention is provided on one side of an information input / output device for inputting / outputting a packet between one side and the other side, and receives an input from one side. First storage means having a first storage area for storing a packet or a predetermined adjustment packet input from the other side, and a second storage area for storing break information of the packet or the adjustment packet; Provided on the other side,
A second storage area for storing an adjustment packet input from one side or a packet input from the other side, and a fourth storage area for storing adjustment packet or packet break information; A storage unit that reads out a packet stored in the first storage unit or the second storage unit, adjusts the size of the packet as necessary, generates an adjustment packet, and stores the adjustment packet in the second storage unit. Alternatively, the second storage unit or the first storage unit may be configured based on the control unit that writes to the first storage unit and the break information of the adjustment packet.
Reading means for reading out the adjustment packet from the storage means and outputting the adjustment packet to the other side or one side, so that the packet input from one side or the other side can be processed as it is or unnecessary. For example, even if the header is deleted and the size of the packet is adjusted by processing as necessary by the control means, it is output to one side or the other side for each packet using the packet delimiter information. This has the effect that it can be performed.

In the information input / output device according to the present invention, in the above, the reading means reads the other side from the second storage means or the first storage means to the other side based on the break information of the adjustment packet. Since the adjustment packet is read and output at the timing of the side or at the timing of the one side to one side, it is possible to automatically read the packet at the timing of the output side based on the information of the division of the packet. It works.

Further, in the information input / output device of the present invention, the control means may recognize the break information of a packet to be read next from the first storage means or the second storage means in advance, and then, Is read, and the break information of the adjustment packet and any adjustment packet is written in the second storage means or the first storage means. The control means adjusts the size of the packet according to the break information, and This produces an effect that the sizes can be made uniform.

Further, the information input / output device of the present invention uses the information of the leading and trailing ends of the packet identified prior to the reading by the reading means, instead of the information of the delimiter of the packet. , It is possible to determine whether the data of the packet to be read next is at the beginning, middle, or end of the packet.

Further, in the information input / output device of the present invention, in the above, the control means reads the packet from the first storage means or the second storage means using DMA transfer,
Since the adjustment packet is written in the second storage unit or the first storage unit, there is an effect that the packet can be transferred at a high speed.

In the information input / output device of the present invention, the first delimiter information is added to the first packet of the DMA transfer in the second storage means or the first storage means of the transfer destination in the DMA transfer. , Or the last packet of the DMA transfer is provided with the end information of the end, or the information of the first storage means or the second storage means of the transfer source is directly transferred by DMA to the transfer destination together with the packet. , Or any combination thereof, or whether the break information is not included in the DMA transfer, is arbitrarily selected. Therefore, if necessary, the packet is processed and transferred, for example, as convenient for the system side. It has the effect of being able to do so.

Further, in the information input / output device of the present invention, before the DMA transfer, the break information of the next packet to be DMA-transferred is read from the first storage means or the second storage means of the transfer source. Therefore, it is possible to pre-read the packet delimiter information before the transfer from the packet delimiter information storage area provided separately from the packet storage area.

Further, the information input / output device of the present invention, in the above, transfers a plurality of packets or one packet read from the first storage means or the second storage means of the transfer source by the DMA transfer. The second storage means or the first
When DMA transfer is performed collectively or one by one to the storage means, the information of the packet delimiter is also transferred at the same time. Therefore, a transfer amount larger than one packet is set.
When the transfer is performed in a mode in which the DMA transfer is not terminated even when the packet delimiter information arrives, a plurality of packets are
A transfer is possible. Further, when a plurality of packets are transferred in one DMA transfer, a mode in which the packet delimiter information is inserted only at the beginning and end of the DMA transfer is set, and the plurality of packets transferred in one transfer are output to the output side. The packet is handled as one packet by the FIFO and read. When a plurality of packets are transferred by one DMA transfer in the break information copy mode, the output FIFO
In O, the packet is handled and read as a plurality of packets, similarly to the input-side FIFO. Thus, there is an effect that various DMA transfers can be performed according to the convenience of the system.

In the information input / output device of the present invention, if the boundary information is read out from the first storage means or the second storage means of the transfer source during the DMA transfer,
It is possible to arbitrarily select whether or not to stop the DMA transfer even if the predetermined transfer amount of the MA transfer has not been reached. If the DMA transfer is to be stopped, after the last transferred packet, the transfer is performed until the predetermined transfer amount is reached. The user can arbitrarily select whether to stop after inserting any data or to stop without inserting. When the end information of the packet arrives, a mode for stopping DMA transfer and inserting any data until a predetermined transfer amount is reached This mode has an effect that the mode in which the delimiter information is inserted at the end of the DMA transfer and the mode in which the delimiter information is inserted at the end of the DMA transfer can be switched according to the convenience of the system.

In the information input / output device of the present invention, when the packet read from the first storage means or the second storage means of the transfer source becomes empty during the DMA transfer, When the packet written to the second storage means or the first storage means becomes full, the user can arbitrarily select whether to wait for the DMA transfer or stop the DMA transfer. In addition, there is an effect that it is possible to switch between standby and stop of the DMA transfer.

In the information input / output device of the present invention, one side is the information processing apparatus side and the other side is the external interface side in the above description.
4 Even if the size of the packet is adjusted by processing the packet input from the interface or the information processing system side by the control means and the packet size is not known,
1394 for each packet using packet break information
There is an effect that the data can be transmitted to the interface or the information processing system for transmission or information processing.

Further, in the information input / output device of the present invention, the control means reads the packet from the first storage means or the second storage means by using DMA transfer,
The adjustment packet is written in the second storage unit or the first storage unit as it is, or the control unit reads the packet stored in the first storage unit or the second storage unit and adjusts the size of the packet. Arbitrarily selects whether the adjustment packet is to be written to the second storage means or the first storage means. There is an effect that the packet whose size has been processed can be arbitrarily combined and the packet can be output to the output side according to the convenience of the system.

[Brief description of the drawings]

FIG. 1 is a diagram of a configuration example of a system to which an information input / output device according to an embodiment is applied.

FIG. 2 is a diagram showing an example of processing of a packet, FIG. 3A is an example of an input packet, and FIG. 3B is an example of an output packet.

FIG. 3 is a diagram showing an image in a FIFO, and FIG.
3B shows an example of an input-side FIFO, and FIG. 3B shows an example of an output-side FIFO.

[Explanation of symbols]

1 ... Packet input side FIFO, 2 ... Packet delimiter information storage area, 3 ... Packet output side FIFO, 4 ...
... Packet delimiter information storage area, 5... Packet output side FIFO, 6... Packet delimiter information storage area, 7
... Microcomputer, 8... Packet delimiter information readout circuit for reading out packets in packet units based on the packet delimiter information and outputting the packets at the output side timing, 9
... A packet separation information readout circuit that reads packets in packet units based on the packet separation information and outputs the packets at the output side timing. 10... Reads out the packets in packet units based on the packet separation information and outputs the timing. , A packet delimiter information reading circuit for outputting a packet, 20.
1, 22, 23 ... packet delimiter information, 24 ... microcomputer read data, 25 ... DMA read data,
31, 32, 33... Packet delimiter information, 34... Microcomputer addition data, 35.
... DMA transfer data, 37 ... DMA transfer optional additional data, 38 ... adjustment packet,

Claims (12)

[Claims] 1. An information input / output device for inputting / outputting a packet between one side and the other side, the information input / output device being provided on the one side and receiving a packet input from the one side or the other side. A first storage area having a first storage area for storing a predetermined adjustment packet input from the second storage section, and a second storage area for storing the packet or the break information of the adjustment packet; And a third storage area for storing the adjustment packet input from the one side or the packet input from the other side, and a fourth storage area for storing the adjustment packet or the break information of the packet. A second storage unit having a storage area of: a size of the packet read out from the first storage unit or the second storage unit and read as needed. And a control unit that generates the adjustment packet by writing the adjustment packet into the second storage unit or the first storage unit; and the second packet based on the break information of the adjustment packet.
And a reading means for reading out the adjustment packet from the storage means or the first storage means and outputting the adjustment packet to the other side or the one side. 2. The information input / output device according to claim 1, wherein the read unit reads the second storage unit or the first storage unit from the second storage unit or the first storage unit based on break information of the adjustment packet. An information input / output device, wherein the adjustment packet is read and output at the timing of the other side or at the timing of the one side to the one side. 3. The information input / output device according to claim 1, wherein the control unit recognizes in advance the break information of a packet to be read next from the first storage unit or the second storage unit, and then executes the next operation. An information input / output device, which reads out the packet and writes the adjustment packet and delimiter information of any adjustment packet to the second storage means or the first storage means. 4. The information input / output device according to claim 3, wherein information of a leading end and a trailing end of a packet identified prior to reading by said reading means is used in place of the break information of the packet. Information input and output device. 5. The information input / output device according to claim 1, wherein the control unit reads a packet from the first storage unit or the second storage unit using a DMA transfer, and stores the packet in the second storage unit. An information input / output device for writing the adjustment packet into the means or the first storage means. 6. The information input / output device according to claim 5, wherein, in the DMA transfer, a first delimiter is assigned to the first packet of the DMA transfer in the second storage means or the first storage means of the transfer destination. The last packet of the DMA transfer, or the last packet of the DMA transfer, or the delimiter information of the first storage means or the second storage means of the transfer source together with the packet. An information input / output device for arbitrarily selecting DMA transfer to a transfer destination, any combination thereof, or not including break information in DMA transfer. 7. The information input / output device according to claim 5, wherein, prior to the DMA transfer, information on a break of a packet to be DMA-transferred next is transferred from the first storage unit or the second storage unit of a transfer source. An information input / output device characterized by reading. 8. The information input / output device according to claim 5, wherein in the DMA transfer, a plurality of packets or one packet read from the first storage unit or the second storage unit of a transfer source are transferred. An information input / output device characterized in that at the time of collectively or one-by-one DMA transfer to the second storage means or the first storage means, packet break information is transferred at the same time. 9. The information input / output device according to claim 5, wherein, during the DMA transfer, when the break information is read from the first storage means or the second storage means of the transfer source, a predetermined DMA transfer is performed. It is possible to arbitrarily select whether or not to stop the DMA transfer even if the transfer amount has not been reached. If the DMA transfer is to be stopped, arbitrary data is inserted after the last transferred packet until a predetermined transfer amount is reached. An information input / output device characterized by arbitrarily selecting whether to stop after inserting or not to insert. 10. The information input / output device according to claim 5, wherein, during a DMA transfer, when a packet read from the first storage unit or the second storage unit of the transfer source becomes empty, or the transfer is performed. When the packet to be written in the second storage means or the first storage means becomes full, it is possible to arbitrarily select whether to wait for DMA transfer or stop DMA transfer. Information input and output device. 11. The information input / output device according to claim 1, wherein said one side is an information processing device side and said other side is an external interface side. 12. The information input / output device according to claim 1, wherein the control unit reads a packet from the first storage unit or the second storage unit using a DMA transfer, and stores the packet in the second storage unit. Means or the first storage means writes the packet as it is, or the control means reads the packet stored in the first storage means or the second storage means and reads the size of the packet. An information input / output device, wherein the information input / output device is configured to generate the adjustment packet by adjusting the above-mentioned adjustment, and arbitrarily select whether to write the adjustment packet in the second storage means or the first storage means.