JPS61295742A - Circuit processing system with start-stop synchronizing procedure - Google Patents

Abstract

PURPOSE:To initiate an interruption without depending upon the amount of received data by starting the interruption processing part of communication circuit processor when the number of continuous mark bits reaches some specific value or above. CONSTITUTION:The 1st bit '0' received in a reception mode during the scanning of circuits is regarded as a start bit, an arithmetic processing part 21 writes start bit detection in the character control field CCF of a circuit control word memory LCM, and a bit counter ACF0 counts in a next scanning period until character length. Then, while the start bits are monitored, mark bits are counted by the mark bit counter of the ACF1. If the mark bits as much as counter length are received, mark reception is indicated in the circuit parameter/status field LPS of the LCW and an interruption request to a circuit microprocessor LMP12 is sent to store status information in the LPS18 of a control storage 14 is a cycle steal mode.

Description

[Detailed Description of the Invention] [Summary] In line processing in an asynchronous procedure, when a predetermined number of mark bits are consecutively received from the line after receiving one character,
A method for generating an interrupt from the line control unit to the processor unit is shown.

[Industrial application field]

The present invention relates to a communication line processing device, and particularly to a line processing system using an asynchronous procedure.

[Conventional technology]

As an example of the configuration of a communication control device, a central control unit (CCU)
) and the line, a line microprocessor (CMP
), control memory (C3), control memory (C3)
There is a method in which a communication line processing unit Wt,'e consisting of a line control word (LCW) and a line control unit (LC) is provided, and data is transmitted/received under microprogram control.

In this conventional communication line processing device, the end character of the message given by the command from the central control unit (CCU) and the control storage
The end of a message was detected by a line microprocessor (LMP) comparing received characters stored in a line buffer (LB) within the line buffer.

[Problem that the invention seeks to solve]

However, this method has the drawback that the line microprocessor (LMP) 6C cannot be interrupted until the line buffer (LB) reaches a certain number even though all end characters have been received.

Another possible method is to provide a mechanism for detecting the end character (for example, ETX) in the line control unit, but this has the disadvantage of poor compatibility with existing equipment0 [Another means to solve the problem] FIG. 1 is a diagram showing the principle of the present invention. In the figure, 1 is a processor section, 2 is a line control section, 3 is a line charge@word memory, and 4 is a diagram showing the principle of the present invention.
5 is a mark bit counting area, 5 is a mark bit counting processing section, and 6 is an interrupt processing section.

Three line control word memories are provided for each line and contain information for controlling data transmission and reception.

The line control unit 2 controls data transmission and reception to and from the line based on the contents of the line control word.

The processor section 1 controls the line control section 2 and accepts interrupt requests from the line control section 2.

The line control word memory 3 is provided with a mark bit counting area 4 for counting consecutive mark bits received from the line. The mark bit count processing unit 5 processes the contents of the mark bit count/area 4 by, for example, +1 when receiving a mark bit from the line after receiving one character, and processes the contents of the mark bit count/area 4 by, for example, +1 when receiving a space bit from the line. Initialize the contents of 4 (for example, all "'0" processing). When the number of consecutive mark bits exceeds a certain predetermined value, the interrupt processing section 6 is activated and an interrupt request to the processor section 1 is issued.

[Effect]

In the present invention, since the interrupt to the processor section is performed based on the continuity of the markby (y), the interrupt can be performed regardless of the amount of received data, and all the problems of the conventional method can be solved.

〔Example〕

FIG. 2 shows a block diagram of a communication line processing device to which the present invention can be applied, in which 10 is a communication line processing device, 11 is a central control unit (CCU), I2 is a line microprocessor (LMP), 13 is a line control unit (LC), 14 is a control memory (C8; C0NTR0L 5TORAGE), 1
5 is a line control word memory (LCW), 16 is an LCW address register, 17 is a line buffer (LB), 1.8 is a line parameter/status area (LPS), and 19 is a main memory (MM>).

The communication line processing device 10 in FIG. It operates according to input/output commands from the III control unit (CCU) u, and the flow of its operation is as follows.

■ Analyze input/output instructions by line microprocessor (LMP) 12;

■ Obtain parameter information from the main memory fl (MM) 19 to the control memory 14, and set parameters (LPS) for the line control unit according to the parameters? 1i11 is created in the memory 14 and the line control unit 13 is activated.

■ 1fR1! The I+ control section 13 controls the parameter (L
PS), the resulting status is created in the status area (LP
S) Store in 18. Thereafter, a request is made to the all-line microprocessor (LMP) 12 to process the received characters.

■ Line microprocessor (LMP) 12 id
, When the series of processing for the line is completed, status information is created in the control memory 14 and sent to the central control unit (CC).
U) Request 11 for all processing of the execution results of the input/output commands.

FIG. 3 is a block diagram of main parts of one embodiment of the present invention,
This figure shows in detail the line control unit (LC) 13, line control word memory (LCW) 15, and LCW address register 16 shown in FIG. In Figure 3, 15.1
6 is the same as that shown in FIG. 2, 20 is a line scanning section, 21 is an arithmetic processing section, 22 is a line control word memory read register, 23 is an interrupt control section, 24 is a byte counter control section, 25Vi+1 circuit , 26 are gate circuits.

Figure 4 is line control! (LCW), in which API-1 assembly field ACFO is an assembly control field with the role of a bit counter, ACFI is an assembly control field with the role of a mark hit counter, OF is a character field, CCF is a character control field, and LPS is a line parameter/status field.

The present invention will be explained in detail with reference to FIGS. 3 and 4.

While scanning the line, the first On received in receive mode
The bit is regarded as the start bit, and the arithmetic processing unit 21 writes the start bit detection into the CCFK of the LCW. The contents of AF are shifted to the right by a shift register operation, added to the bits received from the line, and stored back in LCW.

During the next scan, when the start bit detection bit of the CCF is on, a full count is performed until the bit counter ACFO becomes equal to the character length. When the bit counter ACFO becomes equal to the character length and a start bit is detected, the completed character is written to CF,
Turn off the CCF start bit detection bit.

Next, while monitoring the start bit, mark (M
ark) bit count '1AcF1 mark (Ma
rk) Perform p using a bit counter.

If a mark (Mark) pintra for the counter is received, the mark (Mark) reception is displayed on the LPS of the LCW, and the line microprocessor (
Sends all interrupt requests to LMP ) 12, and sends a cycle to LPS18 in control memory 14.
Store status information in Steal ) mode.

When the start bit is detected, it is assembled into the AP as described above, and when the character is completed, the completed CF character and the now completed character are stored in the line buffer (LB) 18 of the control memory 14 in cycle steal mode. .

When the allocated line buffer (LB) 18 becomes full, it creates the LPSK status of the LCW, sends an interrupt request to the line microprocessor (LMP) 12, and writes a cycle steal (C7cle) to the LPS 18 of the control memory 14.
5teal) mode.

As shown in FIG. 3, the content of ACFI is incremented by 1 every time a mark bit is received after receiving one character, and cleared to "0" every time a space bit is received. The LPS in the LCW determines the amount of data transferred to the allocated line buffer (LB) 18, and when the line buffer (LB) 18 is full, an operation is performed to activate the interrupt control unit 23.

Next, line buffer (LB) 17 and LPS 18
Let me explain about K. LP818 is an area in which line parameter information given from the line microprocessor (LMP) 12 to the line control unit 13 side and line status information reported from the line control unit 13 side to the line microprocessor (CMP) 12 are stored.

Depending on the value of a specific bit in the LP818, the LP818
The contents of the line become line parameter information or line status information.

When starting up the line, the line microprocessor (CMP) 12 sends the LPS 18 receive command information, line buffer (LB)
17, set the usable capacity (number of transferred bytes), etc.

Thereafter, the contents of this LP 818 are read into the LPS on the LCW side, and the receiving operation on the line control unit 13 side is started.

On the line control unit 13 side, the received data is transferred to a line buffer (L
B) Each time the data is transferred to 17, the byte counter control unit 24 decrements the byte count value set inside the LPS in υLCW. Then, when the byte count value in LPS in LCV/ becomes 0'', the contents of LPS in LCW are written to LP818 in control memory 14. At this time, the above-mentioned specific bit is set to 0''. LPS18
is set to indicate that it stores line status.

Thereafter, an interrupt request is issued to the line microprocessor (LMP) 12 via the interrupt control unit 23't. Note that when the byte count value in the LPS in LCW has not reached 0'', i.e. still line buffer (LB)
Even if there is space in 17, if mark bits are received continuously and the ACFI value reaches the predetermined value, the L
The contents of the LPS in the CW are written to the LP818 in the control memory 14, and the line microprocessor (LMP
) 12, an interrupt request is issued.

〔Effect of the invention〕

According to the present invention, it is possible to interrupt the line microprocessor even if the number of line buffers does not reach a certain number, and it is possible to solve the problems of the conventional method.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a block diagram of communication line processing equipment, Fig. 3 is a block diagram of main parts of an embodiment of the present invention, and Fig. 4 is the structure of the line control word. FIG. 3 is a diagram showing an example. In FIG. 2, 12 is a line microprocessor; 13 is a line microprocessor;
is the line control section, 14? 'i control memory, 15 is a diagram illustrating the principle of the present invention.

Claims (2)

[Claims] (1) A line control word memory (15) provided for each line and having information for controlling data transmission and reception, and a line control word memory (15) that controls data transmission and reception between the lines based on the contents of the line control word (15). section (13), and a processor section (12) that controls the line control section (13).
), the line control word memory (15) is provided with a mark bit counting area (ACF1) for counting consecutive mark bits received from the line; , after receiving one character, when a mark bit is received from the line, the above mark bit counting area (
When the value of ACF1) is counted and a space bit is received from the line, the above mark bit counting area (ACF1)
Initialize the value of mark bit counting area (ACF1).
) reaches a predetermined value, the processor section (1
2) A line processing system using an asynchronous procedure, characterized in that it is configured to issue an interrupt request. (2) The processor section (12) and the line control section (1
3), a line buffer (17) in which received data temporarily held in the line control word (15) is transferred and stored; and a control unit in which control information between the processor and the line control unit is stored. An information area (18) is provided, and the usable capacity of the line buffer (17) is notified from the processor unit (12) to the line control unit (13) via the control information area (18). From the line control unit (13) to the processor unit (12), the control information area (18
), the amount of received data transferred to the line buffer (17) is notified, and normally the amount of received data transferred to the line buffer (17) reaches the usable capacity of the line buffer (17). When this occurs, an interrupt request is issued to the processor section (12), and on the other hand, when the value of the mark bit counting field (ACF1) reaches a predetermined value, the received data is transferred to the line buffer (17). Even if the amount does not reach the usable capacity of the line buffer (17), the processor unit (17)
2) A line processing system using an asynchronous procedure according to claim 1, wherein an interrupt request is issued to the start/stop synchronous procedure.