JPS60252962A - Processor down informing system - Google Patents

Abstract

PURPOSE:To reduce the number of signal lines for supervising by informing processor down utilizing unused time of a common bus. CONSTITUTION:When a cause 213 of processor down occurred, a processor down signal forming circuit 210 outputs pulse of 1 clock width that becomes a processor down signal only when a bus busy signal 43 that indicates a common bus 4 is in use is off. The pulse signal of a processor down output 214 makes a processor down signal line 41 effective through an inverter 211, and pulse of a down processor number 215 makes an address signal line 42 selected by a change-over switch 212 effective. Other processor down detecting circuit 22 detects that the signal line 41 is made effective, and outputs a request 101 for interruption by processor down to a processor not shown in the figure, and at the same time, sets the downed processor number sent on the address signal line 42 of a down processor number display register 23 to a flip-flop 231.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processor down notification method for notifying other processors of information regarding a processor going down in a multiprocessor system.

When a processor goes down in a multiprocessor system, it requests other processors to handle the downtime, such as post-processing the task it was in charge of or releasing the shared resources it had been using. It is necessary to notify the processor number. The processor down notification method of the present invention proposes a method for notifying processor down information in such cases.

[Conventional technology]

As a method of notifying processor down information, a method as shown in FIG. 6 is conventionally known.

FIG. 6 shows an example of a system consisting of five 1G, 16.1c processor units. In each processor unit, 11 is a processor, 12 is an internal processor bus, 15 is a local memory, and 14 is a Bus coupling circuit, 15 processor status indication register, 16
is the processor down output circuit. Further, 4 represents a common bus, and 41 represents a processor down signal line.

Assuming that the processor unit 1C is now down, the processor down output circuit 16 in the processor unit 1C displays a processor down indication in the processor status display register 15, and also enables the processor down signal line 41 to notify other processor units. 1a, 1
b is notified of the occurrence of processor down.

Each processor t-+-nit that receives the processor down signal transmits an interrupt request due to the processor down to the respective processor 11. Upon receiving an interrupt request due to a processor going down, the processor 11 sequentially reads the processor status display registers 15 of other processor units in the interrupt processing to determine the number of the down processor unit. Processing to determine the number of a down processor unit is performed independently in all processor units that are not down.

If this method is used, the processor units that are not down access the processor status display register of each processor sequentially, so it takes time to determine the number of the processor unit that is down. The common bus 4 becomes temporarily very congested and the processing capacity of the system is reduced because all the processor units that are not running access the processor status and register of each processor unit to determine which processor unit is down. This problem becomes more noticeable as the number of processor units configuring the system increases.

As another example, by preparing as many processor down signal lines as the number of processor units on the common bus 4 and dedicating these lines to each processor,
There is a method of having hardware automatically determine the processor unit number that has gone down. However, when using this method, processor down signal lines that are unnecessary in normal processing operations must be prepared for the maximum number of processors that can be implemented in the system, and therefore the common bus signal lines are There is a problem that the number increases due to functions that are rarely used.

[Problem that the invention seeks to solve]

The processor down notification method of the present invention eliminates the need for the processor unit that received the notification to access the processor status display registers of other processor units via the common bus when a processor goes down, which reduces the processing capacity of the system. In addition to solving the problem, the present invention attempts to solve the problem of increasing the scale of the common bus by newly adding a dedicated processor down signal m to each processor on the common bus.

[Means for solving problems]

In the processor down notification method of the present invention, when a processor goes down in a multiprocessor system, the existing common bus signal line is temporarily used as a processor down notification line for each processor, and the processor down number and We are trying to notify you of detailed information such as the cause of the downtime.

[Effect]

In the processor down notification method of the present invention, when a processor goes down, detailed information regarding the down and notification to the processor units is performed by using the signal line of the common bus in a time-sharing manner. Detailed information such as the above information can be automatically notified to other processor units, and the processor receiving the interrupt can immediately obtain this information.

〔Example〕

FIG. 1 shows the configuration of an embodiment of the processor down notification system of the present invention. In this figure, the same parts as in FIG. 6 are indicated by the same numbers, 21 is a processor down output circuit, 22 is another processor down detection circuit, 23 is a down processor number display register, 4
This is a 1 huff 'rosessor damo processor down interrupt request.

FIG. 2 also shows the processor down output circuit 21 in the embodiment shown in FIG. Other processor down detection circuit 2
2 mainly shows the detailed configuration of the embodiment shown in FIG. In the same figure, the same parts as in FIG. 1 are indicated by the same numbers, 200 is a wired OR gate, 201 is a pull-up resistor, 210 is a processor down signal generation circuit, 211 is an inverter with an open collector output, 212 215 is a changeover switch, 215 is a processor down factor, 214 is a processor down output, 215 is a down processor number, 220 is an inverter, 221 is an AND gate, 251 is a slip flop (FF), and 43 is a bus busy signal.

FIG. 3 is a time chart showing various signals in the detailed circuit shown in FIG. 2, and each signal 4 in FIG.
1, 42, 43, 213, 214, and 215 are shown with the same numbers. Further, 44 is a bus clock.

A first embodiment of the present invention will be described below based on these figures. In this embodiment, compared to the conventional system shown in FIG. 6, the contents of the processor down output circuit 21 are changed, and the other processor down detection circuits 22. A down processor number display register 26 is added. Furthermore, in this method, the processor status display register 15 in the conventional method can be omitted.

When a processor down factor 216 occurs in the processor down output circuit 21, the processor down signal generation circuit 210 generates a processor down signal when the bus busy signal 46 indicating that the common bus 4 is in use is off (period indicated by b in FIG. 5). It outputs a pulse with a width of one clock (214° 215 in FIG. 5). The pulse of the processor down output 214 passes through the inverter 211 to enable the processor down signal line 41 and output the processor down signal line 41 to the down processor number 2.
The 15th pulse enables the address signal line 42 (which may also be a data signal line) selected by the changeover switch 212.

The address signal line 42 is used to display the processor number that is down, and the address signal line 41 is used to display information indicating the processor number that is down.
It is used as a signal line to indicate that the signal is being output to 2.

On the other hand, the other processor down detection circuit 22 detects that the processor down signal 41 has become valid, and outputs an interrupt request 101 due to processor down to the processor 11, and also outputs an interrupt request 101 due to the processor down to the processor 11. Bit 7 corresponding to the down processor number shown on the address signal line 41
Set the rib 70 and the rib 251. The flip-flop 261 constituting the down processor number display register 25 can be set individually for each bit, so that even if several processors go down at the same time, the number of the previously down processor can be displayed. I'm trying not to destroy it.

The processor 11 that receives the interrupt request 101 due to the processor down reads the down processor number display register 26 in the interrupt processing.
You can instantly know the processor number that has gone down. The down processor number display register 25 has a read reset (or an echo reset) in order to display only the newly down processor number when another processor goes down again after the above-mentioned processor down process ends. shall be.

As is clear from the above explanation, in this embodiment, by using the unused period of the bus, it is possible to extremely easily notify that the processor is down.

FIG. 4 is a time chart illustrating a second embodiment of the processor down notification method of the present invention.

The block configuration and detailed circuit configuration in the system of this embodiment are the same as those shown in FIGS. 1 and 2, respectively. In the first embodiment described above, the idle time of the bus is used to notify that the processor is down, whereas in this embodiment, the common bus is acquired to notify that the processor is down.

When a processor down factor 216 occurs in the processor down output circuit 21, the processor down signal generation circuit 210 controls acquisition of the right to use the common bus. (
The method of controlling acquisition of the right to use the common bus itself is irrelevant to the essence of the present invention, so a detailed explanation will be omitted. ) After acquiring the common bus, the processor down signal generation circuit 210 outputs the down processor number 215, and then outputs the processor down signal 214 (period shown in FIG. 4d). After that, when a certain period of time has elapsed, the output of the processor down signal line 41 is dropped and the common bus is released. Note that the operation of the other processor down detection circuit 22 in this embodiment is similar to the first one described above.
Since this is the same as in the embodiment, the explanation will be omitted.

According to this embodiment, there is an advantage that processor down information can be notified without being restricted by the specifications of the common bus.

FIG. 5 is a diagram showing the configuration of a sixth embodiment of the processor down notification system of the present invention. In this figure, the same parts as in FIG. 2 are designated by the same numbers, and 216 is 6.
- state output gate, 217 is detailed information, 232 is first-in-first-out memory (FiFo),
253 is a FiFo'l inclusion signal. Note that the block configuration and time charts of the signals of each part in the method of this embodiment are the same as those in FIGS. 1 and 4, respectively.

This embodiment is a modification of the second embodiment described above, and was devised focusing on the point that notifications of multiple processor down information do not overlap (because the notification is performed after acquiring a common bus). The differences from the second embodiment are as follows: ■ The number of the down processor is indicated by the bit position of the valid address line 42; It is indicated by a code corresponding to the number.■ The downgro/seven-pick-up display register 25 is not composed of a plurality of seven lip-flops 231 that are set independently, but is
Constructed by Fo252.

The operational differences between this embodiment and the second embodiment will be explained below.

When the processor down factor 215 occurs, the processor down output circuit 21 outputs its own processor number to the address signal line 42 after acquiring the common bus.

It outputs detailed information 217 such as the code that causes the down factor, and also enables the processor down signal line 41.

On the other hand, the other processor down detection circuit 22 detects that the processor down signal line 41 has become valid, and takes in detailed information such as the processor number and down cause outputted to the address signal line 42 to the FiFa 252. . When the information captured in the processor FiFo 252 can be read, the processor →← J+ ・i kr
F Z, -01xλ]^ A anti★shi 噌n噌 -BO 4 --1 ・Li 4← Output for 4 橢.

When the processor 11 receives an interrupt request due to a processor being down, the processor 11 reads the down processor number display register 25 in the interrupt processing.
It is possible to know the processor number stored in the FiFo 232 and detailed information on the cause of the downtime.

According to this embodiment, even if the amount of information to be notified to other processors increases, there is no effect on the hardware, and therefore, there is an advantage that more information can be notified to other processors. .

〔Effect of the invention〕

According to the processor down notification method of the present invention, when a processor goes down, the signal line of the common bus is used in a time-sharing manner to notify detailed information about the down to the processor (use of free time on the common bus or for notification). This is done by acquiring a common bus dedicated to the The receiving processor can obtain the information immediately. Additionally, when a processor goes down, the processor that receives the down notification no longer needs to collect data via the common bus.
This prevents the occurrence of a phenomenon in which the common bus becomes temporarily crowded when a downtime occurs. Furthermore, since the signal lines of the common bus are used in a time-sharing manner, there is no need to add a new signal line to the common bus for notification of down information.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the processor down notification system of the present invention, FIG. 2 is a diagram showing the detailed circuit configuration of the embodiment shown in FIG. 1, and FIG. Time chart showing various signals in the detailed circuit shown, No. 4
5 is a time chart illustrating a second embodiment of the processor down notification method of the present invention; FIG. 5 is a diagram showing the configuration of a sixth embodiment of the processor down notification method of the present invention; FIG.
The figure shows the configuration of a conventional processor down notification system. 1α, 1b, 1c...processor unit, 4
... common lotus, 11 ... processor, 12 ... internal processor bus, 16 ... local memory, 14.
...Bus coupling circuit, 15...Processor status display register, 16.21...Processor down output circuit, 2
2... Other processor down detection circuit, 23... Down processor number display register, 24... Reset signal, 41... Processor down signal line, 42...
Address signal line, 46...Bus busy signal, 44...
・Bus clock, 101... Processor down interrupt request, 200... Wired OR gate, 201...
- Pull-up resistor, 21o... Processor down signal generation circuit, 211... Inverter, 212... Changeover switch, 213... Processor down factor, 214
... Processor down output, 215 ... Down processor number, 216 ... 5-state output gate,
217...Detailed information, 220...Inverter, 22
1...AND gate, 251...Clip flop (pp), 262...First-in-first-out memory (FiFer), 2!13- FiFo write signal Fig. 2 Fig. 3 Fig. a41 1 1 l l 1 l 1 1 1st 4th
Figure 2

Claims (3)

[Claims] (1) In a system in which a plurality of processor units are connected via a common bus, when a processor goes down, the signal line of the common bus is used to time-share the down notification of the processor and the information regarding the down including the number of the processor. Each processor unit is provided with means for notifying other processors when a processor is down, and a storage means for storing information regarding the down state when receiving a down notification from another processor. A processor down notification method characterized by reading and obtaining information about a down processor. (2) The processor down notification method according to claim 1, wherein the time-sharing use of the signal lines of the common bus is based on the use of idle time of the common bus. (3) The processor down notification system according to claim 1, wherein the time-sharing use of the signal line of the common bus is based on acquisition of the common bus.