JPS60132247A - Controlling system common bus - Google Patents

Abstract

PURPOSE:To suppress a function drop caused by an access error to the minimum by making a common bus usable in case of the first access error, and inhibiting access of the common bus in case when an error is generated again in the course of holding the first error. CONSTITUTION:In an initial state, flip-flops (FF)22-24 are off. When an error is generated, an OR circuit 25 becomes on, the FF22 is set and a signal C becomes on. This signal C turns off a bus possessory right acquiring signal D of each bus master 5-1-5-2. As a result, the FF22 is reset, and a common bus becomes usable again. A CPU1 analyzes and investigates the cause of the error, turns on a signal Y when the cause is known, clears a register 21, and resets the FFs 23, 24. When a new error is generated in a state that the cause of the first access error remains unknown, and an output of an AND circuit 26 becomes ''0''. As a result, even if the signal D becomes off, the FF22 remains on, and the common bus becomes unusable.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a system in which a plurality of bus masks connecting input/output devices such as display devices and magnetic disk devices access memory using a common bus. The present invention relates to a common bus usage control method that disables the use of a common bus on the condition that memory access errors occur continuously in a data processing system.

[Prior art and problems]

When multiple bus masks connecting input/output devices such as display devices and magnetic disk devices access memory using a common bus, it is necessary to control the common bus, and a priority circuit is provided for this purpose. . The priority circuit selects one bus mask according to a predetermined priority in response to a common bus occupancy request from each bus mask, and allows that bus mask to occupy the common bus. The bus mask that has acquired the exclusive right accesses the memory using the common bus, but conventionally, the memory access management unit that manages memory access has a problem with parity errors and other errors during memory access. When an access error occurs, the Mary access management unit sends a signal to the priority circuit and each bus master disabling use of the common bus. Therefore, when an access error occurs, system functionality is forced to deteriorate significantly.

[Purpose of the invention]

The present invention is based on the above considerations, and uses a common bus that secures the usage status of the common bus as much as possible even if an access error occurs, and minimizes the functional deterioration caused by the access error. The purpose is to provide a control method.

[Structure of the invention]

To this end, the common bus usage control method of the present invention is designed to control the use of a central processing unit, a main storage device, a memory access management unit that manages access to the main storage device, and an input/output device such as a display device or a magnetic disk device. A plurality of bus masks are connected and access the main memory device through a common bus, and when a bus occupancy request requesting occupancy of the common bus is received from the plurality of bus masks, one bus A common bus use control method is provided in which the mask is provided with a priority circuit that allows the mask to occupy the common bus, and the bus mask that has received permission from the priority circuit accesses the main storage device using the common bus. Therefore, the above memory access management unit is
A holding means that holds the contents when an access error occurs in the main memory, and an unusable unit that sends a common bus unusable signal to each of the priority circuit and the plurality of bus masks when an access error occurs. and a double error detection means for detecting that a new access error has occurred before the holding means is cleared, and a common bus unusable signal is sent from the unusable notifying means. Under the condition that the common bus is released from the plurality of bus masks, the transmission of the above-mentioned unusable signal is stopped, and when the occurrence of a new error is detected by the above-mentioned double error detection means, The present invention is characterized in that the unusable signal is continued to be sent from the unusable notifying means until the holding means is cleared while holding the initial status in the holding means.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the system configuration of one embodiment of the present invention, and FIG.
The figure shows a specific example of the configuration of the memory access management unit. In the figure, l is the CPU (central processing unit), 2 is the memory access 11 units, 3 is the memory,
4 is a priority circuit, 5-1 to 5-n are bus masks, 21 is a status register, 22 to 2
4 is a flip-flop in J-, 25 is an OR circuit, 26
and 27 are AND circuits, and 28 and 29 are inversion circuits.

The bus masters 5-1 to 5-n are control units that allow input/output devices such as display devices, magnetic disk devices, and magnetic tape devices located below them to access memory through the memory access management unit 2. The priority circuit 4 is a circuit that determines the priority among the bus masters 5-1 to 5-. Status information provided in memory access management unit 2
The register 21 stores errors such as address errors, data parity errors, memory uncollectible errors (read data cannot be corrected), etc. (Xo=Xm) when accessing memory via the common bus. be. A flip-flop 22 holds an access error, and a shift flip-flop 23 detects the occurrence of a subsequent error before clearing the first error. Furthermore, the flip-flop 24 clears the status register 21 from the occurrence of an error (
Y signal). Signals A and A to A are sent from the bus masters 5-1 to 5-n to the priority circuit 4 are bus occupancy request signals, and one signal is assigned to each bus master 5-1 to 5-n. . Priority circuit 4 to each bus master 5-1 to 5
- The signals B, through Bn, sent one by one to the buses are priority input signals, and the bus occupancy request signals A, through An.
As a result of taking priority from the inputs, only one is turned on. The only bus mask that has taken it is the one that occupies the bus (turns on the bus seize signal) when no other novus mask is using the bus (when the bus seize signal is off). ) can be turned on).

The bus occupancy acquisition signal is a signal that indicates whether or not the bus is in use.By turning on this signal during transfer, the bus mask that has acquired the bus occupancy signal can communicate with other bus masks. If the bus master 5-i is prohibited from gaining bus occupancy and has lost the occupancy at the end of the transfer, that is, if the priority input signal Bi for that bus master 5-i is in the OFF trap, this signal is turned off. In particular, tell the other bus masks that you are releasing the bus. Signal E is a signal that informs the bus mask occupying the bus that another bus mask is requesting the right to use the bus. The bus mask that is occupying the bus receives the bus occupancy request signal k from itself when the signal E is on.
i must be turned off. Signal C is flip-
This is the output signal of the flop 22. Since the bubble error factor is output from Xo for one clock cycle, OR circuit 2
When the output multiplied by 5 is 111, the signal C is turned on. The operation of the flip-flops 22, 23, 24 will now be considered and explained below.

■ Before the error occurs (initial state) Flip-flops 22, 23, and 24 are all off (Q
='0').

(2) When an error occurs for the first time When an error occurs, the OR circuit 25 is not turned on, the flip-flop 22 is set, and the signal C is turned on.

That is, the signal C is transmitted to the priority circuit 4 and each bus master 5-1 to 5-n when the common bus is unavailable (
This is a notification that an access error has occurred. By turning on this signal C, each bus
The masters 5-1 to 5-1 turn off the bus exclusive right acquisition signal. As a result, since the output of the AND circuit 26 is 111 times the flip-flop 23, the shift flip-flop 22, which is turned on, is reset. The common bus is now usable again. On the other hand, when an access error occurs, the CPUI analyzes and investigates the cause.
Once the cause is known, the contents of the register 21 are cleared by turning on the signal Y according to the contents, and the flip-flops 23 and 24 are reset. However, if the cause of the first access error remains unknown, or if a new error occurs before the contents of the register 21 are cleared, the output of the AND circuit 27 becomes 111 because both clip-flops 24 are Il+. , flip flop 2
When the 0 clip flop 23 is set to 3, its output is 10' and the output of the Punt circuit 26 is I01. As a result, the output Q of flip-flop 22 remains on even though the signal is turned off. Therefore, if signal C remains on, the common bus becomes unusable. As described above, since it would be a problem if the cause of the error cannot be analyzed on the CPU, the register 21 is not set for the second and subsequent errors, and the signal C is kept on until the register 21 is cleared.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the common bus is made usable at the first access error, and the first
If an error occurs again during the first error hold, 1
Since access to the common bus is inhibited while retaining the second error, a high-performance system can be constructed without interfering with the analysis of the cause of the error by the CPU.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the system configuration of one embodiment of the present invention, and FIG.
The figure shows a specific example of the configuration of the memory access management unit. 1...CPU (Central Processing Unit), 2...Memory
Access management unit, 3... memory, 4... priority circuit, 5-1 to 5-n-... bus mask. 21...Register, 22 to 24...Flip
Frog, 25...OR circuit, 26 and 27...AND circuit, 28 and 29...inverting circuit. Patent Applicant: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani 1 (2) Ge2Iri

Claims (1)

[Claims] A central processing unit, a main storage device, a memory access management unit that manages access to the main storage device, and an input/output device such as a display device or a magnetic disk device are connected, and access to the main storage device is controlled through a common bus. a priority circuit that, upon receiving a bus occupancy request requesting occupancy of a common bus from the plurality of bus masks, permits one bus mask to occupy the common bus according to a predetermined priority order; and a common bus use control method in which a bus mask that has received permission from the priority circuit accesses the main storage device using the common bus, wherein the memory access management unit is configured to access the main storage device using the common bus. When an access error occurs, the holding means retains the contents, and the priority circuit and the plurality of buses
Each of the masks is provided with unusable notification means for sending a common bus unusable signal, and double error detection means for detecting that a new access error has occurred before the holding means is cleared, and the above-mentioned Under the condition that the common bus unusable signal is being sent from the unusable notification means, the sending of the unusable signal is stopped on the condition that the common bus is released from the plurality of bus masks, and the above double error is caused. If the detection means detects the occurrence of a new error, the apparatus is configured to continue sending out an unusable signal from the unusable notification means while holding the initial status in the holding means until the holding means is cleared. A common bus usage control method characterized by: