JPH04367964A - Multi-processor system - Google Patents

Abstract

PURPOSE:To quickly transfer fault information mutually without allowing it to pass through a system bus by constituting the system so that the fault information is transferred directly to an other processor by a fault information control circuit. CONSTITUTION:When it is decided that detected abnormality is a serious fault, a CPU 211 commands its fact to a fault information control circuit 217, and the fault information control circuit 217 outputs a fault signal to a signal line 10 through a driver 218. In this regard, a CPU 311 also executes the same processing. A fault information control circuit 317 of a CPU board 31 side always monitors the signal line 10 through a receiver 319, therefore, can detect a fault signal of a CPU board 21 side, and when the fault signal is detected, a fact that a serious fault is generated in the CPU board 21 side is informed to the CPU 311. Accordingly, the CPU 311 can recognize fault information related to the CPU board 21, and can execute quickly the countermeasure processing to the fault. In this regard, a fault information control circuit 217 of the CPU board 21 side also execute the same processing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of processing devices each including a processor are connected to a common bus and each processing device performs parallel processing.

0002

2. Description of the Related Art FIG. 3 is a block diagram showing a system in which two processing units are connected via a common bus. In the figure, 1 is a system bus which is a common bus, 2A and 3A are processing units, 20 and 30 are CPU boards equipped with a processor (CPU), 22 and 32 are memory boards equipped with memory elements, and 23 and 33 are CPU boards equipped with a processor (CPU). This is an I/O board for inputting/outputting various input/output information to/from the outside of the processing devices 2A, 3A.

FIG. 4 is a block diagram showing the configuration of the CPU boards 20 and 30. In the figure, 211 and 311 are CPU boards 211 and 311.
, 212, 312 are local memories having failure information areas 213, 313 in which failure information is stored, 214,
314 is an external input/output interface that exchanges signals with the outside of the CPU boards 20 and 30; 215 and 315 are common bus interfaces that exchange signals with the system bus 1; and 216 and 316 are data transfers inside the CPU boards 20 and 30. This is a local bus.

Next, the operation will be explained. In the system configured as shown in FIG.
11 execute independently assigned processing. In addition, each CPU 211, 311, as necessary,
The contents of the memory on each memory board 22, 32 can be read and written via the system bus 1, and each I/O board 23,
33 is subjected to predetermined processing.

[0005] In such a multiprocessor system, the CPU 211 has to control the control of other CPUs 311 in order to know the occurrence of a failure within the control range of other CPUs 311.
It is necessary to constantly monitor the operating status of 11. That is, the CPU 211 sends information to the system bus 1 via the common bus interface 215 to notify whether the own device is normal or abnormal. Further, the CPU 211 takes in notification information of other devices from the system bus 1 via the common bus interface 215 and sets it in the failure information area 213 of the local memory 212. The other CPUs 311 operate in the same manner to set notification information of other devices in the failure information area 313.

[0006] The CPU 211 sequentially stores the failure information area 2.
13 is read out, and the other processing device 3A is read from the content.
It is possible to check the failure status of the Other processing equipment 3A
If it is recognized that a failure has occurred, the CPU 211 can perform processing corresponding to the failure. Also, CPU
If an abnormality occurs in 311 itself, the CPU 21
1 is the CPU 311 when the CPU 311 is accessed.
It is possible to detect the occurrence of an abnormality by detecting that the device has become unresponsive. Note that the CPU 311 also performs the above processing in the same manner.

[0007]

[Problems to be Solved by the Invention] Since the conventional multiprocessor system is configured as described above, failure information regarding other processing units 3A is transmitted via the system bus 1, and it takes time to transmit the information. In many cases, there is a problem in that even if prompt failure handling is required when a failure occurs, it may not be possible to respond immediately.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multiprocessor system capable of mutually transmitting failure information without using a system bus.

[0009]

[Means for Solving the Problems] A multiprocessor system according to the present invention has a signal line connecting each processing device, and each processing device outputs failure information of its own device and also outputs failure information of other processing devices. a fault information control circuit that inputs fault information; an open collector output buffer that outputs the fault information output by the fault information control circuit to a signal line;
The input buffer has an input side connected to the output side of the output buffer, and inputs failure information of other processing devices and provides it to the failure information control circuit.

0010

[Operation] The failure information control circuit of the present invention not only directly transmits failure information of its own device to other processing devices without using the system bus connecting each processing device, but also directly transmits failure information of other processing devices. Obtain.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 21 and 31 are CPU boards whose configuration is shown in FIG. 2, and 2 and 3 are processing devices, respectively. Further, 10 is a signal line for transmitting a failure signal according to failure information. Other parts are the same as those shown in FIG. 3 with the same reference numerals.

FIG. 2 is a block diagram showing the configuration of the CPU boards 21 and 31. In the figure, 217 and 317 are failure information control circuits that output failure signals according to failure information and input failure information of other devices. , 218, 318 are open collector type drivers (output buffers) that output fault information to the signal line 10, and 219, 319 are receivers (input buffers) that provide the signals on the signal line 10 to the fault information control circuits 217, 317. be. Other parts are the same as those shown in FIG. 4 with the same reference numerals.

Next, the operation will be explained. In the system configured as shown in FIG.
11 execute independently assigned processing. In addition, each CPU 211, 311, as necessary,
The memory contents on each memory board 22, 32 can be read and written via the system bus 1, and each I/O board 23, 3
A predetermined process is performed on 3.

[0014] Here, when the CPU 211 detects an abnormality in an operation such as external input/output, the CPU 211 updates the local memory 212.
The details of the abnormality are stored in the failure information area 213 in the . C.P.
When U211 determines that the detected abnormality is a serious failure, it instructs failure information control circuit 217 to that effect. The failure information control circuit 217 receiving the command outputs a failure signal to the signal line 10 via the driver 218. Note that the CPU 311 also performs similar processing.

Failure information control circuit 3 on the CPU board 31 side
17 constantly monitors the signal line 10 via the receiver 319, so it is possible to detect a failure signal on the CPU board 21 side. Then, when a fault signal is detected, the CP
The CPU 31 indicates that a serious failure has occurred on the U board 21 side.
Notify 1. Therefore, the CPU 311 can immediately recognize failure information regarding the CPU board 21 and can promptly execute processing corresponding to the failure. In addition, CPU board 21
The failure information control circuit 217 on the side also performs similar processing.

If a less serious failure occurs, failure information may be transmitted via the system bus 1 as in conventional processing. Furthermore, the failure information control circuit 217,
317 constantly monitors the CPU 211, 311, it can immediately detect a serious failure of the CPU 211, 311 itself, and notify the other CPU boards 3,
2 can be transmitted.

Note that in the above embodiment, the CPU board 21
, 31 has been described, but the case where there are three or more may be possible. In that case, the drivers and receivers of all CPU boards are connected to the signal line 10, or each signal line is provided between each CPU.

[0018]

As described above, according to the present invention, the multiprocessor system is configured such that the failure information control circuit directly transmits failure information to other processing devices, so that This has the effect of being able to quickly transmit failure information.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing the configuration of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing the configuration of the CPU board shown in FIG. 1;

FIG. 3 is a configuration diagram showing the configuration of a conventional multiprocessor system.

FIG. 4 is a configuration diagram showing the configuration of the CPU board shown in FIG. 3;

[Explanation of symbols]

1 System bus 2,3 Processing equipment 10 Signal line 21, 31 CPU board 211,311 CPU 217, 317 Failure information control circuit

Claims (1)

[Claims] 1. In a multiprocessor system in which processing units including processors that execute predetermined processes while mutually monitoring other processing units are connected via a system bus, a signal line connecting each of the processing units is provided. Each of the processing devices has a fault information control circuit that outputs fault information of its own device and inputs fault information of other processing devices, and a fault information control circuit that outputs fault information of the fault information control circuit to the signal line. An open collector type output buffer that outputs an output; and an input buffer whose input side is connected to the signal line, inputs failure information of another processing device from the signal line, and supplies it to the failure information control circuit. A multiprocessor system featuring: