JPH04344552A - Multi-input/output control method - Google Patents

Multi-input/output control method

Info

Publication number
JPH04344552A
JPH04344552A JP11643491A JP11643491A JPH04344552A JP H04344552 A JPH04344552 A JP H04344552A JP 11643491 A JP11643491 A JP 11643491A JP 11643491 A JP11643491 A JP 11643491A JP H04344552 A JPH04344552 A JP H04344552A
Authority
JP
Japan
Prior art keywords
input
control
output
output device
storage means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11643491A
Other languages
Japanese (ja)
Inventor
Ikufumi Yamada
山田 郁文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP11643491A priority Critical patent/JPH04344552A/en
Publication of JPH04344552A publication Critical patent/JPH04344552A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize high speed switching of multi-input/output control. CONSTITUTION:FIFO(first-in first-out) memory 5 sequentially stores both numbers of input/output devices 11-14 whose initiation are required by a master unit and number of input/output devices to which control is switched for multicontrol. Microprocessor 4 starts an input/output device whose number is read out of the FIFO memory 5, and controls the input/output device by using control information read out of a control information area corresponding to local memory 2. When the control comes to the end, if the FIFO memory 5 is not empty, number of input/output devices under the control and the control information are stored in the FIFO memory 5 and local memory 2, the next number is read out of the FIFO memory 5 to switch the control.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、マイクロプロセッサを
含む入出力制御装置が複数の入出力装置を制御する多重
入出力制御方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple input/output control system in which an input/output control device including a microprocessor controls a plurality of input/output devices.

【0002】0002

【従来の技術】従来、この種の多重入出力制御方式は、
入出力制御装置のプロセッサのレジスタの退避と各入出
力装置の制御情報の格納とのために格納手段を有し、こ
の格納手段を各入出力装置の制御情報域に分割し、各々
の入出力装置に番号をつけ、分割した各制御情報域中に
次の制御を示す入出力装置の番号を格納し、現在制御し
ている入出力装置の番号は起動されている入出力装置の
一番最後の入出力装置の制御情報域に格納する事により
多重の入出力制御の切り換えを行っていた。
[Prior Art] Conventionally, this type of multiple input/output control method
It has a storage means for saving the register of the processor of the input/output control device and storing the control information of each input/output device, and this storage means is divided into the control information area of each input/output device, and each input/output Number the devices, and store the number of the input/output device indicating the next control in each divided control information area, and the number of the input/output device currently being controlled is the last one of the activated input/output devices. Multiple input/output control was switched by storing the information in the control information area of the input/output device.

【0003】0003

【発明が解決しようとする課題】上述した従来の多重入
出力制御方式は、各入出力装置の制御切り換え時に多重
度が増せば増す程、最後に制御する入出力装置の番号を
検出して現在実行している入出力装置の番号を格納する
のに時間がかかるという欠点がある。
[Problems to be Solved by the Invention] In the conventional multiple input/output control method described above, as the degree of multiplicity increases when switching control of each input/output device, the number of the input/output device to be controlled last is detected and the number of the current input/output device is detected. The disadvantage is that it takes time to store the number of the input/output device being executed.

【0004】0004

【課題を解決するための手段】本発明の多重入出力制御
方式は、それぞれ番号付けられた複数の入出力装置と、
上位装置が起動要求した前記入出力装置の番号及び多重
制御のために次の前記入出力装置に制御が切り換えられ
る前記入出力装置の番号を先入れ先出しで格納する第1
の記憶手段と、前記入出力装置のそれぞれごとに制御情
報を格納できる第2の記憶手段と、前記複数の入出力装
置と外部バスを介して接続され前記第1及び第2の記憶
手段と内部バスを介して接続され前記第1の記憶手段か
ら読み出した番号の前記入出力装置を起動し前記第2の
記憶手段から読み出した前記制御情報を用いて制御し制
御の切れ目で前記第1の記憶手段が空でなければ制御し
ていた前記入出力装置の番号及び制御情報を前記第1及
び第2の記憶手段に格納した後前記第1の記憶手段を読
み出して制御の切り換えを行なうマイクロプロセッサと
を備えている。
[Means for Solving the Problems] The multiple input/output control method of the present invention includes a plurality of input/output devices each having a number,
A first storage device that stores, in a first-in, first-out manner, the number of the input/output device for which the host device has requested activation and the number of the input/output device whose control is to be switched to the next input/output device for multiplex control.
a second storage means capable of storing control information for each of the input/output devices; and a second storage means connected to the plurality of input/output devices via an external bus, and an internal The input/output device connected via a bus and having the number read from the first storage means is activated and controlled using the control information read from the second storage means. If the means is empty, a microprocessor stores the number and control information of the input/output device being controlled in the first and second storage means and then reads out the first storage means to switch control; It is equipped with

【0005】又、本発明の多重入出力制御方式は、前記
第1の記憶手段が空であるか否かを前記マイクロプロセ
ッサに伝達する信号線を前記内部バスとは独立に設けた
構成であってもよい。
Further, the multiple input/output control system of the present invention has a configuration in which a signal line for transmitting to the microprocessor whether or not the first storage means is empty is provided independently of the internal bus. You can.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明する
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【0007】図1は本発明の一実施例のブロック図であ
る。
FIG. 1 is a block diagram of one embodiment of the present invention.

【0008】入出力制御装置1は、外部バス6に接続さ
れている入出力装置11,12,13,14を上位装置
である中央処理装置の起動要求によって制御する。入出
力制御装置1は、マイクロプロセッサ4と、入出力装置
11,12,13,14の制御情報域21,22,23
,24を有するローカルメモリ2と、中央処理装置の入
出力装置11,12,13,14に対する起動要求時に
おける事象、及び、入出力装置11,12,13,14
の多重制御の切り換え時における事象を発生した順番に
格納し発生した順番に読み出す事が出来るFIFOメモ
リ5と、上述した事象が無くてFIFOメモリ5が空の
時は“1”、空でない時は“0”をマイクロプロセッサ
4に伝達する信号伝達線7と、ローカルメモリ2とFI
FOメモリ5とマイクロプロセッサ4とを接続する内部
バス3とにより構成されている。
[0008] The input/output control device 1 controls the input/output devices 11, 12, 13, and 14 connected to the external bus 6 in response to an activation request from a central processing unit, which is a host device. The input/output control device 1 includes a microprocessor 4 and control information areas 21, 22, 23 of the input/output devices 11, 12, 13, 14.
, 24, an event at the time of a startup request to the input/output devices 11, 12, 13, 14 of the central processing unit, and the input/output devices 11, 12, 13, 14.
There is a FIFO memory 5 that can store events in the order in which they occur and read them out in the order in which they occur when multiplex control is switched, and the FIFO memory 5 is set to "1" when the above-mentioned event does not occur and the FIFO memory 5 is empty, and when it is not empty. A signal transmission line 7 that transmits “0” to the microprocessor 4, a local memory 2, and an FI
It is composed of an FO memory 5 and an internal bus 3 that connects the microprocessor 4.

【0009】次に、入出力制御装置1が行う多重制御動
作について説明する。
Next, the multiplex control operation performed by the input/output control device 1 will be explained.

【0010】入出力装置11,12,13,14に制御
番号をそれぞれ“01”,“02”,“03”,“04
”と付ける。中央処理装置から外部バス6を介して入出
力装置11に起動要求を受け付けると、マイクロプロセ
ッサ4はFIFOメモリ5に入出力装置11の制御番号
“01”を格納する。続けて中央処理装置から入出力装
置12に起動要求を受け付けたならば、入出力装置11
に対して起動をかけに行くより先に起動要求を受け付け
、前述の処理と同様にマイクロプロセッサ4がFIFO
メモリ5に入出力装置12の制御番号“02”を格納す
る。同様にして、中央処理装置が続けて他の入出力装置
に起動要求をしたならば、FIFOメモリ5にその入出
力装置の制御番号を格納してゆく。
Control numbers are assigned to the input/output devices 11, 12, 13, and 14, respectively, as "01", "02", "03", and "04".
”. When receiving a startup request from the central processing unit to the input/output device 11 via the external bus 6, the microprocessor 4 stores the control number “01” of the input/output device 11 in the FIFO memory 5. When the input/output device 12 receives a startup request from the processing device, the input/output device 11
The microprocessor 4 accepts the startup request before going to start up the FIFO.
The control number "02" of the input/output device 12 is stored in the memory 5. Similarly, if the central processing unit subsequently issues a startup request to another input/output device, the control number of that input/output device is stored in the FIFO memory 5.

【0011】次に中央処理装置から起動要求が来なけれ
ば、FIFOメモリ5を読み出す。最初に起動要求を受
け付けた制御番号“01”がまず読み出され、入出力装
置11の起動処理を開始して、処理の切れ目になったら
制御を切り換える。制御を切り換える為には、先ず、F
IFOメモリ5が空であるか否かを信号伝達線7の状態
によって判断し、空である事を示す“1”の時は制御を
切り換えずにそのまま続行し、空でない事を示す“0”
の時はFIFOメモリ5に制御番号“01”を格納し、
ローカルメモリ2の入出力装置11の制御情報域21に
制御に必要な情報を格納し、FIFOメモリ5を読み出
す。読み出した制御番号が“02”であれば、ローカル
メモリ2中の入出力装置12の制御情報域22から制御
に必要な情報を読み出して入出力装置12の制御を開始
する。上述の動作をくり返すことで多重入出力制御を実
現する。
Next, if no activation request is received from the central processing unit, the FIFO memory 5 is read. The control number "01" for which the startup request was first received is first read out, and the startup process of the input/output device 11 is started, and when the processing ends, the control is switched. To switch the control, first
It is determined whether the IFO memory 5 is empty or not based on the state of the signal transmission line 7, and when it is "1" indicating that it is empty, the control continues without changing the control, and "0" indicating that it is not empty.
In this case, store the control number “01” in the FIFO memory 5,
Information necessary for control is stored in the control information area 21 of the input/output device 11 of the local memory 2, and the FIFO memory 5 is read out. If the read control number is "02", information necessary for control is read from the control information area 22 of the input/output device 12 in the local memory 2 and control of the input/output device 12 is started. Multiple input/output control is realized by repeating the above operations.

【0012】0012

【発明の効果】以上説明したように本発明は、起動要求
された入出力装置や制御が他の入出力装置に切り換えら
れる入出力装置の番号を先入れ先出しの第1の記憶手段
に格納するようにしたので、多重の入出力制御の切り換
えがより高速に出来る効果がある。特に、多重度が多い
時により大きい効果が得られる。
As explained above, the present invention stores the number of the input/output device for which activation is requested or the input/output device whose control is to be switched to another input/output device in the first storage means on a first-in, first-out basis. Therefore, there is an effect that switching of multiple input/output control can be performed faster. In particular, greater effects can be obtained when the degree of multiplicity is high.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1    入出力制御装置 2    ローカルメモリ 3    内部バス 4    マイクロプロセッサ 5    FIFOメモリ 6    外部バス 7    信号伝達線 11〜14    入出力装置 1 Input/output control device 2. Local memory 3 Internal bus 4. Microprocessor 5 FIFO memory 6 External bus 7 Signal transmission line 11-14 Input/output device

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  それぞれ番号付けられた複数の入出力
装置と、上位装置が起動要求した前記入出力装置の番号
及び多重制御のために次の前記入出力装置に制御が切り
換えられる前記入出力装置の番号を先入れ先出しで格納
する第1の記憶手段と、前記入出力装置のそれぞれごと
に制御情報を格納できる第2の記憶手段と、前記複数の
入出力装置と外部バスを介して接続され前記第1及び第
2の記憶手段と内部バスを介して接続され前記第1の記
憶手段から読み出した番号の前記入出力装置を起動し前
記第2の記憶手段から読み出した前記制御情報を用いて
制御し制御の切れ目で前記第1の記憶手段が空でなけれ
ば制御していた前記入出力装置の番号及び制御情報を前
記第1及び第2の記憶手段に格納した後前記第1の記憶
手段を読み出して制御の切り換えを行なうマイクロプロ
セッサとを備えたことを特徴とする多重入出力制御方式
Claim 1: A plurality of input/output devices each numbered, the number of the input/output device requested to be activated by a host device, and the input/output device whose control is switched to the next input/output device for multiple control. a first storage means for storing control information for each of the input/output devices on a first-in, first-out basis; a second storage means for storing control information for each of the input/output devices; The input/output device connected to the first and second storage means via an internal bus and having the number read from the first storage means is activated and controlled using the control information read from the second storage means. If the first storage means is not empty at a break in control, the number and control information of the input/output device being controlled are stored in the first and second storage means, and then the first storage means is read out. A multiple input/output control method characterized by comprising a microprocessor that switches control.
【請求項2】  前記第1の記憶手段が空であるか否か
を前記マイクロプロセッサに伝達する信号線を前記内部
バスとは独立に設けたことを特徴とする請求項1記載の
多重入出力制御方式。
2. The multiple input/output device according to claim 1, wherein a signal line for transmitting to the microprocessor whether or not the first storage means is empty is provided independently of the internal bus. control method.
JP11643491A 1991-05-22 1991-05-22 Multi-input/output control method Pending JPH04344552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11643491A JPH04344552A (en) 1991-05-22 1991-05-22 Multi-input/output control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11643491A JPH04344552A (en) 1991-05-22 1991-05-22 Multi-input/output control method

Publications (1)

Publication Number Publication Date
JPH04344552A true JPH04344552A (en) 1992-12-01

Family

ID=14687012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11643491A Pending JPH04344552A (en) 1991-05-22 1991-05-22 Multi-input/output control method

Country Status (1)

Country Link
JP (1) JPH04344552A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005339426A (en) * 2004-05-31 2005-12-08 Fujitsu Ltd Data processing system and setting method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005339426A (en) * 2004-05-31 2005-12-08 Fujitsu Ltd Data processing system and setting method

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