JPH0836482A - Memory device - Google Patents

Abstract

PURPOSE:To carry out the exchange of the input/output order as a data group, to eliminate data loss and to improve the degree of the control freedom by providing a means preserving input/output addresses for existing data on an internal address control part and adding a function performing a new input/ output address control for the data inputted from this means. CONSTITUTION:The input/output address selector parts 9 and 10 of an internal address control part 4 have the functions which are capable of preserving plural input/output addresses and selecting the input/output addresses by external request signals and preserve the value of the input/output address counter to be being used at present by external request instructions. The internal address control part 4 sets and controls the storage area which is already inputted and preserved from this input/output address counter value as a use inhibition area. Next, the internal address control part 4 sets the new address within a use possible area to the input/output address counter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, particularly a FIFO.
Concerning the control of.

[0002]

2. Description of the Related Art In a FIFO in which data can be read in the order in which data is written, newly input data is written first even though there is already stored data (data written but not read). When it is desired to output to, the stored data must be discarded (reset) and then written and read, and the stored data must be destroyed by this reset. Therefore, in order to output the subsequent data first without destroying the stored data, it was necessary to use another method in which another FIFO was provided and the data was sent to the subsequent stage via another route.

[0003]

As described above, in a FIFO in which data can be read in the order in which data is written, it is possible to output later data first without damaging the data already stored. In order to achieve this, it is necessary to have a plurality of FIFOs, which causes a problem that the circuit becomes large. The purpose of the present invention is to
FI with smaller circuit size compared to conventional technology and more practical
To supply FO.

[0004]

Conventionally, a FIFO is a RAM
It has an input address counter and an output address counter, and can be configured by internally controlling input / output addresses (counting up, address comparison, etc.). For the purpose of the present invention to output the subsequent data first without damaging the already stored data, the internal address control unit is provided with means for storing the input / output address for the existing data, and the already input data is already input. The specified storage area is set as a prohibited area, and a new input / output address control function is added to the data to be input.

[0005]

According to the external request instruction, the value of the input / output address counter currently in use is first saved. Then, the internal address control unit sets, from the input / output address counter value, the storage area that has already been input and saved as the use prohibited area,
to manage. Next, the internal address control unit sets a new address in the usable area in the input / output address counter. By these settings, it becomes possible for the data input / output thereafter to output the subsequent data first without destroying the existing data.

As another alternative for satisfying this function, when a switching request is input, the data stored in the FIFO is temporarily read.
Use the FIFO after evacuating it to AM or the like and emptying the FIFO. A method of re-inputting the data temporarily saved after use from the FIFO input side can be considered. This method is
It is good if the amount of data that has already been saved is small, but if it is large, it will take time to transfer.

[0007]

The details of the present invention will be described below with reference to the illustrated embodiments.

As shown in FIG. 1, a normal FIFO 5 comprises an input data buffer 1, an output data buffer 2 for input / output data, a RAM (or a dual port memory etc.) 3 for holding data, and an internal address control section 4. . FIG. 2 shows a configuration example of the internal address control unit 4. The internal address control unit 4 uses the shift IN (input request signal),
It is composed of an output address counter control unit 6, an input address counter control unit 7, an address comparison control unit 8 and the like for controlling internal addresses by using shift OUT (output request signal), reset, and external output status as input / output signals. The address comparison controller 8 outputs the external output status by comparing the input address with the output address.
In addition to this, in the actual circuit of the internal address control unit 4, Ful
Controls input and output disabling (address count-up prohibited) in the l and Empty states. As an example of the present invention, FIG.
An internal block diagram of the internal address controller is shown in FIG. This has an output address select section 9 and an input address select section 10 in addition to the conventional one shown in FIG. The input / output address select units 9 and 10 have a function of storing a plurality of input / output addresses and a function of selecting the input / output address area by an external request signal. The following two methods can be considered as the method of the external request. 1)
Uses an interrupt as an external request. In other words, the interrupt input holds the previous input / output address, determines the prohibited address area from this, and newly controls the subsequent input / output address to save the data before the interrupt and input the data after the interrupt. It becomes possible to output.
Then, after the data processing after the interruption is completed, a termination interrupt or the like is received from the outside, and the old address is reset in the output address counter control unit 6 and the input address counter control unit 7,
Restart control of old data. 2) It has a plurality of input / output control signals as external request signals. As a result, a region is selected, and a plurality of addresses can be held and controlled by the input / output address select units 9 and 10, and a plurality of FIs can be simulated.
It can be treated like having a FO. As an address control method for controlling the plurality of data groups, an address area is secured in the order of input, and the address area is made variable. In some cases, the address area is decided by. The latter method of predetermining the area also includes (a) address area equal division method and (b) address area weight division method, as shown in FIG. 4, but these are selected as necessary.

FIG. 5 shows an example of a system to which this method is applied. Performs operation 1 on the input data and outputs the result to FIFO
1 is input, and the output of this FIFO 1 is used as an input for calculation 2
And the result is input to the FIFO2. Similarly this F
Calculation 3 is performed with the output of IFO2 as input, and the result is F
It is input to IFO3. Here, the address area "1" is first selected as an external request. As a result, the input / output address select control units 9 and 10 set the current input / output address in the address area “1” in the input / output address register. Calculate the input data,
The calculation result is input to the address area “1” of FIFO1 to 3. If it is desired to obtain the operation result of another input data before the data stored in the FIFOs 1 to 3 as an interrupt process, the address area “2” is set as an external request.
Select As a result, the input / output address select unit 9,
10 stores the current input / output address from the input / output address register. Next, the input / output address select units 9 and 1
0 sets the current input / output address in the address area “2” in the input / output address register. After this, if the calculation is started with the input data, it is possible to output the later processed data using the address area “2” while keeping the existing data in the FIFOs 1 to 3.

After that, even if the data in the address area "2" of the FIFO remains, the address area "1" or the address area "3" can be selected by an external request. The output order can be freely controlled.

[0011]

The present invention has the following effects. (1) Since it is not necessary to have a plurality of FIFOs in parallel, the amount of hardware can be reduced, and the hardware occupying area and cost can be reduced. (2) Since the data that has already been input is not destroyed, the output results (manufactured products, etc.) are not wasted or recreated due to the continuity of this data. (3) Since the input / output order for each data group can be freely controlled, wasteful time such as waiting time can be reduced by separately controlling external request for input and output.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration example of a FIFO.

FIG. 2 is a diagram showing a configuration example of an internal address control unit.

FIG. 3 is a diagram showing a configuration example of a FIFO according to the present invention.

FIG. 4 is an example of FIFO address division (a) equal division method,
(b) A diagram showing a weight division method.

FIG. 5 is a diagram illustrating a system application example.

[Explanation of symbols]

1 ... Input data buffer, 2 ... Output data buffer, 3
RAM (or dual port memory), 4 internal address control unit, 5 FIFO, 6 output address counter control unit, 7 input address counter control unit, 8 address comparison control unit, 9 output address select unit, 10
... Input address select section.

Claims (1)

[Claims] 1. A storage element capable of reading data in the order in which data is written by controlling an internal address of a large-capacity storage medium (eg, RAM) (hereinafter referred to as FIFO (First
InFirst Out). ), It has a means to control the internal address from the outside, and it is possible to read earlier from the data to be written next without damaging the already saved data (data written but not read). Memory device characterized by.