JPH04361348A - Data transfer method - Google Patents

Abstract

PURPOSE:To efficiently use a prefetch data buffer corresponding to the transfer ability of an input/output device. CONSTITUTION:A channel controller 300 is equipped with a prefetch data buffer 302 shared among plural channels and each time data are transferred from a central processing unit 100, the transfer ability of input/output devices 500-504 is received. A prefetch data buffer control circuit 303 manages the condition of using the prefetch data buffer 302, and the use areas of the prefetch data buffer in channel devices 400-404 are secured corresponding to the transfer performance of the input/output devices received according to an input/output instruction 1. A data transfer control circuit 304 performs memory access corresponding to the secured use area of the prefetch data buffer 302 and controls data transfer between a main storage device 200 and the input/output devices 500-504.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a data transfer method.
The present invention relates to a data transfer method having a channel control device that allows data to be sent and received between a main storage device connected to a central processing unit and an input/output device connected to a channel device.

0002

2. Description of the Related Art In conventional data transfer methods, when a channel control device transfers data from a connected central processing unit and main memory to an input/output device via a channel device, a channel control device is connected under one channel device. Since a prefetch data buffer with a fixed size is provided inside the channel device according to the transfer performance of the input/output device to be connected, different channel devices are configured depending on the transfer performance of the input/output device connected under the channel device.

0003

[Problems to be Solved by the Invention] Since the channel control device in the conventional data transfer method described above is equipped with a prefetch data buffer of a fixed size inside one channel device, the input/output There is a problem in that each time the transfer performance of a device improves, a high-performance channel device must be provided. In addition, when I/O devices with different transfer performance are connected under a channel device, a prefetch data buffer is provided, which is necessary for transfer from a high-performance I/O device, so that it can be connected to an I/O device with low transfer performance. There was a problem in which the pre-fetch data buffer used was wasted. In addition, in recent years, input/output devices have become faster and faster, and it is now inevitable to combine input/output devices with high transfer performance and input/output devices with low transfer performance, so there is a problem that the waste of prefetch data buffers increases.

0004

[Means for Solving the Problems] A data transfer method of the present invention includes controlling a plurality of channel devices connected to a main storage device and a central processing unit, and controlling an input/output device connected to the main storage device and the channel device. a shared prefetch data buffer that temporarily stores data to be transferred to the plurality of channel devices;
a first means for receiving and storing the transfer performance of the input/output device connected subordinately from the central processing unit at the time of initial setting; and a transfer performance of the input/output device for managing and storing the usage status of the prefetch data buffer. a second means for securing a used area of the pre-fetch data buffer according to the data buffer; and a second means for securing a used area of the pre-fetch data buffer according to the secured data buffer, and performing a memory access according to the secured used area of the pre-fetch data buffer to transfer data between the main storage device and the input/output device. and third means for performing transfer control.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a channel device 40 is provided under a channel control device 300.
The case where four numbers 0 to 404 are connected is shown.

In FIG. 1, a central processing unit 100 is a device that performs arithmetic processing, and issues an input/output instruction 1 to a channel control device 300 when performing data input/output processing. Transfer performance information 17 of all input/output devices connected under the channel control device 300 is given at the time of initial setting of the channel control device 300.

[0008] The main storage device 200 is a central processing unit 100
A storage device that is connected to the channel control device 300 and reads or writes data from the input/output devices 500 to 501 required by the central processing unit 100 via the channel devices 400 to 404, and is connected to the channel control device 300. For each memory request 3 issued from 300, a 1-word memory reply 4 is sent.

The channel control device 300 controls the channel device 40 according to the input/output command 1 issued by the central processing unit 100.
0 to 401 to control the main storage device 200 and the input/output device 5.
This is a device that transfers data between 00 and 501.

Channel devices 400, 401,...403 control interfaces with input/output devices 500, 501,...503, and transfer transfer output data 7 received from channel control device 300 to input/output devices 500-504. It is a device.

The channel control circuit 301 is a circuit that decodes and processes the input/output command 1 received from the central processing unit 100.
The transfer performance of the input/output devices 500 to 504 specified by is read from the input/output device transfer performance table 308, a prefetch data buffer area is secured according to the transfer performance of the input/output devices 500 to 504, and the data transfer control circuit 304 and This is a circuit that gives data transfer instructions to channel devices 400-404.

The prefetch data buffer 302 is a buffer that stores transfer data read from the main storage device 200 prior to data transfer, and is a buffer that writes and reads data to and from addresses specified by the prefetch data buffer control circuit 303. It is.

The prefetch data buffer control circuit 303 is
According to the usable area of the prefetch data buffer 302 allocated to the input/output devices 501 to 505 to be transferred with reference to the prefetch data buffer management flag group 305,
This circuit generates the write address 16 and the read address 15, limits the number of memory accesses to the data transfer control circuit 304, and controls the amount of data in the prefetch data buffer 302, and is used by the input/output devices 500 to 50.
When the usage area of the prefetch data buffer 302 allocated to 4 becomes full, a request suppression signal 13 is output,
Further, the channel device numbers of the memory requests are stored in the order in which the memory requests are made, and each time the data input register 306 receives the memory reply 4, the write address 16 of the prefetch data buffer 302 is outputted.
When outputting memory reply data to the channel devices 400 to 404, the read address 15 of the prefetch data buffer 302 and the channel device number 11 to be transferred are sent.

The data transfer control device 304 controls the main storage device 20 according to the data transfer instruction 8 of the channel control circuit 301.
This is a circuit that accesses 0, and receives the request suppression signal 13 for each channel from the prefetch data buffer control circuit 303.
The data buffer control circuit 3 continues to send the memory request 3 for each channel device 400 to 404 until the memory request 3 is output, and every time the memory request 3 is sent, the request sending signal 14 for each channel device 400 to 404 is preempted.
Send to 03.

The flag group 305 assigns one flag to each unit area of the prefetch data buffer 302, and is composed of a channel device number and a bit in use. When the channel devices 400 to 404 connected to the channel devices 400 to 404 are being used for data transfer,
4 and the in-use bit is set to "1", and when the flag is not in use, the in-use bit is set to "0", and is set/reset based on the usage status of the prefetched data buffer 302 by the channel control circuit 301. is displayed all the time.

Data input register 306 is a register for receiving memory reply 4 from main storage device 200 and writing it to prefetch data buffer 302 . The data output register 307 transfers the data read from the prefetch data buffer 302 to the prefetch data buffer control circuit 3.
This is a register for sending data to the channel devices 400 to 404 specified by the channel device number 11 output from 03. The input/output device transfer performance table 308 stores the transfer performance of all the input/output devices 500 to 504 connected to the channel control device 300 given by the central processing unit 100 at the time of initial setting of the channel control device 300. It's memory.

Next, the operation of this embodiment will be explained.
The central processing unit 100 issues an input/output command 1 to the channel control device 300, and in the channel control device 300, the channel control circuit 301 decodes the input/output command 301, and transfers data to the input/output devices 500 to 504. , and determines whether I/O instruction 1 can be executed based on the usage status of the prefetch data buffer 302 by referring to the prefetch data buffer management flag group 305. Prefetch data buffer 302
If the available area is insufficient, the central processing unit 100 is notified that execution is impossible because the prefetch buffer is busy (BUSY).

The central processing unit 100 has a prefetch buffer B.
When USY, another input/output control device path is selected and input/output command 1 is issued. If input/output instruction 1 can be executed, set the channel device number and in-use bit "1" in the flag group 305 for prefetch data buffer management, and set the prefetch data buffer 302 and usage area necessary for executing input/output instruction 1. ensure that Then, the channel devices 400 to 404 to which the input/output devices 500 to 504 specified by the input/output command 1 are connected are notified of the start of data transfer via the signal line 9. Channel devices 400 to 40 that received the notification
4 is in a state of waiting for input/output data. Further, the channel control circuit 301 provides transfer control information 8 to the data transfer control circuit 304 to start memory access. The data transfer control circuit 304 that has received the transfer control information 8 starts sending the memory request 3 and sends a request sending signal 14 to the prefetch data buffer control circuit 303 every time one memory request is made, and performs prefetch data buffer control. The memory request 3 continues to be sent until the request suppression signal 13 is output from the circuit 303.

The prefetch data buffer control circuit 303
Referring to the prefetch data buffer management flag group 305, when the memory requests of the input/output devices 500 to 504 that are being transferred become full of the used area of the prefetch data buffer 302 allocated to the input/output devices 500 to 504 that are being transferred, A request suppression signal 13 is output to the data transfer control circuit 304. In addition, a plurality of channel devices 400 to 4
04 are performing transfer operations at the same time, each channel device 400 to 404 is transferred according to the usage area of the prefetch data buffer 302 allocated to each channel device 400 to 404.
Send memory request 3 from 0 to 404.

When memory reply 4 arrives, data input register 306 stores memory reply data 5 in prefetch data buffer 302 at the address designated by prefetch data buffer control circuit 303 . The prefetch data buffer 302 outputs memory reply data 5 at the address specified by the prefetch data buffer control circuit 303 to the data output register 307 as data 6. When data output register 307 receives data 6, it outputs data to channel device 400 designated by prefetch data buffer control circuit 303.
- 404, and when the sending is completed, a data sending signal 12 is sent to the prefetch data buffer control circuit 303 to notify completion of data output.

The prefetch data buffer control circuit 303 is
When the data sending signal 12 comes from the data output register 307, the request inhibit signal 13 is stopped and the data transfer control circuit 304 is allowed to send the memory request 3. The above operations are repeated until the transfer amount specified by the input/output instruction 1 is completed, and when the data transfer is completed, the channel control circuit 301 outputs the completion report 2 of the input/output instruction 1 to the central processing unit 100. Then, the operation of channel control device 300 ends.

FIG. 2 shows the prefetch data buffer 302 of FIG.
This is a diagram showing the relationship between the prefetch data buffer management flag group 305, and one prefetch data buffer management flag is associated with each unit area of the prefetch data buffer 302. Consists of the channel device numbers of the channel devices 400 to 404 that are using the unit area of the buffer 302 and an in-use bit indicating whether or not the unit area is in use; when the in-use bit is “0”, the corresponding preemption is performed. data buffer 3
02 indicates that the unit area is unused. The channel control circuit 301 selects the prefetch data buffer 302 based on the number of words of prefetch data necessary for executing the input/output instruction 1.
The necessary number of unit areas is calculated, and the channel device numbers and in-use bits of the channel devices 400 to 401 to be used are set prior to the data transfer operation. As soon as the data transfer operation is completed, the in-use bit is reset.

[0023]

As explained above, the present invention shares the prefetch data buffer of a plurality of channel devices to which input/output devices with different transfer capabilities are connected, and performs transfer operations according to the transfer capabilities of the input/output devices. By making the usage amount of the prefetch data buffer variable, the prefetch data buffer can be used efficiently. Furthermore, since input/output devices with high transfer performance and input/output devices with low transfer performance can be freely connected, there is an effect that the prefetch data buffer is not wasted.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of this embodiment.

[Explanation of symbols]

100 Central processing unit 200 Main storage device 300 Channel control device 301 Channel control circuit 302 Prefetch data buffer 303 Prefetch data buffer control circuit 304
Data transfer control circuit 305 Display flag 306 Data input register 307 Data output register

Claims (1)

[Claims] 1. A channel control device connected to a main storage device and a central processing unit, controlling a plurality of channel devices, and transferring data between the main storage device and an input/output device connected to the channel device. , a shared prefetch data buffer for temporarily storing data to be transferred to the plurality of channel devices, and a first means for receiving and storing transfer performance of the input/output device connected thereunder from the central processing unit at the time of initial setting. , a second means for securing a usage area of the prefetch data buffer according to the transfer performance of the input/output device that manages and stores the usage status of the prefetch data buffer; and third means for controlling data transfer between the main storage device and the input/output device by performing memory access accordingly.