JPH0486043A - Redundant switching system for atm switch - Google Patents

Redundant switching system for atm switch

Info

Publication number
JPH0486043A
JPH0486043A JP2199658A JP19965890A JPH0486043A JP H0486043 A JPH0486043 A JP H0486043A JP 2199658 A JP2199658 A JP 2199658A JP 19965890 A JP19965890 A JP 19965890A JP H0486043 A JPH0486043 A JP H0486043A
Authority
JP
Japan
Prior art keywords
switch
cell
cells
switching
switching information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2199658A
Other languages
Japanese (ja)
Other versions
JP2671576B2 (en
Inventor
Ryuichi Ikematsu
龍一 池松
Akihiro Miyamoto
宮本 晃宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19965890A priority Critical patent/JP2671576B2/en
Publication of JPH0486043A publication Critical patent/JPH0486043A/en
Application granted granted Critical
Publication of JP2671576B2 publication Critical patent/JP2671576B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To execute the redundant changeover of an synchronous transfer mode (ATM) switch without instantaneous interruption and without abandonning cells by using the idle cell or synchronizing cell of an input data for instructing timing for the write redundant switch of switch information. CONSTITUTION:The switch information received from a high-order control part 2 is written in the idle cell received at a switch information inserting part 1. A supervisory and control part 3 supervises the appearance of the cell for switch control writing the switch information and controls a branching circuit 4 so as to execute switching from an active system switch 5 to an auxiliary system switch 6. The cell for switch control is finally resident at a buffer 51 in the active system switch 5, and the cell following just after is resident at a buffer 61 of the auxiliary system switch 6. When the cell for switch control is received while selecting an output signal S7 from the active system switch 5, the selection is switched to the selection of an output signal S8 from the auxiliary system switch 6. Thus, without abandonning cells resident in the buffer 51 of the active system switch 5 when receiving switch information from the high-order control part 2, the switch can be changed over without any instantaneous interruption.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はATMスイッチの冗長切替方式に関し、特にセ
ルの競合を避けるため出力部にバッファを設けたATM
スイッチの冗長切替方式に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a redundant switching system for ATM switches, and in particular to ATM switches equipped with a buffer at the output section to avoid cell contention.
Regarding the redundant switching method of switches.

〔従来の技術〕[Conventional technology]

従来のこの種のATM (非同期転送モード)スイッチ
の冗長切替方式では、第4図に示すように分岐回路14
及び選択回路18が上位制御部12からの切替情報を直
接受信して同時に分岐回路14及び選択回路18を現用
系スイッチ15及び予備系スイッチ16の一方から他方
へ切替えている。
In the conventional redundant switching system of this type of ATM (asynchronous transfer mode) switch, the branch circuit 14 is
The selection circuit 18 directly receives switching information from the upper control unit 12 and simultaneously switches the branch circuit 14 and the selection circuit 18 from one of the active system switch 15 and the standby system switch 16 to the other.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のATMスイッチの冗長切替方式では、例
えば現用系スイッチ15から予備系スイッチ16への切
替が行われるときに、現用系スイッチ15内のバッファ
に残っていたデータが廃棄されてしまうため、瞬断が発
生するという問題点がある。
In the conventional ATM switch redundancy switching method described above, for example, when switching from the active switch 15 to the backup switch 16, the data remaining in the buffer in the active switch 15 is discarded. There is a problem in that instantaneous interruptions occur.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の冗長切替方式は、それぞれセルデータを一時記
憶するためのバッファを持つ非同期転送モード(ATM
)用の現用系スイッチ及び予備系スイッチと、入力デー
タ中のセルに切替情報を書き込む切替情報挿入部と、該
切替情報の書き込まれたセルを監視して前記現用系スイ
ッチ及び前記予備系スイッチへ転送するセルの振り分け
を行う分岐回路と、該分岐回路のセル振り分けを制御す
る第1の監視制御部と、前記現用系スイッチ及び前記予
備系スイッチから読み出されるセルの選択を行う選択回
路と、該選択回路の選択を制御する第2の監視制御部と
を備えている。
The redundancy switching method of the present invention is based on asynchronous transfer mode (ATM), which has a buffer for temporarily storing cell data.
) for the active system switch and the backup system switch, a switching information insertion unit that writes switching information into cells in input data, and monitors the cells in which the switching information is written and sends them to the active system switch and the backup system switch. a branch circuit that distributes cells to be transferred; a first supervisory control section that controls cell distribution in the branch circuit; a selection circuit that selects cells to be read from the active switch and the backup switch; and a second monitoring control section that controls selection of the selection circuit.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例を示すブロック図てらう
。この実施例と第4図の従来方式との相違点は、分岐回
路4の前段にアイドルセルへ切替情報を書き込むための
切替情報挿入部1を設けたことと、該切替情報の書き込
まれた切替制御用セルを監視しながら分岐回路4及び選
択回路8をそれぞれ制御する監視制御部3及び7を設け
たことである。第4図の従来方式では、上位制御部12
から送信する切替情報が分岐回路14と選択回路18と
直接制御してスイッチが切替を行なうので、切替情報受
信時に現用系スイッチ5(あるいは予備系スイッチ]6
)内のバッファ内に溜っているセルが廃棄されてしまう
FIG. 1 is a block diagram showing a first embodiment of the present invention. The difference between this embodiment and the conventional method shown in FIG. The supervisory control units 3 and 7 are provided to control the branch circuit 4 and the selection circuit 8, respectively, while monitoring the control cells. In the conventional system shown in FIG.
Since the switching information transmitted from the switch directly controls the branch circuit 14 and the selection circuit 18, the switch performs switching, so when the switching information is received, the active system switch 5 (or standby system switch) 6
) will be discarded.

本実施例では、切替情報挿入部1で受信したアイドルセ
ルに、上位制御部2から受信する切替情報を書き込む。
In this embodiment, the switching information received from the upper control unit 2 is written into the idle cell received by the switching information insertion unit 1.

監視制御部3では、該切替情報が書き込まれている切替
制御用セルの出現を監視し、切替制御用セルを受信する
と分岐回路4を制御して現用系スイッチ5から予備系ス
イッチ6への切替を行う。これにより、切替制御用セル
は現用系スイッチ5内のバッファ51の最後に溜り、切
替制御用セルの直後に続くセルは予備系スイッチ6のバ
ッファ61に溜る。監視制御部7では、現用系スイッチ
5からの出力信号S7を選択中に切替制御用セルを受信
すると、予備系スイッチ6からの出力信号S8の選択に
切替える。これにより、上位制御部2からの切替情報受
信時に現用系スイッチ5のバッファ51に内に溜ってい
るセルを廃棄せずに、無瞬断でスイッチ切替えを行うこ
とができる。
The supervisory control unit 3 monitors the appearance of a switching control cell in which the switching information is written, and when a switching control cell is received, controls the branch circuit 4 to switch from the active switch 5 to the standby switch 6. I do. As a result, the switching control cells are accumulated at the end of the buffer 51 in the active switch 5, and the cells immediately following the switching control cells are accumulated in the buffer 61 of the standby switch 6. When the supervisory control unit 7 receives the switching control cell while selecting the output signal S7 from the active switch 5, it switches to select the output signal S8 from the standby switch 6. Thereby, when switching information is received from the upper control unit 2, the cells stored in the buffer 51 of the active switch 5 are not discarded, and switch switching can be performed without momentary interruption.

第2図は本発明の第2の実施例のブロック図である6本
実施例は、第1の実施例(第1図参照)にデータ消去部
9.11を付加した構成を有する。冗長切替えを行なう
場合には、予備系スイッチ6内のバッファ61はデータ
消去部11により何も書き込まれていない状態にされ、
上位制御部2から切替情報挿入部1に切替情報S2が送
信される。切替情報挿入部1は、データS1の空きセル
(アイドルセル)に切替情報S2を書き込む。
FIG. 2 is a block diagram of a second embodiment of the present invention. This embodiment has a configuration in which a data erasing section 9.11 is added to the first embodiment (see FIG. 1). When performing redundancy switching, the buffer 61 in the standby switch 6 is made into a state where nothing is written by the data erasing section 11,
Switching information S2 is transmitted from the upper control unit 2 to the switching information inserting unit 1. The switching information insertion unit 1 writes switching information S2 into a vacant cell (idle cell) of data S1.

分岐回路4に入力されるデータS3の空きセルを監視し
ている監視制御部3は、切替情報を持つ空きセルを検出
すると、その空きセルを現用系スイッチ5に送出した後
、データS5と同じデータS6を予備系スイッチ6にも
送出するよう分岐回路4に指示を出し、分岐口Ft@4
は現用系スイッチ5と予備系スイッチ6に同じデータS
5、S6を送出し、同じように書き込んでいく。ここで
バッファ51及びその予備系であるバッファ61に着目
すると、バッファ51内には切替情報を持つ空きセルよ
り順序が前のセル、切替情報を持つ空きセル及び切替情
報を持つ空きセルより順序が後のセルがデータとして書
き込まれている。またバッノア61内には切替情報を持
つ空きセルより順序が後のセルがデータとして書き込ま
れている。監視制御部7は、バッファ51に書き込まれ
ているデータを順に読み出していく選択回路8を監視し
ており、選択回路8が切替情報を持つ空きセルを読み出
したことを検出すると、選択回路に対して現用系スイッ
チ5から予備系スイッチ6へ切替えるように指示を出す
。選択回路8の切替え完了後、分岐回路4はデータS5
の送出を停止する。
When the supervisory control unit 3, which monitors empty cells of the data S3 input to the branch circuit 4, detects an empty cell with switching information, it sends the empty cell to the active switch 5, and then outputs the same data as the data S5. The branch circuit 4 is instructed to send the data S6 to the standby switch 6, and the branch port Ft@4
is the same data S for the active switch 5 and the standby switch 6.
5. Send S6 and write in the same way. Here, if we focus on the buffer 51 and its backup buffer 61, we can see that there are cells in the buffer 51 that are earlier in order than empty cells that have switching information, empty cells that have switching information, and cells that are earlier than empty cells that have switching information. The subsequent cells are written as data. In addition, cells that are later in order than empty cells having switching information are written as data in the banner 61. The supervisory control unit 7 monitors the selection circuit 8 that sequentially reads data written in the buffer 51, and when it detects that the selection circuit 8 has read out an empty cell having switching information, it sends a message to the selection circuit. and issues an instruction to switch from the active switch 5 to the standby switch 6. After the switching of the selection circuit 8 is completed, the branch circuit 4 selects the data S5.
stop sending.

選択回路8は予備系スイッチ6へ切替えを行った後、バ
ッファ61に書き込まれているデータを順に読み出して
いき、データStOとして出力する。
After switching to the backup system switch 6, the selection circuit 8 sequentially reads out the data written in the buffer 61 and outputs it as data StO.

データ消去部9は、予備系スイッチ6から現用系スイッ
チ5への切り戻しに備え、現用系スイッチ5のバッファ
51内に残っているデータを消去する。予備系スイッチ
6から現用系スイッチ5への切り戻しは、上述の動作を
逆にしたものである。
The data erasing unit 9 erases data remaining in the buffer 51 of the active switch 5 in preparation for switching back from the backup switch 6 to the active switch 5. Switching back from the standby switch 6 to the active switch 5 is the reverse of the above operation.

以上の手順を行うと、有効なデータを運んでいるセルは
1つも廃棄されないので、無瞬断で冗長切替えを行うこ
とができる。
If the above procedure is performed, no cells carrying valid data will be discarded, so redundancy switching can be performed without momentary interruption.

第3図は本発明の第3の実施例を示すブロック図である
。この実施例では一定周期で装置内制御用セルを発生す
る周期セル発生部10を設けて、入力データS1に時分
割セルを多重化し、この周期セルに切替情報を書き込ん
で、第1あるいは第2の実施例の場合と同様に現用系ス
イッチ5及び予備系スイッチ6の相互切替えを行なわせ
、無瞬断で冗長切替えができる。
FIG. 3 is a block diagram showing a third embodiment of the present invention. In this embodiment, a periodic cell generating section 10 is provided which generates internal control cells at a constant period, multiplexes time division cells with input data S1, writes switching information to this periodic cell, and writes the switching information to the first or second cell. As in the case of the embodiment described above, the active system switch 5 and the standby system switch 6 are mutually switched, and redundant switching can be performed without momentary interruption.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、入力データのアイドルセ
ルあるいは同期セルに切替情報の書き込んだ冗長切替え
のタイミング指示用とすることにより、セルを廃棄せず
に、無瞬断でATMスイッチの冗長切替えを行なえると
いう効果を有する。
As explained above, the present invention enables ATM switch redundancy switching without a momentary interruption without discarding cells by writing switching information into idle cells or synchronous cells of input data for redundancy switching timing instructions. It has the effect of being able to do the following.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本発明の実施例を示すブロック図
、第4図は従来のATMスイッチの冗長切替方式を示す
ブロック図である。 1・・・切替情報挿入部、2,12・・・上位制御部、
3.7・・監視制御部、4,14・・分岐回路、5゜1
5・・・現用系スイッチ、51・・・バッファ、6゜1
6・・・予備系スイッチ、61・・・バッファ、7・・
・切替制御用セル監視及び選択回路制御部、8,18・
・・選択回路、9.11・・・データ消去部、10・・
・同期セル発生部。
1 to 3 are block diagrams showing embodiments of the present invention, and FIG. 4 is a block diagram showing a conventional ATM switch redundancy switching system. 1... Switching information insertion section, 2, 12... Upper control section,
3.7...Monitoring control unit, 4,14...Branch circuit, 5゜1
5... Active system switch, 51... Buffer, 6゜1
6... Backup system switch, 61... Buffer, 7...
・Cell monitoring and selection circuit control unit for switching control, 8, 18・
...Selection circuit, 9.11...Data erasing section, 10...
- Synchronous cell generation section.

Claims (1)

【特許請求の範囲】 1、それぞれセルデータを一時記憶するためのバッファ
を持つ非同期転送モード(ATM)用の現用系スイッチ
及び予備系スイッチと、入力データ中のセルに切替情報
を書き込む切替情報挿入部と、該切替情報の書き込まれ
たセルを監視して前記現用系スイッチ及び前記予備系ス
イッチへ転送するセルの振り分けを行う分岐回路と、該
分岐回路のセル振り分けを制御する第1の監視制御部と
、前記現用系スイッチ及び前記予備系スイッチから読み
出されるセルの選択を行う選択回路と、該選択回路の選
択を制御する第2の監視制御部とを備えていることを特
徴とするATMスイッチ冗長切替方式。 2、前記切替情報を書き込む前記セルは、前記入力デー
タ中の空きセルである請求項(1)記載のATMスイッ
チの冗長切替方式。 3、前記切替情報を書き込む前記セルは、前記入力デー
タ中に一定周期で発生させた同期セルである請求項(1
)記載のATMスイッチの冗長切替方式。 4、前記切替情報に応する制御に先立って前記現用系ス
イッチ及び予備系スイッチの前記バッファ内のデータを
消去するデータ消去部を有する請求項(1)記載のAT
Mスイッチの冗長切替方式。
[Claims] 1. An active switch and a standby switch for asynchronous transfer mode (ATM) each having a buffer for temporarily storing cell data, and switching information insertion for writing switching information into cells in input data. a branch circuit that monitors the cells in which the switching information is written and distributes the cells to be transferred to the active switch and the backup switch; and a first monitoring control that controls the cell distribution of the branch circuit. an ATM switch comprising: a selection circuit that selects cells to be read from the active switch and the standby switch; and a second supervisory control unit that controls selection of the selection circuit. Redundant switching method. 2. The redundant switching system for an ATM switch according to claim 1, wherein the cell into which the switching information is written is an empty cell in the input data. 3. Claim (1) wherein the cell in which the switching information is written is a synchronous cell generated at a constant period in the input data.
) Redundant switching method for ATM switches described in ). 4. The AT according to claim (1), further comprising a data erasing section that erases data in the buffers of the active switch and the backup switch prior to control according to the switching information.
Redundant switching method of M switch.
JP19965890A 1990-07-27 1990-07-27 ATM switch redundant switching method Expired - Lifetime JP2671576B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19965890A JP2671576B2 (en) 1990-07-27 1990-07-27 ATM switch redundant switching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19965890A JP2671576B2 (en) 1990-07-27 1990-07-27 ATM switch redundant switching method

Publications (2)

Publication Number Publication Date
JPH0486043A true JPH0486043A (en) 1992-03-18
JP2671576B2 JP2671576B2 (en) 1997-10-29

Family

ID=16411490

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2671576B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0723032A (en) * 1993-07-05 1995-01-24 Nec Corp Duplex line system switching method
JPH07321816A (en) * 1994-05-24 1995-12-08 Nec Corp System switching control method for atm switch
JPH0998187A (en) * 1995-09-29 1997-04-08 Nec Corp Phase matching control circuit for output buffer type switch
US5671213A (en) * 1994-11-04 1997-09-23 Nec Corporation Duplicated arrangement for ATM switching system
US5896381A (en) * 1996-02-16 1999-04-20 Nec Corporation Instantaneous switching unit and switching method for delay/priority control buffer
US6181675B1 (en) 1997-07-08 2001-01-30 Nec Corporation Uninterrupted switching between active and backup systems in ATM communication apparatus
US6490282B1 (en) 1998-03-12 2002-12-03 Nec Corporation Switching system for asynchronous transfer mode switch
US10292455B2 (en) 2012-07-17 2019-05-21 Shima Seiki Mfg., Ltd. Shoe upper and method for producing shoe upper

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02228146A (en) * 1989-03-01 1990-09-11 Fujitsu Ltd Self-routing exchange system
JPH02246646A (en) * 1989-03-20 1990-10-02 Fujitsu Ltd Self-routing exchange system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02228146A (en) * 1989-03-01 1990-09-11 Fujitsu Ltd Self-routing exchange system
JPH02246646A (en) * 1989-03-20 1990-10-02 Fujitsu Ltd Self-routing exchange system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0723032A (en) * 1993-07-05 1995-01-24 Nec Corp Duplex line system switching method
JPH07321816A (en) * 1994-05-24 1995-12-08 Nec Corp System switching control method for atm switch
US5671213A (en) * 1994-11-04 1997-09-23 Nec Corporation Duplicated arrangement for ATM switching system
JPH0998187A (en) * 1995-09-29 1997-04-08 Nec Corp Phase matching control circuit for output buffer type switch
US5896381A (en) * 1996-02-16 1999-04-20 Nec Corporation Instantaneous switching unit and switching method for delay/priority control buffer
US6181675B1 (en) 1997-07-08 2001-01-30 Nec Corporation Uninterrupted switching between active and backup systems in ATM communication apparatus
US6490282B1 (en) 1998-03-12 2002-12-03 Nec Corporation Switching system for asynchronous transfer mode switch
US10292455B2 (en) 2012-07-17 2019-05-21 Shima Seiki Mfg., Ltd. Shoe upper and method for producing shoe upper

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