JPH0998187A - Phase matching control circuit for output buffer type switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To switch an active system and a reserve system with any arbitrary timing without depending on the number of pieces of residual data. SOLUTION: In response to detection information from a detection part 21, a control part 22 of an active system 2 transfers the count value of an up/down counter 24 to a down counter 25. When that count value becomes '0', the control part 22 reports read permission 101 to a control part 32 of a reserve system 3. In response to detection information from a detection part 31, the control part 32 of the reserve system 3 initializes the contents of an up/down counter 34, down counter 35 and output buffer switch 33. The control part 32 write data inputted after the detection at the detection part 31 into the output buffer switch 23 but does not read data from the output buffer switch 33 and in response to the input of the read permission 101 from the control part 22, the read of data from the output buffer switch 33 is started.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase alignment control circuit for an output buffer type switch, and more particularly to a data phase alignment control method for a current system and a standby system of an output buffer type switch.

[0002]

2. Description of the Related Art Conventionally, in a data phase matching control method between an active system and a standby system of an output buffer type switch, an object is to perform non-instantaneous switching between the active system and the standby system of the output buffer type switch. It is used.

As shown in FIG. 2, the above-mentioned output buffer type switch is composed of an inserting section 5, a working system 6, a standby system 7, and an opposite receiving section 8.

The active system 6 and the standby system 7 are respectively provided with a detector 61,
71, control units 62 and 72, output buffer switches (SW) (n × n) 63 and 73, and up / down (U /
D) Counters (hereinafter referred to as counters) 64 and 74.

Further, the counter receiving section 8 is provided with detecting sections 81 and 82.
And a switching control section 83 and a selection circuit (SEL) 84.

In the active system 6 and the standby system 7, normally, the counters 64 and 74 are incremented when data is written to the output buffer switches 63 and 73, and the counters 64 and 74 are read when data is read from the output buffer switches 63 and 73.
By decrementing 74, the values of the counters 64 and 74 indicate the number of residual data of the output buffer switches 63 and 73.

Since the storage of data in the output buffer switches 63 and 73 of each of the active system 6 and the standby system 7 differs depending on the rising timing, the output buffer switch 6
There will be a difference in the degree of data accumulation in 3, 73.

When the phases of the data read from the output buffer switches 63 and 73 are adjusted, first, the input line 20 is selected.
The switching request information is inserted by the inserting unit 5 into the data input from 0. The insertion of the switching request information into the input data is detected by the detection units 61 and 71 of the active system 6 and the standby system 7, respectively, and notified to the control units 62 and 72, respectively.

When the control unit 62 of the active system 6 receives the detection information from the detection unit 61, the writing of the input data to the output buffer switch 63 is stopped and the output buffer switch 6
Only reading from 3 is continuously performed. At this time, the counter 64 is in a decrement only state.

When the control unit 72 of the standby system 7 receives the detection information from the detection unit 71, the control unit 72 outputs the data after the detection information is received from the detection unit 71 so that the data can be immediately read from the output buffer switch 73. At the same time as the detection information is received, the contents of the counter 74 are cleared and the reading of data from the output buffer switch 73 is stopped.

After that, the control unit 72 writes the data input immediately after the detection information is received, into the first read address of the output buffer switch 73. At this time, the counter 74 is in a state of only incrementing.

When the value of the counter 64 of the active system 6 becomes "0" after the above-described control is performed in the active system 6 and the standby system 7, that is, when there is no residual data in the output buffer switch 63, the control unit 62 notifies the control unit 72 of the standby system 7 of the read permission 201, and outputs to the output data data indicating that the own system switches from the active system to the standby system. After that, the current system is switched to the standby system in the own system.

Upon receiving the read permission 201 from the control unit 62 of the active system 6, the control unit 72 of the standby system 7 outputs to the output data data indicating that the own system is switched from the standby system to the active system. After that, the control unit 72 starts reading data from the output buffer switch 73 and decrementing the counter 74, and switching from the standby system to the active system is performed in the own system.

In the phase matching control described above, the control units 62, 7
The data output from each of the two are monitored by the detection circuits 81 and 82 of the opposite reception unit 8, and the detection circuit 81 corresponding to the active system 6 is detected.
Detects the data indicating that its own system is switched from the active system to the standby system, the detection circuit 82 corresponding to the standby system 7 again.
When detecting data indicating that the own system has switched from the standby system to the active system, each outputs detection information to the switching control unit 83.

When the switching control unit 83 receives the detection information from the detection circuits 81 and 82, it instructs the selection circuit 84 to switch to the system that has detected the data indicating that the own system has switched from the standby system to the active system. Thus, the selection circuit 84 realizes non-instantaneous switching of output data to the output line 202.

[0016]

In the above-described conventional phase adjustment control method for the output buffer type switch, since the switching is performed after the switching control information is received, the switching processing time increases in proportion to the number of remaining data in the active system. Will end up. That is, since switching between the active system and the standby system is performed by using the phase alignment of the active system and the standby system as a trigger, the switching processing time is greatly affected by the size of the residual data in the active system.

Further, when the active system and the standby system are switched, the standby system is switched to the active system after all the residual data in the buffer of the active system is output, that is, after the buffer of the active system is emptied, the switching control is performed. The number of residual data in the buffers of the current working system and the backup system will be different.

Therefore, an object of the present invention is to solve the above-mentioned problems and to perform phase adjustment of an output buffer type switch capable of switching between the active system and the standby system at an arbitrary timing without depending on the number of residual data. It is to provide a control circuit.

[0019]

A phase adjustment control circuit for a first output buffer type switch according to the present invention includes data storage means in each of an active system and a standby system, and the active system is provided in response to an external phase alignment request. A phase adjustment control circuit for an output buffer type switch for performing phase adjustment of data reading from the data storage means of a system and a standby system, which holds the residual data amount of the data storage means at the time of inputting the phase adjustment request and Monitoring means for monitoring a change in the residual data amount due to data read from the data storage means; and when the monitoring means detects that the residual data amount has been exhausted, the monitoring means monitors the other system from the data storage means. Notifying means for notifying permission of data reading and the phase adjustment when the monitoring means of another system monitors the change in the residual data amount. Means for initializing the data storage means and the monitoring means of its own system in response to an input of a request, and the above-mentioned device of its own system until another system notifies the data read permission at the time of initialization of the data storage means. A means for inhibiting data reading from the data storage means is provided in each of the active system and the standby system.

The second output buffer type switch phase adjustment control circuit according to the present invention has, in addition to the above-mentioned configuration, means for monitoring permission of the data read from another system in each of the active system and the standby system. It has.

The phase matching control circuit for the third output buffer type switch according to the present invention has, in addition to the above configuration, data to be written in the data storing means of another system in response to the input of the phase matching request. Each of the active system and the standby system is provided with means for controlling the same data to be written in the data storage means of its own system.

A fourth phase adjusting control circuit for an output buffer type switch according to the present invention comprises a storage means for storing data and a counting means for counting the amount of data stored in the storage means in each of the active system and the standby system. A phase adjustment control circuit of an output buffer type switch for performing phase adjustment of data reading from the storage means of the active system and the standby system in response to a phase alignment request from the outside, when the phase alignment request is input. Monitoring means for holding the residual data amount of the storage means and monitoring a change in the residual data amount due to data reading from the storage means; and when the monitoring means detects that the residual data amount is exhausted. The notifying means for notifying the other system of permission to read the data from the storage means and the monitoring means of the other system notify the change of the residual data amount. Means for initializing the storage means, the counting means, and the monitoring means of its own system in response to the input of the phase matching request when observing, and for reading the data from another system when the storage means is initialized. Each of the working system and the standby system is provided with means for suppressing data reading from the data storage means of its own system and counting operation by the counting means until permission is notified.

In addition to the above-mentioned configuration, the fifth phase adjustment control circuit for the output buffer type switch according to the present invention has means for monitoring permission of the data read from another system in each of the active system and the standby system. It has.

The phase adjustment control circuit for the sixth output buffer type switch according to the present invention has, in addition to the above configuration, data to be written in the data storage means of another system in response to the input of the phase adjustment request. Each of the active system and the standby system is provided with means for controlling the same data to be written in the data storage means of its own system.

[0025]

First, the operation of the present invention will be described below.

In the present invention, in each of the data storage units consisting of the active system and the standby system, a phase matching request is made at an arbitrary time point before the switching, and when the phase matching request is received, the data storing unit in the active system. Holds the data storage amount and monitors whether the data storage amount becomes “0”.

In the meantime, after the phase alignment request is accepted in the active system and the standby system, the same data is written in the data storage units of the active system and the standby system respectively, and the data is read from the data storage unit. When "0" is detected by monitoring the amount of data stored in the data storage unit in the active system, the read permission is output to the standby system that has been prevented from reading data from the data storage unit until then, and the active system is used. The reading from the data storage unit of each of the system and the standby system is made the same.

As a result, the subsequent switching can be performed at any timing without interruption, so that the switching between the active system and the standby system can be performed at any timing without depending on the number of residual data. it can.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, an output buffer type switch according to an embodiment of the present invention comprises an insertion unit 1, a working system 2, a standby system 3, and an opposite reception unit 4.

The active system 2 and the standby system 3 are respectively provided with a detector 21,
31, control units 22 and 32, and output buffer switch 2
3, 33 and up / down (U / D) counter (hereinafter,
Counters 24 and 34 and down (D) counters 25 and 35.

When the phases of the data read from the output buffer switches 23 and 33 are adjusted, first, the input line 10 is selected.
The switch unit 1 inserts the switching request information into the data input from 0. The insertion of the switching request information into the input data is detected by the detection units 21 and 31 of the active system 2 and the standby system 3, respectively, and is notified to the control units 22 and 32, respectively.

Upon receiving the detection information from the detection unit 21, the control unit 22 of the active system 2 transfers the count value of the counter 24 indicating the number of residual data of the output buffer switch 23 to the down counter 25.

When the control unit 22 transfers the count value of the counter 24 to the down counter 25, it decrements the counter 24 and the down counter 25 for reading data from the output buffer switch 23, and the output buffer switch 23 for the input data. For writing to, the counter 24 is incremented.

The count value of the down counter 25 is "0".
In this case, since it means that the data stored in the output buffer switch 23 before the detection of the phase matching request information has run out, the control unit 22 notifies the control unit 32 of the standby system 3 of the read permission 101.

On the other hand, the control unit 32 of the standby system 3 has the detection unit 31.
When the detection information is received from the counter, the values of the counter 34 and the down counter 35 are reset and the residual data number is set to "0".
And the contents of the output buffer switch 33 are cleared.

The control unit 32 increments the counter 24 for writing the input data into the output buffer switch 23 after the detection of the phase matching request information. However,
The control unit 32 controls so as not to read data from the output buffer switch 23.

After that, the controller 32 controls the controller 2 of the active system 2.
The input of the read permission 101 from 2 is monitored, and the control unit 22
When the read permission 101 is detected, the reading of data from the output buffer switch 33 and the decrement of the counter 34 are started.

By the control described above, the output data phase of the standby system can be matched with the output data phase of the active system 2. Therefore, in the opposite receiving section 4, the selection circuit (SEL) 41 can be switched at any timing. Yes, output line 1
The system switching can be realized without instantaneously interrupting the output data to 02.

As described above, the down counter 25 holds the residual data amount of the output buffer switch 23 of the active system 2 at the time of inputting the phase matching request to monitor the change in the residual data amount, and during this period, the active system 2 and the standby system. The same data is written in the output buffer switches 23 and 33 of the system 3, and when the residual data amount becomes "0", the read permission is output from the control unit 22 of the active system 2 to the control unit 32 of the standby system 3. Then, by starting the reading of data from the output buffer switch 33 of the standby system 3, the active system 2 and the standby system 3 are responded to according to the arbitrarily input phase matching request information.
Since the same output data can be output, the active system and the standby system can be switched at any timing without depending on the number of residual data.

[0040]

As described above, according to the present invention, the residual data amount of the data storage means is held at the time of inputting the phase matching request, and the change of the residual data amount due to the data read from the data storage means is monitored. , When it is detected that the residual data amount is exhausted, it notifies the other system of permission to read the data from the data storage means, and when the change of the residual data amount is monitored in the other system, the input of the phase adjustment request In response to the above, the data storage means of the own system is initialized, and the data read from the data storage means of the own system is suppressed until the data read permission from the other system is notified from this initialization. There is an effect that the active system and the standby system can be switched at any timing without depending on

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Insertion Unit 2 Working System 3 Standby System 4 Opposed Reception Unit 21, 31 Detection Unit 22, 32 Control Unit 23, 33 Output Buffer Switch 24, 34 Up / Down Counter 25, 35 Down Counter 41 Selection Circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiro Kawada 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa NEC Telecom Systems Co., Ltd.

Claims (6)

[Claims] 1. An output buffer type including a data storage means in each of the active system and the standby system, and performing phase alignment of data reading from the data storage means of the active system and the standby system in response to an external phase alignment request. A phase matching control circuit for the switch, the monitoring means holding the residual data amount of the data storing means at the time of inputting the phase matching request and monitoring a change in the residual data amount due to data reading from the data storing means; A notification unit for notifying another system of permission to read data from the data storage unit when the monitoring unit detects that the residual data amount is exhausted; A means for initializing the data storage means and the monitoring means of its own system in response to the input of the phase matching request when monitoring the change in the amount; Each of the active system and the standby system has means for suppressing data read from the data storage means of its own system until initialization of the data storage means until the other system notifies the data read permission. A characteristic phase matching control circuit. 2. The phase matching control circuit according to claim 1, wherein each of the active system and the standby system includes means for monitoring permission of the data read from another system. 3. A means for controlling to write the same data as the data written in the data storage means of another system to the data storage means of the own system in response to the input of the phase matching request. 3. The phase matching control circuit according to claim 1, wherein the phase matching control circuit is included in each of the backup systems. 4. A storage means for storing data and a counting means for counting the amount of data stored in the storage means are included in each of the active system and the standby system, and the active system is responsive to a phase matching request from the outside. And a phase adjustment control circuit of an output buffer type switch for performing a phase adjustment of data reading from the storage means of the standby system, which holds the residual data amount of the storage means at the time of inputting the phase adjustment request, and the storage means. Monitoring means for monitoring the change of the residual data amount due to the data read from the storage device, and permitting the other system to read the data from the storage device when the monitoring device detects that the residual data amount is exhausted. The notification means for notifying and the storage means of its own system in response to the input of the phase matching request when the monitoring means of the other system monitors the change of the residual data amount. And means for initializing the counting means and the monitoring means respectively, and data reading from the data storing means of the own system and the data reading means until the data reading permission is notified from another system at the time of initializing the storing means. A phase matching control circuit having means for suppressing the counting operation by the counting means in each of the active system and the standby system. 5. The phase matching control circuit according to claim 3, wherein each of the active system and the standby system includes means for monitoring permission of the data read from another system. 6. A means for controlling to write the same data as the data written in the data storage means of another system to the data storage means of the own system in response to the input of the phase matching request. 6. The phase matching control circuit according to claim 4, wherein the phase matching control circuit is included in each of the backup systems.