JPH05252189A - Atm communication equipment with cell array synchronizing function - Google Patents

Abstract

PURPOSE:To provide a technique for matching cell arrays between an in-use system transmission line and a stand-by system transmission line on the transmitter side and receiver side of an ATM communication equipment. CONSTITUTION:This equipment is equipped with the in-use system 104 and stand-by system 107 of an interface part for transmission line transmission for converting the format from the cell format in the ATM communication device to a transmission line, the precedent-stage equipment of the in-use system 104 and stand-by system 107 are provided with an excessive cell output means that outputs excessive cells which are present in the ATM communication equipment, but not sent out to the transmission line 102 at a constant rate and a cell identification information output means which outputs information for distinguishing the excessive cells from other cells, and two interface parts 104 and 107 for transmission line transmission are provided with a detecting means 108 for detecting whether or not a cell is an excessive cell and a deleting means which deletes the excessive cell and allow the quantity of transmission line sent-out cells to be matched with the maximum quantity of data which can be sent out by constant-rate excessive cell deletion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell transfer method in a digital communication device using an ATM (Asynchronous Transfer Mode) method, in which a cell array on a reception signal from a duplex transmission line is transmitted in an active system. This is a method to match the transmission line with the protection transmission line. This cell array synchronization is
It can be applied to transmission line non-instantaneous switching based on data bit comparison and collation.

[0002]

2. Description of the Related Art As one of the methods of making the active standby switching of a transmission line non-interruptive in an ATM communication device, there is a transmission line non-interruptive switching method in the 1991 IEICE Autumn Meeting B-483 "ATM network. Study: Ota, Tatsuno, Ueda ”, etc. The above-mentioned prior art shows a method of detecting and correcting the delay time difference by comparing and collating the received signal of the working transmission line and the received signal of the protection transmission line.
In this method, in order to protect against the data error of the transmission line and the contents of the cells to be compared and collated, it is necessary that the order and intervals of the cells to be compared and collated are always the same in the active system and the standby system. In order to perform cell array synchronization as typified by this example, it is necessary to have a means for removing the influence of a surplus cell that is deleted or added during transmission / reception of a transmission line.

The surplus cells are as follows. For the in-device signal of the ATM communication device, the cell throughput is set higher than that on the transmission line, and the surplus throughput is used as a wander absorbing function or a supervisory control information transfer function. The wander absorption function is a function of absorbing fluctuations in the propagation velocity due to daily and yearly differences such as temperature fluctuations occurring on the transmission line. As an example of the surplus throughput, the intra-device clock frequency is the same as the transmission line clock, the cell length on the transmission line is 53 bytes, and the intra-device cell length is 54 bytes for adding routing information. It is assumed that the signal format in which the data bytes dedicated to the physical layer processing are removed are used. Transmission line cell throughput [cell / sec] and in-device cell throughput [cell / sec]
The ratio with is (26/27) · (54/53) = 52/53. In this case, this (26/27) is the ratio of the maximum bit rate assigned to the ATM layer and the bit rate of the physical layer. Therefore, in this example, 1/5 of the internal signal
3 is a surplus cell based on the cell throughput difference. In order to send and receive a transmission line, it is necessary to convert the signal format between the transmission line and the inside of the device. This is called "cell length conversion" here.
Call it a function. This is a FIF with a capacity of several cells.
It has an O (First In First Out) memory, and realizes a signal format conversion function by stopping writing and reading as necessary to the FIFO memory. Since this function is a physical layer information terminating function and a clock transfer function, it is installed in the transmission line interface section, and when the transmission line is duplicated, this function is also included in the duplicated section.

As a conventional technique relating to this cell length conversion processing, there is one shown in FIG. Figure 5 shows SDH (Synchronous
It is a device configuration example of a Digital Hierarchy) based ATM method, and shows an example of sending cells to an STM-1 transmission line.

The cell length conversion processing operation shown in FIG. 5 will be described. In FIG. 5, the transmission line transmission side cell length conversion unit 513 deletes the surplus cell by stopping the FIFO writing. The in-device signal 502 from the cell output unit 501 is signal-converted by the transmission line transmission interface unit 503 and transmitted to the STM-1 transmission line 504. The signal conversion processing in the cell length conversion unit 513 installed in the transmission path interface unit 503 is performed as follows. The in-device signal 502 is written in the FIFO memory 505, and the comparison function 508 of the write address 506 and the read address 507 is installed. If necessary, empty cells are erased by stopping FIFO writing so that these two addresses maintain an appropriate phase relationship. For this reason, the control means 50 which detects an empty cell and suspends the writing.
9 and write address counter 5 when needed
Pause 06. When this operation cannot be performed because there is no empty cell, an output temporary stop instruction 510 is sent to the signal output unit 501 to forcibly create an empty cell. As a result, in the steady state, empty cells are deleted at a ratio of 1/53. When this FIFO operation is expressed as an address transition, it becomes as shown in FIG. FIG. 6 is an explanatory diagram of the address transition and address approach detection method of the cell length conversion FIFO in the conventional technique shown in FIG. In FIG. 6, when the read side operation is uncertain, the write side operation is also uncertain. With reference to the SOH timing in the read address 601, a timing advanced by more than a predetermined phase (approach detection threshold) 602 from this is defined as a write address approach detection area, and contact of the write address with this detection area is monitored. Time point 604 when address contact is detected and empty cell 606 is detected in in-device signal 605
Then, the writing is temporarily stopped and the empty cell 606 is erased.
If the approach detection threshold value 602 is set to about 1 cell time in order to save the FIFO memory capacity, the write address and the read address maintain a steady state when the average phase difference becomes about 1/2 cell time, and the address of both addresses is maintained. The transition average slope is 26/27 [bytes / clock cycle].

In this method, empty cells 6 to be erased
The timing of 06 is uncertain, and the operation does not match between the active system and the standby system when the transmission line interface is duplicated. The reason is that in the example shown in FIG.
Frame counter and FIF of frame generation unit 511
This is because the O address counter 507 is self-propelled in the active system and the standby system, and the operation phase is not deterministic, so that the address comparison operation is different between the active system and the standby system.

In the address transition shown in FIG. 6, if the read phase is shifted, the write address also has an average phase difference of about 1 /.
The operation changes so as to keep the time for two cells. Since the cell phase on the write side is fixed, this change appears in the form of changing the empty cells to be deleted. Even if the writing phase is configured such that the frame counter and the address counter do not run by themselves, if the clock distribution is divided between the FIFO writing side and the reading side, the operation of the address comparison 508 is analog due to the variation of the distribution system. In some cases, the process may show uncertain behavior. In addition to the above, as shown in the example of FIG. 5, when a function 512 for inserting a cell for supervisory control communication into an empty cell on an in-device signal by writing is installed, the operation timing is set to the active system and the standby system. If it is different, the operation of the write stop control means 509 is changed.

In addition to the above, there is a second conventional technique in which the redundant cell deleting operation on the transmission path transmitting side can be partially deterministic. This is shown in 1991 IEICE Autumn Meeting B-485 "A Study on In-Device Monitoring Method and In-Device Information Transfer Method in ATM Device: Ikematsu, Tsutsui, Kurano, Nishihara, Miyamoto".
The above-mentioned conventional technique specifies the surplus cell timing by the SDH frame phase. A surplus cell is generated at the head of the frame in M frame cycles, and each unit in the apparatus processes the frame head timing as a surplus cell. If the conventional technique is used for the surplus cell deletion control in the transmission line transmission interface unit, the surplus cell at the head of the frame is definitely deleted.

However, the amount of surplus cells whose timing is designated by this conventional technique is (8000 / M) [cells / second]. On the other hand, in the present example, the total number of surplus cells to be deleted is 360 kHz × 1/53 = in the case of the STM-1 transmission line.
It is 360,000 / 53 [pieces / second]. Here 360kHz
Is the cell cycle of the in-device signal. Therefore, even in the method according to this conventional technique, it is not always necessary to definitely perform all the surplus cell deletion operations. Some redundant cell deletion operations occur at uncertain timings. In order to make all the surplus cell removal operations deterministic by this method, it is necessary to lengthen the frame pulse period. When there are 360,000 / 53 [pieces / second] as in the above example, the frame pulse period must be 8/53 kHz. In this case, there is a problem that the frame pulse period becomes too long and the timing system design becomes complicated.

Further, the cell length conversion section in the interface section on the transmission path reception side performs this inverse conversion.
A surplus cell is added by stopping the IFO reading. The surplus cell addition timing is also determined based on the comparison between the write address and the read address of the FIFO. Since this buffer is a transfer circuit between the transmission path reception clock and the internal clock, the surplus cell addition timing determination operation is an analog process that is affected by the transmission path reception signal jitter, wander, and transmission delay, and is uncertain. Behavior is shown. That is, the surplus cell addition operation at the time of receiving the transmission path is uncertain in the amount and timing of addition depending on the transmission path, and the signal that has passed through the working transmission path and the signal that has passed through the protection transmission path are the same. do not do.

In order to make the cell arrangements of the received signal on the current transmission path and the received signal on the protection transmission path coincide with each other, it is necessary to provide a method of coping with the inconsistency of the cell intervals caused by the surplus cells. First, consider whether or not the inconsistency of the cell intervals caused by the cell length conversion on the transmission side and the cell length conversion on the reception side can be all corrected by comparing the working system signal and the protection system signal in the transmission path receiving side device. View. In this case, there are the following two problems. The first problem is that the in-device cell throughput of the receiving device must be sufficiently high.
The second problem is that there is no resistance to transmission line bit errors.

This will be described with reference to FIG. FIG. 7 is an explanatory diagram showing a problem when the conventional technique is used for the cell length conversion on the transmission side transmission side. In FIG. 7, the upper side shows the processing on the transmission path transmission side, and the lower side shows the processing on the transmission path reception side, each of which has a working system and a backup system.

The first problem occurs when a cell for in-network supervisory control communication is inserted in the transmission line interface section.
As shown in FIG. 7, processing 702 of the active transmission line transmission interface unit is performed for the in-device signal 701 of the transmission side device.
The processing 703 of the backup transmission line interface section is to insert the supervisory control communication cell into an arbitrary empty cell, delete the arbitrary empty cell, and send out to the transmission line as described above.

In the process 704 of the active system transmission line receiving interface unit and the process 705 of the standby system transmission line receiving interface which receive this, the supervisory control communication cell is inserted into an arbitrary empty cell through each transmission line, The surplus cell is added at the timing of.

Consider the cell array synchronization processing 706 for correcting the arrangement for the output cell stream from here. It can be seen that the surplus cells added by the cell length conversion on the receiving side can be deleted once, but the empty cells received from the transmission line cannot be deleted. This is because the timing when an empty cell is present in one system may be a supervisory control communication cell in the other system, so the empty cell received from the transmission line cannot be deleted. Therefore, for cell array synchronization, the empty cell deleted by the cell length conversion on the transmission path transmission side is simply reproduced (added), and the internal signal 701 of the transmission side apparatus 701 is transmitted without deleting other empty cells. It is necessary to reproduce the effective cell spacing. The valid cell is a cell used by the user other than the empty cell, the supervisory control communication cell and the surplus cell. The time interval between the effective cells is called the effective cell interval, and in order to reproduce this time interval, it is necessary that the in-device cell throughput of the receiving side device is larger than the in-device cell throughput of the transmitting side.

The second problem is that the individual cells received from the transmission line are compared between the active system and the standby system,
This is because the empty cell insertion position is determined. As can be seen from the cell array synchronization processing 706 in FIG.
In this method, when the arrangement is corrected, the active system signal 71
When 1 is a valid cell and one is an empty cell or a supervisory control communication cell, the user cell is buffered to add an empty cell. In this case, if a user cell is mistaken as an empty cell or a supervisory control communication cell due to a transmission line bit error, an unnecessary empty cell is added. On the contrary, if the empty cell or the supervisory control communication cell is mistaken for the user cell, the necessary empty cell is not added. In this way, due to a bit error in the transmission path, the cell interval becomes abnormal, and the phase synchronization is immediately lost.

As described above, in order to reproduce the cell array in the transmitting side device in the cell array synchronizing process on the receiving side, the in-device cell throughput of the receiving side device is larger than the in-device cell throughput of the transmitting side, and , It can be seen that there is a problem in the resistance to transmission line bit error because the empty cell addition timing is determined based on the received signal comparison. In addition, since the condition of the in-device cell throughput between the transmitting-side device and the receiving-side device is not required and the resistance to transmission line bit error is ensured, the cell-interval control in the receiving-side device is performed by It must be limited to controlling the position of surplus cells generated by throughput.

That is, it is necessary to adopt a method in which the cell spacing of the transmission path transmission side device is adjusted in the active system and the protection system, and only the position of the surplus cell added by the self device is controlled on the transmission path reception side device. ..

[0019]

As described above, in the prior art, the effective cell interval mismatch between the working system and the protection system occurs in both the cell length conversion on the transmission side and the cell length conversion on the reception side. That is, the arrangement (time interval) of effective cells differs between the active system and the standby system. Since it is difficult to correct all these inconsistencies only by the transmission path receiving side device, as described above, both the transmission path transmitting side device and the transmission path receiving side device allocate the effective cells to the active system and the standby system, respectively. It is necessary to match with the system.

The objects of the present invention are the following two points. The first purpose is related to the cell length conversion method on the transmission path transmission side. The empty cell deletion operation in the transmission path transmission interface section is made deterministic, and the placement of effective cells on the transmission path is determined by the active system and the standby system. That is, there should be no discrepancy between them. In addition, this is to be realized by timing control that is as simple as possible. The second purpose relates to the control of the surplus cell position of the device on the transmission path receiving side, and is a method of matching the cell arrangement between the active system reception signal and the standby system reception signal. In addition, this surplus cell position control is to be realized without increasing the load on the transmission line interface unit.

[0021]

The first problem described above is an ATM communication device which transmits / receives cells which are fixed length blocks in an Asynchronous Transfer Mode (ATM) and which is connected to a transmission line. The ATM communication apparatus is provided with a dual structure consisting of a working system and a standby system of a transmission line transmission interface unit for converting the format of the transmission line cell format into a transmission line cell format, and the transmission line transmission interface unit is currently used. In an ATM communication device having a pre-stage device located upstream of a system and a standby system, the pre-stage device outputs a surplus cell which is present in the ATM communication device but is not sent to a transmission line at a constant ratio. Means and cell identification information output means for outputting information for distinguishing the surplus cell output by the surplus cell output means from other cells, Each of the two transmission line transmission interface units detects the cell based on the information from the cell identification information output unit to detect whether or not the cell is a surplus cell, and in the case of a surplus cell, deletes the surplus cell. It is possible to solve the problem by matching the amount of cells to be transmitted on the transmission line with the maximum amount of data that can be transmitted on the transmission line by deleting excess cells at a constant ratio by these means. Since the empty cells other than the surplus cells are necessary for saving the cell interval, the transmission path transmission interface section regards them as one kind of valid cells and allows them to pass, and does not delete them in normal times.

The cell identification information output means adds information for distinguishing the surplus cell and another cell to the cell and outputs the cell, and the detection means outputs the cell based on the information added to the cell as the surplus cell. It is possible to detect whether or not.

The cell identification information output means outputs information for distinguishing the surplus cell from other cells via a control line,
The detection means can detect whether or not the cell is a surplus cell via the control line based on the information from the cell identification information output means.

It is also possible to predetermine all the surplus cells to be deleted in the transmission path transmission interface section and periodically output the generation thereof. That is, the cell identification information output means periodically outputs information that distinguishes the surplus cell from other cells. This cycle is determined by the surplus cell amount required for the above cell throughput matching, and
It does not have to coincide with the timing of the DH frame, the physical layer cell, or the like.

The transmission line transmission interface unit normally deletes only surplus cells. This cycle is determined by the surplus cell amount, that is, the throughput difference between the inside of the device and the transmission path, and may not coincide with the timing of the SDH frame or the physical layer cell. Since empty cells other than the surplus cells are necessary for saving the cell interval, the FIFO for cell length conversion is regarded as a kind of valid cell and is passed through, and is not deleted in normal times.

Next, the second problem allows the surplus cell to occur at an uncertain timing at the time of converting the cell length on the receiving side of the transmission line, but this is caused by the cell array synchronization unit located at the subsequent stage. It is realized by modifying. That is, an ATM communication device that transmits / receives cells of fixed length blocks in an Asynchronous Transfer Mode (ATM) and is connected to a transmission line, from the ATM communication transmission line cell format to the in-device cell format. In an ATM communication apparatus having a duplex configuration of a transmission path receiving interface section that performs format conversion and including a working system and a standby system, the transmission path receiving interface section outputs a surplus cell in the ATM communication apparatus. The surplus cell output means and the cell identification information output means for outputting information for distinguishing the surplus cell from other cells when the surplus cell is output by the surplus cell output means, and the transmission path receiving interface Between the effective cells used by the user on the output signal after conversion at the transmission line receiving interface section, which is located in the subsequent stage of the section. A cell array synchronization unit that matches the distance between the active system and the standby system, and the cell array synchronization unit receives the duplexed transmission path based on the information from the cell identification information output means. Detecting means for detecting whether or not the cells from the active system and the cells from the standby system of the communication interface unit are surplus cells respectively, and converting means for rearranging the surplus cells of the active system and the spare cells of the standby system at the same position. Have and.

The converting means deletes the surplus cells when the surplus cells are detected, and deletes the surplus cells from the working system and the spare system of the duplexed transmission line receiving interface section. It is possible to have an inserting means for determining a necessary extra cell amount from the extra cell amount and inserting the extra cell amount at the same position of the current system signal and the spare system signal.

Further, the converting means detects, when the surplus cell from the first system is detected, when either the current system or the standby system of the transmission line receiving interface section is set as the first system. , A deleting means for deleting the surplus cell, and a surplus cell from the other system of the first system of the transmission line receiving interface unit, when detecting a surplus cell from the first system of the transmission line receiving interface unit. Insertion means for inserting an extra cell at the same position in the cell array.

As described above, one or both surplus cells of the active system and the standby system are temporarily deleted or separated,
The above problem can be achieved by reinserting a surplus cell for re-matching this with the in-device signal rate at a timing common to the active system and the standby system. For this purpose, it has a FIFO memory for cell array synchronization, and deletes or separates surplus cells by stopping writing, and inserting surplus cells by stopping reading. Since the empty cells other than the surplus cells are necessary for saving the cell interval, the FIF for cell array synchronization is used.
In O, it is regarded as a type of valid cell and is allowed to pass, and is not deleted in normal times.

[0030]

First, the processing on the transmission side of the transmission path will be described below.
In the pre-stage device of the transmission path transmission interface unit, the surplus cell output means periodically stops the output of the transmission path transmission cell and outputs the surplus cell. When the surplus cell is generated by the surplus cell output means, the cell identification information output means outputs information that distinguishes the surplus cell from other cells.

In the format conversion of the interface section on the transmission side of the transmission path, only this periodic surplus cell is deleted and a data byte dedicated to physical layer processing such as overhead is added. This cycle is determined by the amount of surplus cells to be deleted in the transmission path interface unit, and the cycle is set such that if the cells are deleted in this cycle, the cell quantity matches the transmission path cell throughput. Therefore, the normal cell length conversion unit does not need to perform the empty cell deletion control based on the FIFO address comparison, and the operations of the active system and the standby system do not become inconsistent.

Further, since it is known in advance that a periodic surplus cell will be deleted, the content is limited to the transfer information for use in the device even if some transfer information is written.
Therefore, the transmission line sending cell written in the transmission line interface unit will not be lost due to periodic cell deletion. Since the empty cells other than the surplus cells are regarded as a kind of valid cells and are passed, the cell intervals of the in-device signals are preserved except that the periodic surplus cells are deleted.

As described above, by adopting a method in which the cells to be deleted at the time of cell length conversion are determined in advance before the transmission path transmission interface section, the cells are output on the output signals of the working transmission path and the protection transmission path. The intervals can be matched.

Next, the processing on the receiving side of the transmission path will be described below. In the transmission line reception interface unit, physical layer termination processing such as SDH frame termination processing, cell synchronization and format conversion are performed, surplus cell output means adds a surplus cell, and cell identification information output means is the surplus cell output means. When a surplus cell is generated, information that distinguishes the surplus cell from other cells is output and sent to the cell array synchronization unit.

In the cell phase synchronizing section, the detecting means detects the surplus cells based on the information from the cell identification information output means, and the converting means arranges the surplus cells of the working system and the surplus cells of the spare system at the same position. Change the position and perform the position correction process. Specifically, the signal which is the target of the surplus cell position correction is written in the FIFO memory for cell array synchronization. When a surplus cell is detected in the write signal, the FIFO write is temporarily stopped to temporarily delete or separate the surplus cell. FIFO
At the time of reading, the FIFO is used at the required timing of the surplus cell.
A surplus cell is inserted by suspending reading.
This surplus cell insertion is performed at a timing common to the active system and the standby system for matching the cell spacing, and is set to the same amount as the deletion amount for matching the in-device signal speed. For example, the following examples can be considered. The first example is a method of determining the surplus cell insertion interval based on the actual measurement value of the cell throughput on the transmission path, and correcting the surplus cell positions of both the active system and the standby system in accordance with this. The second method is to use one of the duplicated transmission lines as a reference for the surplus cell insertion timing and correct the surplus cell position of the other signal.

Since it has been known in advance that the surplus cells added by the transmission line interface section will be deleted or replaced, therefore, when writing some transfer information, the transfer can be deleted or replaced. Limited to information. The empty cells other than the surplus cells are regarded as a kind of valid cells and are passed through the FIFO for cell array synchronization. Therefore, the cell interval on the transmission path is preserved except the point where the surplus cells are added.

In this surplus cell position correction processing, it is necessary to detect only the in-device header indicating the surplus cells added in the device, and the empty cell insertion timing is determined based on the data comparison of valid cells. Since there is no control to determine, it is not affected by transmission line bit error. In addition, since it is a method of once deleting the surplus cells generated by the in-device cell throughput of the receiving side device and then inserting the same amount of surplus cells again, regardless of the value of the in-device cell throughput of the transmitting side device. The cell array can be stably synchronized.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 show an application example of the present invention in cell length conversion on the transmission side of the transmission path. FIG. 1 is a block diagram of an embodiment of the present invention in the cell length conversion on the transmission side transmission side. In the configuration shown in FIG. 1, an in-device header indicating a surplus cell is added to a surplus cell output in a 53-cell cycle, and the cell length conversion unit detects and deletes this. FIG. 2 shows a configuration diagram of another embodiment of the present invention in the cell length conversion on the transmission side transmission side. The configuration shown in FIG.
Surplus cell output and deletion are performed in synchronization with the pulse of 53 cell cycles.

1 and 2 show an example of a line setting device using the SDH-based ATM system. Output cell flow from the line setting switches (SW) 101 and 201
It is sent to the STM-1 transmission lines 102 and 202. In this case, since the in-device clock frequency is the same as the transmission line and the in-device cell has a length of 54 bytes, the in-device signal 10
Cell throughput of 3 and 203 is 360000 [cell / sec]
Therefore, 1/53 of these must be deleted when converting the cell length. Therefore, the outputs of the SWs 101 and 201 are stopped once every 53 cell cycles, and the surplus cells generated in the device are output at that timing.

Insertion of extra cells in the device in the line setting switches (SW) 101 and 201 will be described.

The output stage of the line setting switch (SW) has an ATM transmission interface circuit for changing the cell format on the transmission line to the cell format in the own device. The interface circuit for ATM transmission outputs a surplus cell output means for newly outputting a surplus cell and a cell identification information output means for outputting information for distinguishing the surplus cell from other cells when the cell formats are replaced. Have and.

As circuits for implementing the ATM transmission interface circuit, a cell buffer for accumulating cells from the ATM transmission line, a write address control circuit for designating a write address of the cell buffer according to a cell format on the transmission line, A read address control circuit that indicates a read address of the cell buffer according to the cell format in the device itself, an address comparison circuit that compares the write address and the read address, and a surplus based on the comparison result from the address comparison circuit. The read address includes a surplus cell instruction circuit that outputs a cell instruction, and an additional circuit that adds information for distinguishing the surplus cell output by the instruction from the surplus cell instruction circuit and other cells to the cell. The control circuit stops the reading of the cell according to the instruction from the surplus cell instruction circuit. To.

That is, the cell buffer stores cells from the ATM transmission line, the write address control circuit indicates the write address of the cell buffer according to the cell format on the transmission line, and the read address control circuit is in its own device. The read address of the cell buffer is designated according to the cell format of. The address comparison circuit compares the write address and the read address, and the surplus cell instruction circuit outputs an instruction of the surplus cell to the additional circuit and the read address control circuit based on the comparison result. In response to an instruction from the surplus cell instruction circuit, the addition circuit adds information that distinguishes the generated surplus cell and other cells to the cell, and the read address control circuit stops reading of the cell.

As described above, from the line setting switch (SW) 101 in FIG. 1, information for distinguishing the output surplus cell from the other cells is added to the cell and output.
As information for distinguishing cells, information indicating that the cells are extra cells generated in the device is added to the cell header. In addition, in the line setting switch (SW) 201 having the ATM transmission interface circuit in FIG. 2, the SW 201, the active interface unit 204, and the standby interface unit 20.
7, a clock distribution unit (not shown) provides a reference phase signal of 53 cell cycle (360/53 kHz) via a control line.
(Frame pulse) 208 is supplied. The clock distribution unit can also be provided inside the line setting switch (SW) 201. Instead of adding the cell identification information shown in FIG. 1, the insertion of extra cells is instructed periodically, that is, by a reference phase signal (frame pulse) 208 having a 53-cell period (360/53 kHz) via a control line. ing.

Next, the transmission line transmission side interface unit 1
In 04 and 204, cell length conversion sections 105 and 20
At step 5, only the surplus cells of the 53 cell period are deleted, and at the same time, SDH frames are generated by the SDH frame generators 106 and 206 to map the cells therein. Since the cell throughput matches the transmission line cell throughput only with this periodic cell deletion, the normal cell length conversion units 105 and 205 need to perform the deletion control of other transmission line empty cells based on the FIFO address comparison. Absent. Therefore, when the transmission line interface is duplicated, the operations of the active systems 104 and 204 and the standby systems 107 and 207 do not become inconsistent.

In the embodiment shown in FIG. 1, in the embodiment shown in FIG. 1, SW1 is used as a method of combining the cell format of the surplus cell deleting operation of the active system interface section and the standby system interface section with the 53 cell cycle stop operation of SW101 and 201.
Since the header indicating that the cell is a surplus cell is added to the periodic surplus cell at 01, the transmission path interface 104
Then, the surplus cell detection unit 108 detects the header to detect the surplus cell cell format.
That is, the transmission path transmission interface 104 detects the cell based on the information from the cell identification information output section, and detects whether or not there is a surplus cell, and in the case of a surplus cell, a deletion section that deletes the surplus cell. Have.

Transmission line transmission interfaces 104 and 2
The detailed operation in 04 will be described. First, the cell from SW101 in FIG. 1 is input to the surplus cell detection unit 108, and the surplus cell detection unit 108 detects a cell header indicating the type of the cell added in SW101, and is not an in-apparatus surplus cell. It is identified and output to the write stop control unit, which is a deletion unit. If it is a surplus cell in the device, the write stop control unit instructs the write address counter to stop writing to the FIFO memory. Also,
The cell from the SW 201 in FIG. 2 is received by the transmission path interface 204, and the instruction from the reference phase signal 208 having a 53-cell cycle is received by the write stop controller.
The write stop control unit, when there are excess cells in the device,
The write address counter is instructed to stop writing to the FO memory.

Further, in the above two embodiments, the transmission line interface units 104 and 204 have the intra-network supervisory control communication cell transmission functions 109 and 209, and in this case, the intra-network supervisory control communication cell is written in an empty cell. The shape is inserted. At this time, it is known in advance that a surplus cell of 53 cell cycles will be deleted, so timing control is performed so that this surplus cell is not programmed. For example, even in the empty cell detecting means of the transmission function 109 of the in-network supervisory control communication cell, similarly to the above-described surplus cell detection unit 108, an extra cell is detected, and the in-network supervisory control communication cell is set to the other empty cell. Write. Alternatively, when the surplus cell detection unit 108 detects a surplus cell, the surplus cell detection unit 108 may instruct the empty cell detection unit of the transmission function 109 of the in-network supervisory control communication cell that the cell is a surplus cell. As a result, the supervisory control communication cell for transmitting the transmission path will not be lost due to the redundant cell deleting operation. Since the empty cells other than the surplus cells are regarded as a kind of valid cells and passed through the cell length conversion FIFO memories 110 and 210, the cells of the in-device signal are excluded except that the surplus cells of 53 cell cycles are deleted. The intervals are saved.

Next, in the cell length conversion FIFOs 110 and 210, when the write phase and the read phase transiently approach, the approach is detected by the address comparisons 111 and 211, and the address can be corrected. This address correction is performed by deleting empty cells other than periodic surplus cells. This is different from the conventional technique in which an arbitrary empty cell is deleted as shown in FIG.
As shown in FIG. 8, since the address approach detection threshold 802 is set large by allowing the capacity of the FIFOs 110 and 210 to have a margin of 1 cell or more, the phase of the read address 801 is uncertain with a width of about 1 cell time. However, in the normal state, the address approach is not detected and the write address 803 is not directly influenced by the read address 801 to become indeterminate. In FIG. 8, the condition of address approach detection is different from that of the conventional technique, and the write operation in the normal state is deterministic even if the read phase is indefinite, and the throughput matching can be achieved only by periodical redundant cell deletion. ..

Detailed operations in the cell length conversion units 105 and 205 will be described. FIFO 110 and 210
Is a cell buffer 12, which is read from the previously written cell. The write address of the FIFO 110 is designated by a write address counter, which is a write address control circuit. The write address counter operates according to the internal clock of the ATM communication device,
The write address can be designated by incrementing 1 when the FIFO 110 writes and decrementing 1 when read. The read address of the FIFO 110 is designated by a read address counter, which is a read address control circuit. The read address counter operates according to the clock on the transmission line, and in the case of the FIFO memory, always indicates the leading address. The address comparison means compares the addresses of the write address counter and the read address counter, outputs the difference between the addresses, and instructs the write stop controller when the data amount increases. The write stop control unit is instructed when the address difference from the address comparison unit becomes equal to or smaller than a predetermined numerical value. For example, by predetermining the address difference to be 2 cells, it is instructed to stop writing when the address difference between the write address counter and the read address counter becomes 2 cells. However, under normal conditions, this operation does not occur because the address difference is kept within 2 cells by the surplus cell deletion of 53 cell cycles.

Therefore, even when the operation phase on the read side is uncertain, the write address transition 803 in the normal state is a deterministic operation, and only the periodic surplus cells 806 are deleted, and the average address transition slope (26 / 27) [Byte / clock cycle] can be maintained.

Similar to the above, the standby system can also be operated.

In addition, when the STM-1 transmission line is transmitted, 360/5
An example in which one surplus cell is generated / deleted at a 3 kHz cycle has been shown, but when applied to an STM-N (N> 1) transmission line, 3 cells are used.
The number of surplus cells per 60/53 kHz cycle may be N.

According to the present embodiment, excess cells are periodically output in the SW section, and only the periodical excess cells are deleted in the transmission line transmission side cell length conversion, and the output signal is set to the transmission line cell throughput. Align. Therefore, the redundant cell deleting operation is deterministic, and the operation does not conflict between the active system and the standby system when the transmission line interface is duplicated.

Next, FIG. 3 shows an example of the configuration of the surplus cell position correcting function on the transmission path receiving side.

FIG. 3 is a block diagram of the cell array synchronizing section of the embodiment of the present invention on the receiving side of the transmission path, in which the surplus cell positions of both the active system and the standby system are detected and the common timing is set. At the same time, the insertion position of the surplus cell is corrected.

In the transmission line reception interface section, S
DH frame termination processing, physical layer termination processing such as cell synchronization, and cell length conversion are performed, and received signals 301 and 302 to which surplus cells have been added are input to the cell array synchronization unit. At this time, an in-device header for identifying the surplus cell is added to the surplus cell as described above. The cell array synchronization unit detects excess cells from this header and corrects their positions.

In this embodiment, the surplus cell insertion positions after cell array synchronization are arranged at equal intervals as much as possible. In the surplus cell detection units 303 and 304, which are the detection means of the active system and the standby system, the surplus cells are detected by the in-device header,
The surplus cell number counting and surplus cell insertion timing creation unit 305 counts this number. As a result, the surplus cell interval to be reinserted when the surplus cell position is corrected is determined, and the surplus cell insertion timing signal 306 is output. For example, from the count values of the surplus cells from the current system reception signal and the surplus cells from the standby system reception signal, the average value of both surplus cells per unit time is calculated to determine the surplus cell interval. The surplus cell insertion timing signal 306 is output according to this interval. This is an operation for detecting the effective cell input speed fluctuation caused by the fluctuation of the transmission line clock frequency and absorbing the fluctuation. The active system signal 301 and the standby system signal 302 are transferred to the respective FIFO memories 307 and 30.
When writing to 8 and a surplus cell is detected in the input signal,
By temporarily stopping the write address counters 309 and 310, the surplus cells are once erased. FI
On the FO read side, the surplus cell insertion timing signal 306
Thus, the read address counters 311 and 312 are temporarily stopped and a surplus cell is added. As a result, since the read suspension control is common to the active system and the standby system, the surplus cell positions are the same in both. That is, they can be rearranged at the same position.

As described above, in this embodiment, since all the surplus cells added by the cell length conversion on the transmission path reception side are once deleted, the cells for supervisory control communication are written in the empty cells in the transmission path reception interface section. In the case of writing, the cells are distinguished from each other so that only the normal empty cells are written without writing in the surplus cells.

FIG. 4 shows the configuration of another embodiment of the surplus cell position correcting function on the transmission path receiving side. In the present embodiment, the surplus cell positions of the spare system signal are replaced according to the surplus cell positions of the working system signal. That is, in this example, the current system received signal 401 is used as the reference for the surplus cell insertion timing,
The surplus cell position of the spare system reception signal 402 is set to the spare system FIF.
Correction is performed using the O memory 403. When the spare cell surplus cell detection unit 404 detects a surplus cell, the spare system FIF is detected.
The surplus cell is erased by temporarily stopping the O write address counter 405. FIFO 403 for the backup system signal
At the time of further reading, when a surplus cell is detected by the surplus cell detection unit 406 of the active system, the FIFO read address counter 407 of the spare system is temporarily stopped to add a new surplus cell. As a result, the positions of the surplus cells in the spare cell row can be matched to the current system and rearranged to the same position.

Further, in this example, the surplus cells that have not been written in the FIFO are held in the surplus cell FIFO unit 408, and the read side of the normal cell FIFO 403 is provided with a function of re-inserting them as surplus cells. There is. The surplus cell FIFO write execution condition is when the spare cell of the spare system is detected, and the read execution condition is when the surplus cell of the active system is detected. By such processing, the surplus cell can be used for purposes such as in-apparatus monitoring control communication. The information that can be transferred by such a surplus cell is information that can be exchanged in position. When the error detection code of a valid cell is calculated and transferred, it is impossible to replace its position. Therefore, the cell write processing is performed separately so that the normal cell is written without writing to the surplus cell. I do.

As described above, as shown in FIGS. 3 and 4, the surplus cells added by the cell length conversion on the transmission path receiving side are once deleted and reinserted at a necessary timing to correct the surplus cell position. .. At this time, the normal empty cell received from the transmission line normally passes through the FIFO of the cell length conversion unit and the cell array synchronization unit as a kind of valid cell, so it is transmitted except for the point where the surplus cell is added. The cell spacing on the road is saved.

In this surplus cell position correction processing, it is necessary to detect only the in-device header indicating the surplus cell added in the device, and the empty cell insertion timing based on the data comparison of valid cells. Since there is no control for determining, there is no influence of transmission path bit error. In addition, since it is a method of once deleting / separating surplus cells generated by the in-device cell throughput of the receiving side device, and then inserting the same amount of surplus cells again, the value of the in-device cell throughput of the transmitting side device Regardless of this, cell array synchronization can be stably achieved. Further, in the configuration shown in FIG. 4, the positions of the surplus cells of the spare system signal are exchanged in accordance with the positions of the surplus cells of the working system signal. The surplus cell positions of may be replaced.

Further, FIGS. 3 and 4 also show the function of the transmission line delay difference compensation. This is because transmission delay difference compensation must also be performed in order to perform cell array synchronization by replacing the surplus cell positions. In the embodiment shown in FIG. 4, the surplus cell position replacement is performed only by the standby system, but the active system reception signal is also written in the active system FIFO memory 409 to absorb the transmission line delay difference.

These functions will be described below. FIFO memories 307 and 409 for the active system and F for the standby system
The output signals from the IFO memories 308 and 403 are compared by the cell comparison units 313 and 410, which are cell comparison means. When it is determined that the output phases do not match, the mode shifts to the delay amount adjustment mode, and in this mode, the FIFO delay insertion amount is adjusted until the output phases match. When the coincidence of the output phases of both systems is detected, the mode is shifted to the delay amount maintaining mode, and in this mode, only the replacement of the surplus cell position is performed. The delay increase / decrease control units 314 and 411 control this state transition, and the delay amount of each FIFO is determined according to the output cell comparison result and the calculation result of the in-FIFO cell amount calculation units 315, 316, 412, and 413. An increase control signal and a delay amount decrease control signal are generated. FIFO
The delay amount is reduced by erasing the normal empty cells other than the surplus cells. The empty cell detectors 317, 318, 414 and 415 detect normal empty cells in the input signal,
At this timing, the FIFO write address counter 30
This function is realized by suspending 9, 310, 416 and 405. The delay amount of the FIFO is increased by adding an empty cell. The FIFO read address counters 311, 312, 41 are unconditionally applied during the delay amount increase control.
This function is realized by pausing 7 and 407.

According to the present embodiment, the surplus cell added to the protection system transmission line signal is once deleted, and the surplus cell is added to the protection system signal again at the timing of the surplus cell added to the working system transmission line. Since it is only the in-device header that indicates a surplus cell that needs to be detected in this process, it is not affected by the transmission path bit error and is the control of the cell throughput in the own device. It is not affected by the in-device cell throughput of the transmitting device.

Since the cell arrays on the received signals from the working transmission line and the protection transmission line can be always matched,
It is effective in transmission line non-interruption switching based on data bit comparison and collation.

As described above, according to the present invention, the timing control of the transmission side processing circuit is simple, and in the surplus cell replacement process on the reception side, the influence of the cell throughput in the device of the transmission side device and the transmission path bit error are suppressed. It has the advantage of not being affected.

[0070]

According to the present embodiment, on the transmission line transmission side, the empty cell deletion operation on the transmission line can be made deterministic, and the arrangement of valid cells can be made to match between the active system and the standby system.

On the receiving side of the transmission path, the cell arrangement can be matched between the active system and the standby system.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention in a cell length conversion on a transmission path transmission side.

FIG. 2 is a configuration diagram of another embodiment of the present invention in cell length conversion on the transmission path transmission side.

FIG. 3 is a configuration diagram of an embodiment of the present invention on a transmission path reception side.

FIG. 4 is a configuration diagram of another embodiment of the present invention on the receiving side of the transmission path.

FIG. 5 is an explanatory diagram showing an example of a conventional technique in cell length conversion on a transmission path transmission side.

FIG. 6 is a cell length conversion FIFO in the related art shown in FIG.
Explanatory drawing of the address transition of O, and the address approach detection method.

FIG. 7 is an explanatory diagram showing a problem when the conventional technique is used for the cell length conversion on the transmission path transmission side.

FIG. 8 is a cell length conversion F in the embodiment of FIGS.
Explanatory drawing of address transition of IFO.

[Explanation of symbols]

101 ... Line setting switch (SW), 102 ... STM-1
Transmission line (working system), 103 ... In-device signal, 104 ... Transmission line sending side interface unit (working system), 105 ... Cell length conversion unit, 106 ... SDH frame generating unit, 107 ... Transmission line sending side interface unit (spare) System), 108 ... surplus cell detection unit, 109 ... in-network supervisory control communication cell transmission function, 110 ...
Cell length conversion FIFO memory, 111 ... FIFO address comparison unit, 112 ... Cell array on in-device signal, 113 ...
Cell array on the active transmission path, 114 ... Cell array on the standby transmission path, 201 ... Line setting switch (SW), 202 ...
STM-1 transmission line (working system), 203 ... In-device signal, 20
4 ... Transmission path transmission side interface unit (active system), 205 ...
Cell length conversion unit, 206 ... SDH frame generation unit, 207
... Transmission line transmitting side interface unit (spare system), 208 ... 5
Reference phase signal (frame pulse) of 3 cell cycle, 209 ...
In-network supervisory control communication cell transmission function, 210 ... Cell length conversion FIFO memory, 211 ... FIFO address comparison unit, 2
12 ... Cell arrangement on in-apparatus signal, 213 ... Cell arrangement on working transmission line, 214 ... Cell arrangement on standby transmission line, 3
01 ... Working system reception signal, 302 ... Standby system reception signal, 30
3 ... Working system surplus cell detection unit, 304 ... Standby system surplus cell detection unit, 305 ... Surplus cell number count / surplus cell insertion timing creation unit, 306 ... Surplus cell insertion timing signal,
307 ... Current system FIFO memory, 308 ... Standby system F
IFO memory, 309 ... Working system write address counter, 310 ... Standby system write address counter, 311
... Read address counter for active system, 312 ... Read address counter for spare system, 313 ... Cell comparison unit, 314
... delay increase / decrease control unit, 315 ... active system FIFO in-cell amount calculation unit, 316 ... standby system FIFO-in-cell amount calculation unit, 3
17 ... Working system empty cell detection unit, 318 ... Standby system empty cell detection unit, 401 ... Working system received signal, 402 ... Standby system received signal, 403 ... Standby system FIFO memory, 404 ... Standby system surplus cell detection unit, 405 ... Spare system write address counter, 406 ... Working system surplus cell detection unit, 407 ...
Spare system read address counter, 408 ... surplus cell FIFO unit, 409 ... active system FIFO memory, 410
... Cell comparison unit, 411 ... Delay increase / decrease control unit, 412 ... Working system FIFO cell amount computing unit, 413 ... Standby system FIFO
O internal cell amount calculation unit, 414 ... Active cell empty cell detection unit, 4
15 ... Spare cell empty cell detection unit, 416 ... Working system write address counter, 417 ... Working system read address counter, 501 ... Cell output unit, 502 ... In-device signal, 5
03 ... Transmission path transmission side interface section, 504 ... STM
-1 transmission path, 505 ... FIFO memory for cell length conversion, 5
06 ... write address counter, 507 ... read address counter, 508 ... FIFO address comparison unit, 509
... Empty cell detection / write stop controller 510 ... Cell output temporary stop instruction 511 ... SDH frame generator 512
... in-network supervisory control communication cell insertion unit, 513 ... cell length conversion unit, 514 ... cell array on device signal, 515 ... cell array on transmission path, 601 ... FIFO read address transition,
602 ... Address approach detection threshold, 603 ... FIFO write address transition, 604 ... Time of empty cell deletion condition detection,
605 ... Cell array on in-device signal, 606 ... Empty cell to be deleted, 701 ... In-device signal of transmission path transmission side device, 7
02 ... Processing of transmission line transmission interface unit (active system), 7
03 ... Processing of transmission line transmission interface unit (spare system), 7
04 ... Processing of transmission path reception interface unit (active system), 7
05 ... Processing of transmission path reception interface unit (spare system), 7
06 ... Cell array synchronization processing of transmission path receiving side device, 707 ...
Cell array of working system transmission signal, 708 ... Cell array of protection system transmission signal, 709 ... Cell array processed by transmission line receiving interface unit (working system), 710 ... Transmission line receiving interface unit (spare system) ) Processed cell array,
711 ... Active system reception signal at cell array synchronization, 712 ... Standby system signal at cell array synchronization, 801 ... FIFO read address transition, 802 ... Address approach detection threshold, 80
3 ... FIFO write address transition, 804 ... Surplus cell detection time point, 805 ... Cell array on in-device signal, 806 ... 5
A surplus cell with a 3-cell period.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiromi Ueda 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation (72) Inventor Hiroshi Ota 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (10)

[Claims] 1. Asynchronous transfer mode (ATM)
Transfer Mode) is an ATM communication device that transmits and receives cells that are fixed-length blocks and is connected to a transmission line.
The TM communication apparatus is provided with a dual structure including a working system and a standby system of a transmission line transmitting interface unit for converting the format from the cell format in the communication line to the transmission line cell format, and the working system and the standby system of the transmission line transmitting interface unit are provided. In an ATM communication device having a pre-stage device located in a pre-stage with a system, the pre-stage device outputs a surplus cell that is present in the ATM communication device but is not sent to a transmission line at a fixed ratio, and a surplus cell output means. There is provided cell identification information output means for outputting information for distinguishing the surplus cell output by the surplus cell output means from other cells, and each of the two transmission path transmission interface sections outputs the cell identification information. Detecting means for detecting whether or not the cell is a surplus cell based on the information from the means, and in the case of a surplus cell, deleting the surplus cell That remove and means, ATM communication apparatus having a cell array synchronization function, characterized in that to match the maximum amount of data that can be transmitted path outgoing transmission path outgoing cell weight by excess cell deletion of a constant ratio by these means. 2. The cell identification information output means according to claim 1, wherein information for distinguishing between the surplus cell and another cell is added to the cell and output, and the detection means is added to the information added to the cell. An ATM communication device having a cell array synchronization function, which detects whether or not a cell is a surplus cell based on the above. 3. The cell identification information output means according to claim 1, which outputs information for distinguishing a surplus cell from another cell via a control line, and the detection means outputs the information via the control line. A having a cell array synchronization function characterized by detecting whether or not a cell is a surplus cell based on information from the cell identification information output means
TM communication device. 4. An ATM communication device having a cell array synchronization function according to claim 2 or 3, wherein the cell identification information output means periodically outputs information for discriminating between a surplus cell and another cell. .. 5. Asynchronous transfer mode (ATM)
Transfer Mode) is an ATM communication device that transmits and receives cells that are fixed-length blocks and is connected to a transmission line.
In an ATM communication device having a duplex structure composed of a working system and a standby system of a transmission line receiving interface unit for converting a format from a TM communication transmission line cell format to an in-device cell format, the transmission line receiving interface unit is: Surplus cell output means for outputting surplus cells in the ATM communication device, and cell identification information output means for outputting information for distinguishing surplus cells from other cells when the surplus cell output means outputs surplus cells And located at a stage subsequent to the transmission path receiving interface section, and setting the interval of effective cells used by the user on the output signal after conversion in the transmission path receiving interface section as the active system and the standby system. And a cell array synchronization unit for matching the cell array synchronization unit, wherein the cell array synchronization unit performs duplication based on information from the cell identification information output unit. Detecting means for detecting whether each redundant cell for the cell from the cell and a standby system from the working system of the transmission path reception interface section which,
An ATM communication device having a cell array synchronizing function, comprising: a conversion means for rearranging a surplus cell of an active system and a surplus cell of a standby system at the same position. 6. The converting means according to claim 5, wherein the converting means deletes the surplus cells when the surplus cells are detected, and the surplus cells from the working system of the duplexed transmission line receiving interface section. And an amount of surplus cells from the spare system, a necessary surplus cell amount is determined, and the surplus cell amount is newly inserted at the same position as the working system signal and the spare system signal. An ATM communication device having a cell array synchronization function. 7. The converting means according to claim 5, wherein when either the active system or the standby system of the transmission line receiving interface section is set as the first system, the surplus cell from the first system is removed. When detecting a surplus cell from another system of the first system of the transmission line receiving interface unit when deleting the surplus cell, the first means of the transmission line receiving interface unit is detected. An ATM communication device having a cell array synchronization function, comprising: an insertion means for inserting an extra cell at the same position of the cell array from the system. 8. The transmission line reception according to claim 1, further comprising a duplex structure comprising an active system and a standby system of a transmission line reception interface section from the transmission line cell format to the cell format in the ATM communication device. A cell array synchronization unit, which is located at a subsequent stage of the communication interface unit and matches the interval of effective cells used by the user on the output signal after conversion by the transmission line reception interface unit between the active system and the standby system. The transmission line receiving interface section has a surplus cell output means for outputting at a constant ratio surplus cells that are present in the ATM communication device but are not sent to the transmission line, and are output by the surplus cell output means. Cell surplus cell and a cell identification information output means for outputting information for distinguishing another cell from each other, and the cell array synchronization unit is configured to output the cell identification information. Detecting means for detecting whether or not the cells from the active system and the cells from the standby system of the transmission line receiving interface unit are respectively redundant cells based on the information from, and the excess cells of the active system and the redundant system of the standby system. A having a cell array synchronization function, characterized by having a conversion means for rearranging cells at the same position.
TM communication device. 9. Asynchronous transfer mode (ATM)
Transfer Mode) is an ATM communication device that transmits and receives cells that are fixed-length blocks and is connected to a transmission line.
The TM communication transmission line is provided with a duplex configuration composed of a working system and a standby system of a transmission line transmitting interface unit for converting the format into a device cell format, and the working system and the standby system of the transmission line transmitting interface unit. When operating an ATM communication device having a pre-stage device positioned in front of the above, the surplus cells that are present in the ATM communication device but are not sent to the transmission line are output at a constant ratio, and the surplus cell and other cells are output. Is output, the cell is detected as to whether or not the cell is a surplus cell based on the information, and when the cell is a surplus cell, the surplus cell is deleted. 10. Asynchronous transfer mode (ATM)
transfer mode), which is an ATM communication device connected to a transmission line by transmitting / receiving a fixed-length block cell.
When operating an ATM communication device having a duplex configuration including a working system and a standby system of a transmission line receiving interface unit for converting a format from a cell format in the TM communication device to a transmission line cell format, in the ATM communication device, The surplus cells that are present but not sent to the transmission line are output at a fixed ratio, the identification information that distinguishes the surplus cell from other cells is output, and the current use of the transmission line reception interface unit is based on the identification information. It is detected whether the cells from the system and the cells from the spare system of the transmission line receiving interface unit are surplus cells, respectively, and the surplus cells of the working system of the transmission line receiving interface unit and the spare of the transmission line receiving interface unit are detected. A cell array synchronization method characterized by rearranging redundant cells of a system at the same position.