JP2842678B2 - Phase information transfer method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital synchronous network defined by NNI, SONET, and the like, and more particularly, to a phase information transfer method accompanying data phase change.

2. Description of the Related Art Conventionally, a phase information transfer method associated with this type of phase change involves preparing a memory for a write data head flag in addition to a data memory, and controlling the memory by controlling a write address counter and a read address counter similar to data. In this method, a read data head flag is generated based on information output from the CPU.

A conventional phase information transfer method using a memory for a write data head flag will be described in detail.

FIG. 2 is a block diagram showing a configuration of a conventional phase information transfer method. Fig. 2 shows the stuff variation and analog jitter caused by the use of memory for signals (signals that use pointers as the start position information of internal data) used in digital synchronous networks specified by NNI and SONET. FIG. 6 is a functional diagram for absorbing data and the like and replacing data and its leading position information with a phase in the apparatus.

The input signal from terminal 1 is a write address counter 4
Thus, only necessary data is written to the memory 3. The write data phase information detection circuit 6 detects the phase information included in the input signal from the terminal 1, and the write data head flag 7 determines the start of the write data to the memory 3 based on the phase information from the write data phase information detection circuit 6. A flag is generated, and the write data head flag itself is input to the memory 3 similarly to the data. On the read side, the read data and the read data head flag are output from the memory 3 by the read address counter 5. The read data head flag detection circuit 8 detects the read data head flag read from the memory 3, and the read data phase information generation circuit 9 determines the relationship between the position of the flag from the read data head flag detection circuit 8 and the previous flag. For example, the phase information of the read data is generated from the read data. The read data phase information insertion circuit 10 inserts the read data phase information from the read data phase information generation circuit 9 into the data from the memory 3, and finally the signal after the phase change is output from the terminal 2.

However, the conventional phase information transfer method described above is
To prepare a memory equivalent to the data for the data head flag, the larger the data memory capacity is, the larger the hardware scale will be, and if the memory does not have a reset function, abnormalities such as alarm release There is a possibility that unnecessary flag information may remain in the memory during the phase optimization of writing and reading of the memory at the time of recovery from the state,
There is also a drawback that the transfer of phase information of data to the downstream determined by the flag position and the relationship between the flags is delayed unless special processing is performed for the upstream fluctuation.

The present invention has been made in view of the above-described conventional circumstances, and accordingly, an object of the present invention is to provide a novel phase information transfer method capable of solving the above-described disadvantages inherent in the conventional technology. It is in.

Means for Solving the Problems In order to achieve the above object, according to the present invention, a phase information transfer method is provided on a writing side of a memory generated from phase information indicating a head position of data extracted from an input side signal. Means for accumulating information at the start position of the write data of a write address counter for controlling data writing to the memory by a write data start flag indicating the start of data and generating an address relative value of the write data start flag; Means for comparing the address relative value of the flag with information of a read address counter for controlling data read from the memory, and generating a read data head flag which is position information corresponding to the write data head flag on the read side phase; The read data destination is determined by the write data head flag. Means for driving a function of generating a head flag and stopping the function of generating the read data head flag based on the read data head flag and input signal abnormality information until the write data head flag is generated; and Means for generating phase information of the data on the read side by the head flag, incorporating the information into the read data, and outputting the data.

Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. In one embodiment of the present invention, the present invention is applied to the above-described conventional side.

Referring to FIG. 1, as described above, the present embodiment employs an NN
For signals used in digital synchronous networks specified by I, SONET, etc. (signals using pointers as the start position information of internal data), use memory to absorb fluctuations due to stuff and analog jitter, etc. A function for transferring data and its start position information to a phase in the apparatus will be described. Terminal 1 is a signal input terminal from the line side. The memory 3 stores only data excluding management signals such as overhead information from the terminal 1, that is, only signals dominated by the start position information in the frame of predetermined data included in the input signal. The write address counter 4 and the read address counter 5 control writing of data to the memory 3 and reading of data from the memory 3 in accordance with the input signal phase and the internal phase of the apparatus, respectively. The write data phase information detection circuit 6 detects the phase information from the input signal from the terminal 1, and the write data head flag generation circuit 7 uses the phase information from the write data phase information detection circuit 6 to output the head flag of the write data to the memory 3. Generate The write data head flag address relative value generation circuit 81
The information at the head position of the write data of the write address counter 4 that controls data writing to the memory 3 is accumulated by the head flag of the write data from the write data head flag generation circuit 7, and the address relative value of the write data head flag is generated. I do. The read data head flag generation circuit 82 compares the address value of the write data head flag from the address relative value generation circuit 81 with the information from the read address counter 5 and determines that the value of the read address counter 5 is relative to the address of the write data head flag. When the value matches, a read data head flag is generated. The abnormal state detection circuit 83 detects an abnormal state such as input loss or loss of synchronization with respect to the input signal from the terminal 1 and outputs an alarm. The read data head flag generation control circuit 84 causes the read data head flag generation circuit 82 to start operating according to the write data head flag from the write data head flag generation circuit 7, while the read data head flag from the read data head flag generation circuit 82 And a function of stopping by an alarm signal from the abnormal state detection circuit 83. The read data phase information generation circuit 9 generates the phase information of the read data based on the flag from the read data head flag generation circuit 82, and the read data phase information insertion circuit 10 generates the read data phase information into the read data from the memory 3. The phase information from the circuit 9 is inserted, and the signal after the phase change is output from the signal output terminal 2 to the next processing step in the device.

Effect of the Invention As described above, according to the present invention, a read data head flag is written by using information of a write data head flag and a memory write / read address counter without using a memory for a data head flag. , The hardware scale can be reduced, and the generation function of the read data head flag is controlled by the write data head flag, the input signal abnormality information, and the previous read data head flag, and the generation of unnecessary flags is prohibited. As a result, there is an effect that accurate processing on the reading side can be performed without using a special method when recovering from an abnormal state such as when an alarm is released.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of a phase information transfer method according to the present invention, and FIG. 2 is a block diagram of a conventional technique. 1 ... input terminal, 2 ... output terminal, 3 ... memory, 4 ...
... Write address counter, 5 ... Read address counter, 6 ... Write data phase information detection circuit, 7
…… Write data head flag generation circuit, 8 …… Read data head flag detection circuit, 9 …… Read data phase information generation circuit, 10 …… Read data phase information insertion circuit, 81 …… Address relative value of write data head flag Generation circuit, 82 ... read data head flag generation circuit,
83: Abnormal state detection circuit, 84: Read data head flag generation control circuit

Continuation of the front page (56) References JP-A-4-119032 (JP, A) JP-A-3-26032 (JP, A) JP-A-3-26033 (JP, A) (58) Fields studied (Int .Cl. ⁶ , DB name) H04L 7/00

Claims (1)

(57) [Claims] [Claim 1] NNI of CCITT (International Telegraph and Telephone Consultative Committee)
(Network Node Interface) and Bellcore (Bell Communi
cations Research) SONET (Synchronous Optical Net)
work transport systems), in the phase information transfer method accompanying the data phase change, the memory write side generated from the phase information indicating the head position of the data extracted from the input side signal. Means for accumulating information at the start position of the write data of a write address counter for controlling data writing to the memory by a write data start flag indicating the start of data and generating an address relative value of the write data start flag; Means for comparing the address relative value of the flag with information of a read address counter for controlling data read from the memory, and generating a read data head flag which is position information corresponding to the write data head flag on the read side phase; , The write data head Means for driving the function of generating the read data head flag by the lag and stopping the function of generating the read data head flag based on the read data head flag and the abnormality information of the input signal until the write data head flag is generated And a means for generating phase information of data on the read side by the read data head flag, incorporating the information into read data, and outputting the data.