JPH04127736A - Phase information transfer system - Google Patents

Abstract

PURPOSE:To reduce the scale of a hardware by generating a read data head flag by using a write data head flag and the information of a read address counter to a memory without using the memory to the data head flag. CONSTITUTION:An address relative value generation circuit 81 for the write data head flag stores information at the head position of write data in a write address counter 4 and generates the address relative value of the write data head flag. A read data head flag generation circuit 82 compares the write data head flag address value from the address relative value generation circuit 81 with the information from a read address counter 5 and generates the read data head flag when the value of the read address counter 5 is coincident with the address relative value of the write data head flag. Thus, it is not necessary to prepare memories for the data head flag as many as data, and the scale of the hardware is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital synchronous network defined by NNI, 5ONET, etc., and particularly relates to a phase information transfer system associated with data phase switching.

Conventional technology The conventional phase information transfer method associated with this type of phase switching is to write data into the data memory pool, write the memory for the data head flag into the data memory, write the data in the same way, and then write the data into the data storage pool. Under the control of a counter, a read data header flag is generated for each piece of information output from memory.

A conventional phase information transfer method using memory for the write data head flag will be explained in detail.

No. 2121 is a block diagram showing the configuration of a conventional phase information transfer system. Figure 2 shows a signal used in a digital synchronous network specified by NNI and 5ONET (a signal that uses a pointer as information on the start position of internal data), using memory to control staff fluctuations and analog FIG. 3 is a functional diagram for absorbing jitter and the like and replacing the data and its head position information with the internal phase of the device.

The input signal from the terminal 1 is written into the memory 3 by the write address counter 4. Only necessary data is written into the memory 3. The write data phase information detection circuit 6 detects the phase information included in the input signal from the terminal 1. The first flag of the write data to the memory 3 is input to the memory 3 in the same manner as the data.On the read side, the read address counter 5 reads out the data from the memory 3!
- Output the data and the read data head flag.

The read data head flag detection circuit 8 detects the read data head flag read from the memory 3, and the read data phase information generation circuit 9 detects the position of the flag from the read data head flag detection circuit 8 and its relationship with the previous flag. The phase information of the read data is generated from etc. The read data phase information insertion circuit 10 inserts the read data phase information from the read data phase information generation circuit 9 into the data from the memory 3, and finally the signal after phase switching is output from the terminal 2.

Problems to be Solved by the Invention However, in the conventional phase information transfer method described above, in order to prepare a memory equivalent to the data for the data head flag, the more a large data memory capacity is required, the more the accompanying hardware is required. In addition, if the memory does not have a recent function, there is a risk that unnecessary flag information may remain in the memory when optimizing the phase of writing and reading of the memory when recovering from an abnormal situation such as when an alarm is canceled. This also has the disadvantage that the transfer of phase information of data to the downstream determined by the flag position 1 and the relationship between the flags is delayed in adapting to upstream fluctuations unless special processing is performed.

The present invention has been made in view of the above-mentioned conventional situation,
Accordingly, an object of the present invention is to provide a novel phase information transfer method that makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, the phase information transfer method according to the present invention transfers data on the writing side of the memory generated from phase information representing the start position of data extracted from the input side signal. means for generating an address relative value of the write data head flag by accumulating information at the head position of the write data of a write address counter that controls writing of data into the memory using the write data head flag indicating the head of the data; Means for generating a read data head flag which is position information corresponding to the write data head flag in the read side phase by comparing the address relative value of the data head flag with information of a read address counter that controls data reading from the memory. The write data head flag drives a function that generates the read data head flag using the write data head flag, and the write data head flag generates a function that generates the read data head flag based on the read data head flag and input signal abnormality information. and a means for generating data phase information on the reading side based on the read data header flag, incorporating it into the read data, and outputting it.

EXAMPLE Next, a preferred embodiment of the present invention will be explained in detail.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. One embodiment of the present invention is one in which the present invention is applied to the conventional side described above.

Referring to FIG. 1, similar to the above, this embodiment has NN
It uses memory to absorb staff fluctuations and analog jitter for signals used in digital synchronous networks such as I and 5ONET (signals that use pointers as information on the start position of internal data). , shows a function for transferring data and its head position information to the internal phase of the device. Terminal 1 is a signal input terminal from the line side. The memory 3 stores only data excluding management signals such as overhead information from the terminal 1, that is, signals dominated by the intra-frame head position information of predetermined data included in the input signal. A write-at counter 4 and a read address counter 5 respectively control writing of data to the memory 3 and reading of data from the memory 3 in accordance with the input signal phase and the internal phase of the device. The write data phase information detection circuit 6 detects phase information from the input signal from the terminal 1, and the write data head flag generation circuit 7 detects the phase information from the input signal from the terminal 1.
generates a head flag for the data to be written to the memory 3 based on the phase information from the write data phase information detection circuit 6. The address relative value generation circuit 81 for the write data head flag generates information at the head position of the write data of the write address counter 4 that controls data writing to the memory 3 using the write data head flag from the write data head flag generation circuit 7. It accumulates and generates the address relative value of the write data head flag. The read data head flag generation circuit 82 compares the address value of the write data head flag from the address relative value generation circuit 81 with the information from the read address counter 5, and determines whether the value of the read address counter 5 is the address relative of the write data head flag. When the value matches, a read data start flag is generated. The abnormal state detection circuit 83 detects an abnormal state such as input disconnection or loss of synchronization with respect to the input signal from the terminal 1, and outputs an alarm. The read data head flag generation control circuit 84 causes the read data head flag generation circuit 82 to start operating with the write data head flag from the write data head flag generation circuit 7 , while the read data head flag from the read data head flag generation circuit 82 starts its operation. It also has a function of stopping by an alarm signal from the abnormal state detection circuit 83. The read data phase information generation circuit 9 generates phase information of the read data based on the flag from the read data head flag generation circuit 82, and the read data phase information insertion circuit 10 generates read data phase information for the read data from the memory 3. The phase information from the circuit 9 is inserted, and the phase-switched signal is output from the signal output terminal 2 to the next processing step within the device.

As described in detail, according to the present invention, the read data head flag is determined by using the information of the write data head flag and the memory write and read address counters without using memory for the data head flag. By generating this, the hardware scale can be reduced, and the generation function of the read data start flag is controlled using the write data start flag, input signal abnormality information, and previous read data start flag to prohibit generation of unnecessary flags. As a result, it is possible to achieve the effect of enabling accurate processing on the reading side without using any special method when recovering from an abnormal state such as when an alarm is canceled.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing an embodiment of the phase information transfer system according to the present invention, and FIG. 2 is a block diagram of a conventional technique. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Output terminal, 3... Memory, 4... Write address counter, 5... Read address counter, 6... Write data phase information detection circuit, 7...・Write data head flag generation circuit, 8... Read data head flag detection circuit, 9...
- Read data phase information generation circuit, 10...Read data phase information insertion circuit, 81...Address relative value generation circuit for write data head flag, 82...Read data head flag generation circuit, 83...Abnormality state check circuit,

Claims (1)

[Claims] CCITT (International Telegraph and Telephone Consultative Committee) NNI (Ne
workNodeInterface) and Bellc
ore(BellCommunicationsRes.
SONET (Synchronous O
pticalNetworkTransportSys
Regarding digital synchronous networks specified by
In a phase information transfer method that involves data phase switching, data is transferred to the memory using a write data start flag that indicates the start of data on the write side of the memory, which is generated from phase information that represents the start position of data extracted from the input side signal. means for accumulating information at the start position of write data of a write address counter that controls writing and generating an address relative value of a write data start flag;
The address relative value of the write data head flag is compared with the information of a read address counter that controls data reading from the memory, and a read data head flag, which is positional information corresponding to the write data head flag in the read side phase, is determined. a function for generating the read data head flag based on the read data head flag and input signal abnormality information; A phase information transfer method comprising means for stopping until a flag is generated, and means for generating phase information of data on the read side using the read data head flag, incorporating it into the read data and outputting it.