JPS6083451A - Synchronous data buffering system - Google Patents

Abstract

PURPOSE:To simplify a control program and an interface by storing a synchronizing signal which is predetermined in parallel when the head and tail of a message and discriminating the head and tail of the message from the synchronizing signal. CONSTITUTION:Start-stop synchronous data when sent through a communication circuit is converted into a parallel signal, and a parity check on it is made to send only a normal message to the message buffer 9'' of a buffer 9'. When a check circuit 8' makes the parity check, codes indicating the head and tail of a message are detected. When a message is read out by a control program, a synchronizing signal is also read out simultaneously to check on whether it is present or not, thereby discriminating the head and tail of the message.

Description

[Detailed Description of the Invention] +a+ Technical Field of the Invention The present invention provides a data buffering method in which a check circuit checks asynchronous reception data from a communication line and stores only normal data in a data buffer for passing to a control program. The present invention relates to a synchronous data buffering method that can be realized with a simple control program and a simple hardware interface.

(b) Background of the Technology Asynchronous data from a communication line is sometimes sent in a concentrated manner. In this case, if the check circuit checks the data and passes normal data directly to the control program, it is necessary to pass all previous data to the control program before the next data is input to the check circuit. This increases the access load on the control program. For this reason, a data buffering method is used which has a data buffer that stores data for several claims and passes the data stored in the data buffer to a control program.

(C) Prior art and problems Figure 1 is a block diagram of the asynchronous reception data, Figure 2 is a block diagram of the conventional data buffer pulling method, and Figure 3 is the data stored in the buffer in Figure 2. FIG.

In the figure, 1.2.3 are messages, 4 and 5.6 are check codes, F is a code indicating the beginning, F' is a code indicating the end, and 7 is a serial-to-parallel conversion circuit (hereinafter referred to as S/P conversion circuit). , 8 is a check circuit, 9 is a buffer, 10 to 12 are code areas indicating the beginning, 13 to 15 are code areas indicating the number of bytes of each message, and 1' to 3' are message areas.

When asynchronous data as shown in FIG. 1 is sent from the communication line, it is converted into parallel signals by the S/P conversion circuit 7, and the check circuit 8 sends messages 1, 2.3 and check codes 4, 5.6. For example, a parity check is performed and only normal data is sent to the buffer 9, and the buffer 9 stores several frames worth of messages, such as the message 112.3 in FIG. However, when storing it, it is necessary to store it so that each message 1.2.3 can be identified.

For this reason, as shown in Figure 3, the code area 10°1 indicating the beginning
1.12 stores a code indicating the beginning, and code areas 13 to 15 indicating the number of bytes store codes indicating the number of bytes of messages 1 to 30 stored in each message area 1' to 3'. There is. These codes indicating the beginning and the code indicating byte @ are created by the check circuit 8. The code indicating the beginning of the message is an impossible code (1
A W configuration (for example, a code configuration in which several bytes are all "1") is used. For this reason, the check circuit 8 has to create a code that indicates the entire beginning and a code that indicates the number of bytes, which increases the circuit scale and requires the control program to distinguish between these, making both the control program and the hardware interface complex. There is a drawback.

(dl) OBJECT OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide a synchronous data buffering system that can be implemented using a simple 1llf control program and a simple hardware interface.

(e+ Structure of the Invention In order to achieve all of the above objects, the present invention stores only the messages to be passed to the control program in a buffer, and also detects the start and end codes of asynchronous reception data in a check circuit. The main feature is that a predetermined synchronization signal is stored in parallel when the beginning and end of the message are stored, and the beginning and end of the message can be determined by this synchronization signal.

(f) Effect of the invention Embodiments of the present invention will be explained below with reference to the drawings.

FIG. 4 is a block diagram of a synchronous data buffering system according to an embodiment of the present invention, and FIG. 5 is a configuration diagram of data stored in the buffer of FIG. 4.

Components in the figure that have the same functions as those in FIG. 2 are indicated by the same symbols.

8' is a check circuit, 9' is a buffer, 9'' is a first-in, first-out message buffer, 9'' is a first-in, first-out synchronization signal buffer, 1''2//, 3'' is a message area, 1
6.17.1'8 is a synchronization signal area indicating the beginning, 19.2
0°21 indicates the synchronization signal area for ending the signal.

When asynchronous data as shown in FIG. 1 is sent from the communication line, the S/P conversion circuit 7 converts it into a parallel signal, and the check circuit 8' determines whether the data is ・Metssafe 1.2.
3 and check codes 4, 5, and 6, for example, all parity checks are performed and only normal messages are sent to the message buffer 9' in the buffer 9'.When parity check is performed by the check circuit 8', the top and This is done by detecting the signs F and F''e indicating the end. This code F
, By detecting F', the end of message 1.2.3 in FIG. For example, a 1-bit rubel synchronization signal is transferred to the simultaneous r4 synchronization signal buffer 9''. FIG. 5 shows the state in which these are transferred.

That is, the message storage area 1 of the message buffer 9''
", 2", 3" stores messages 1, 2゜3,
Synchronization signal areas 16, 17, 18 indicating the beginning of the synchronization signal buffer 91'' and synchronization signal areas 19, 2 indicating the end in parallel with the start and end messages of message 1.2.3.
“1” is stored in 0.21. Is there a message in the control program? When reading out the message, the start and end points of the message may be detected by reading out the synchronization signal at the same time and checking for the presence or absence of the synchronization signal. It may also be used as an interrupt signal. In this way, the check circuit 8' becomes a simpler circuit than the conventional one, and the control program also becomes simpler.

(g) Effects of the Invention As explained in detail above, the present invention has the advantage that a data buffering system can be realized with a simple control program and a simple software interface.

[Brief explanation of drawings]

Fig. 1 is a block diagram of asynchronous reception data, Fig. 2 is a block diagram of a conventional data buffering method, Fig. 3 is a block diagram of data stored in the buffer of Fig. 2, and Fig. 4 is a block diagram of a conventional data buffering method. FIG. 5 is a block diagram of a synchronous data buffering system according to an embodiment of the present invention, and is a configuration diagram of data stored in the buffer of FIG. 4. In the figure, 1 to 3 are messages, 4 to 6 are check codes, a code indicating the start of F's, F' is a code indicating the end, 7 is a serial/parallel conversion circuit, 8.8' is a check circuit, and 9°9' is a Buffer, 10 to 12 are code areas indicating the beginning, 13 to 5 are code areas indicating the number of bytes of each message, 1' to 3'11''
~3'' is a message area, 16 to 18 are synchronization signal areas indicating the beginning, 19 to 2.1 are synchronization signal areas indicating the end, 9
"" indicates a first-in, first-out message buffer, and 9# indicates a first-in, first-out synchronization signal buffer.

Claims (1)

[Claims] In the data buffering method, in which the 911 step synchronization received data from the communication line is checked by a check circuit and only normal data is stored in the data buffer for passing to the control program, only messages to be passed to the control program are stored in all buffers. In addition, the check circuit creates a message synchronization signal that is accessed at the same time as the start and end points of the message when the control program reads and accesses the message, and stores it in the buffer. A synchronous data buffering method featuring