JPH08249257A - Serial data receiver - Google Patents

Abstract

PURPOSE: To store plural data blocks along with corresponding status data inside a reception FIFO and to read the status data only when an error is generated. CONSTITUTION: A reception error detection circuit 2 detects the reception error information of reception data and outputs the status data, a final data detection circuit 3 monitors whether or not the reception data are final data and the reception FIFO 4 stores the reception data converted into a parallel data form in a serial/parallel conversion circuit 1 and final data flags corresponding to them. A reception status control circuit 5 moves the status data stored after the reception data whose final data flag is '1' to a reception status register 6 and a reception status read requesting circuit 7 requests the read of the status data to a CPU 8 when the status data indicates the generation of a reception error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data receiving apparatus, and more particularly to a serial data receiving apparatus for converting received serial data into parallel data and outputting the parallel data and detecting a reception error.

[0002]

2. Description of the Related Art Conventionally, in this type of serial data receiving apparatus, as shown in FIG. 7, a serial data converting device for converting received data in serial data format into parallel data format is used.
A parallel conversion circuit 1, a reception error detection circuit 2 that detects reception error information from the reception data, and a reception FIFO (first in first out) 21 that stores the reception data converted into the parallel data format by the serial / parallel conversion circuit 1. It consists of and.

Received data received in a serial data format by a receiving circuit (not shown) is converted into a parallel data format by a serial / parallel conversion circuit 1. The reception data converted into the parallel data format is stored in the reception FIFO 21 in the order of reception.

At this time, the reception error detection circuit 2 uses the received data received in the serial data format to abort or CR.
C (Cyclic Redundancy Check)
code) Received error information such as an error is detected, and the received error information is output as status data.

When the reception of one data block (one packet data) is completed, the status data output from the reception error detection circuit 2 following the final data of the data block is stored in the reception FIFO 21.

The received data and status data stored in the reception FIFO 21 are stored in the reception FIFO 21 in the order in which they are stored in the CPU connected to the serial data receiving apparatus.
It is read by a (central processing unit) (not shown). In this method, it is possible to store a plurality of data blocks according to the number of stages of the reception FIFO 21.

In addition to the above method, as shown in FIG.
There is also a method of storing the status data output from the reception error detection circuit 2 in the reception status register 23.
A serial data receiving apparatus according to this method includes a serial / parallel conversion circuit 1 for converting received data in a serial data format into a parallel data format, a reception error detection circuit 2 for detecting reception error information from the received data, and a serial / parallel conversion circuit. It is composed of a reception FIFO 22 for storing the reception data converted into the parallel data format at 1, and a reception status register 23 for storing the status data output from the reception error detection circuit 2.

The received data received by the receiving circuit in the serial data format is converted into the parallel data format by the serial / parallel conversion circuit 1. The reception data converted into the parallel data format is received in the reception FIFO in the order of reception.
It is stored in O22.

At this time, the reception error detection circuit 2 uses the received data received in the serial data format to abort or CR.
Reception error information such as a C error is detected, and the reception error information is output as status data. The status data output from the reception error detection circuit 2 is stored in the reception status register 23 after the reception of one data block is completed.

The reception data stored in the reception FIFO 22 is read by the CPU connected to the serial data receiving device in the order of storage in the reception FIFO 22. The status data stored in the reception status register 23 is read by the CPU after the final data of one data block is read from the reception FIFO 22. In this method, the number of data blocks that can be received is determined by the number of stages of the reception FIFO 22 and the number of stages of the reception status register 23.

All of the above methods are used under the system configuration shown in FIG. In this system configuration, the serial data receiving device 11 includes a serial data transmitting device 12, a CPU 13, a direct memory access controller (DMAC) 14, a RAM (random access memory) 15, and a ROM (read only memory) 16, respectively. It is connected.

The received data converted into the parallel data format by the serial data receiving device 11 is read by the CPU 13 and the direct memory access controller 14 and stored in the RAM 15.

The ROM 16 stores a program for controlling the CPU 13. The CPU 13 executes the program so that the serial data receiving device 1
The reception processing of the reception data and the status data from the reception FIFO 21 and 22 of 1 and the reception status register 23 is controlled.

The second method among the above methods is described in detail in JP-A-63-293657. In the serial communication control device disclosed in this publication, a FIFO-type reception data buffer for temporarily storing reception data and a FIFO for temporarily storing reception status.
An O-type reception status buffer is provided,
The reception data in each buffer and the reception status are associated with each other. This makes it possible to read a plurality of consecutive frames without performing interrupt processing for each frame.

In addition to the above technique, Japanese Patent Laid-Open No. 5-2682
There is a technique disclosed in Japanese Patent No. 71. First in this technology
The first FIFO memory stores the data and the error data, and the second FIFO memory stores the bit indicating the final byte of the data.

As a result, the data next to the data corresponding to the bit indicating the last byte of the second FIFO memory among the data stored in the first FIFO memory can be written in the error register as error data. , The data in the first FIFO memory can be continuously read. In this case, the error data written in the error register may be read before the final byte of the next frame stored in the first FIFO memory is output.

Further, in the above technique, the error bit is stored in the second FIFO memory in addition to the bit indicating the last byte, so that an error occurs only when the error bit indicates that there is an error. It is possible to write data to the error register. In this case, the error data need not be written to the error register unless the error bit indicates that there is an error.

[0018]

In the above-mentioned conventional serial data receiving apparatus, one data block is received F
In the case where the status data is stored in the reception FIFO after the last data of the data block after being stored in the IFO, it is possible to store a plurality of data blocks in the same reception FIFO according to the number of stages of the reception FIFO. However, after reading one data block from the reception FIFO, the status data stored in the reception FIFO must be read after the final data of the data block.

In the method of storing the received data in the reception FIFO and the status data in the reception status register, the status data stored in the reception status register should be read only when a reception error occurs. However, if a plurality of reception status registers are not prepared in advance, the status data in the reception status register may be overwritten when trying to receive a plurality of data blocks. In this case, it is difficult to associate a plurality of data blocks with the status data.

Further, in the case of the technique disclosed in Japanese Patent Application Laid-Open No. 63-293657, a plurality of frames are fetched in the reception data buffer, and a plurality of frames are not required for interrupt processing depending on the reception status. Although it is possible to read a frame, a plurality of reception status buffers are required to store the reception status corresponding to each of a plurality of frames.

Furthermore, in the case of the technique disclosed in Japanese Unexamined Patent Publication No. 5-268271, data and error data are stored in the first FIFO memory, and a bit indicating the last byte of the data is stored in the second FIFO memory. Is stored and the data next to the data corresponding to that bit is written in the error register as error data, so that the data in the first FIFO memory can be continuously read.

However, if the error data written in the error register cannot be read before the final byte of the next frame is output, the error data will be lost.

According to this technique, the error data is stored in the second FIFO memory in addition to the bit indicating the last byte, so that the error data is errored only when the error bit indicates that there is an error. It allows the registers to be written so that the error data need not be written to the error registers unless the error bits indicate an error. However, according to this method, the number of stages of the second FIFO memory is determined in proportion to the number of stages of the first FIFO memory that stores the received data, so when increasing the number of stages of the first FIFO memory, the number of stages of the second FIFO memory is increased. The number of steps must also be increased.

Therefore, an object of the present invention is to solve the above-mentioned problems, to enable a plurality of data blocks to be stored in a reception FIFO together with corresponding status data, and the status data can be read only when an error occurs. It is to provide a data receiving device.

[0025]

A serial data receiving apparatus according to the present invention is a serial data receiving apparatus which converts serial data into parallel data and receives the serial data and detects error information of the serial data. A first-in first-out receiving buffer for temporarily storing the parallel data and the error information; a register for holding the error information; a means for extracting the error information from the data read from the receiving buffer and transferring it to the register; And a means for outputting a read request for the error information held in the register only when the error information held in the register indicates that an error has occurred in the serial data.

[0026]

The received serial data format received data is converted into parallel data format by the serial / parallel conversion circuit and temporarily stored in the receive FIFO.
The status data from the reception error detection circuit is temporarily stored in the IFO.

After this, under the control of the reception status control circuit, the status data is read from the reception FIFO and moved to the reception status register, and is received only when the status data held in the reception status register indicates that an error has occurred in the reception data. From status read request circuit C
Outputs a status data read request to the PU.

Thus, a plurality of data blocks can be stored in the reception FIFO together with the corresponding status data, and the status data can be read only when an error occurs.

Further, although it depends on the number of stages of the reception FIFO, it becomes possible to store a plurality of packet data in the reception FIFO. Therefore, even when the CPU that reads received data from the reception FIFO is busy with other processing, as long as there is a free space in the reception FIFO, it is possible to store a plurality of reception packet data in the reception FIFO and the processing of the CPU can be performed. Receive FIFO when you're not busy
The received data can be read from.

Further, it is possible to store a plurality of packet data in the reception FIFO by one status data register without requiring a plurality of status data registers indicating error information of the received data. Become. In other words, in the method of storing the status data in the register separately from the reception data, when it is desired to receive a plurality of packet data, the same number of reception status registers as the receivable number of packet data must be prepared. A plurality of packet data can be received by the reception status register.

Furthermore, it is not necessary to read the reception status data when no error has occurred in the reception packet data. That is, in the method of storing the reception data and the status data in the same reception FIFO, it is necessary to read the status data from the reception FIFO every time one block of packet data is read from the reception FIFO.

However, the frequency of occurrence of an error in the received data is much lower than that in the case of receiving normal data, that is, the probability that an error occurs in the received data during communication is as low as about 10 ^-7. It is not necessary to read the status data of.

[0033]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a serial data receiving apparatus according to an embodiment of the present invention includes a serial / parallel conversion circuit 1
, Reception error detection circuit 2 and final data detection circuit 3
A reception FIFO 4, a reception status control circuit 5,
It is composed of a reception status register 6 and a reception status read request circuit 7.

The serial-parallel conversion circuit 1 converts received data received in serial data format by a reception circuit (not shown) into parallel data format, and outputs the received data to the final data detection circuit 3 and the reception FIFO 4.

The reception error detection circuit 2 detects reception error information such as an abort or CRC error from the reception data received in the serial data format, and outputs the reception error information as status data.

The final data detection circuit 3 monitors the reception data converted into the parallel data format by the serial / parallel conversion circuit 1, and if the reception data indicates the preset final data, the reception FIFO 4 to that effect is provided. Output to.

The reception FIFO 4 stores in the data section the reception data converted into the parallel data format by the serial / parallel conversion circuit 1 in the order of reception, and based on the output of the final data detection circuit 3, whether the reception data is the final data or not. The bit indicating whether or not it is stored in the final data flag portion (F) corresponding to the received data.

The reception status control circuit 5 is a reception FIFO.
The reception data is read from the data section 4 and the content of the final data flag section corresponding to the reception data is confirmed. If the content is "0", the reception data is requested to be read from the reception FIFO 4.

If the content of the final data flag portion is "1", the reception status control circuit 5 requests reading of the reception data from the reception FIFO 4, and the reception data is the final data of one data block. This is notified to the CPU 8. After that, the reception status control circuit 5 recognizes that the next data of the reception data is the status data, and receives the status data without receiving the data reading request to the CPU 8.
Move from O4 to the reception status register 6.

The reception status read request circuit 7 determines whether or not the status data stored in the reception status register 6 indicates that a reception error has occurred. In this case, if the status data indicates that a reception error has occurred, the reception status read request circuit 7 outputs an interrupt signal to the CPU 8 to request reading of the status data stored in the reception status register 6.

If the status data does not indicate that a reception error has occurred, the reception status read request circuit 7 does not output an interrupt signal to the CPU 8 and the read request for the status data stored in the reception status register 6 is issued. Not performed.

FIG. 2 is a diagram showing the configuration of the reception FIFO 4 of FIG. In the figure, a reception FIFO 4 receives a final data flag unit 4a for storing a bit indicating whether or not the final data is from the final data detection circuit 3 and received data converted by the serial-parallel conversion circuit 1 into a parallel data format. The data part 4b is stored in order.

Final data flag section 4a of the reception FIFO 4
If the received data is not the final data, "0" is stored in, and if the received data is the final data, "1" is stored therein.
When "1" indicating the final data is stored in the final data flag portion 4a, the final data flag portion 4a
"1" is stored in the next data part 4 of the received data
Status data is stored in b.

The operation of the embodiment of the present invention will be described with reference to FIGS. First, received data received from a communication partner in serial data format is converted into parallel format by the serial / parallel conversion circuit 1.

For example, when data represented by bit units of "1" and "0" are continuously input serially, eight pieces of the data are grouped into parallel data (octet data). Since the number of received data is arbitrary in the receiving circuit, a plurality of data in units of octets will be received.

The reception error detection circuit 2 constantly monitors the reception data in the serial data format, and if any error occurs in the reception data, outputs the data indicating the error content. However, the reception error detection circuit 2 outputs the data indicating that the data is normally received, even if the received data has no error.

The final data detection circuit 3 constantly monitors the received data converted into the parallel data format by the serial / parallel conversion circuit 1, and if it does not judge the received data to be the final data of one data block, it outputs "0". When it is determined that the data is the final data of one data block, "1" is output to the reception FIFO 4, respectively.

The reception data converted into the parallel data format by the serial / parallel conversion circuit 1 is output to the reception FIFO 4. Similarly, the output data of the reception error detection circuit 2, that is, the status data is also output to the reception FIFO 4.

The reception data converted into the parallel data format is stored in the reception FIFO 4 in the order of reception, and when the reception of one data block is completed, the status data is input to the reception FIFO 4 following the data block. Therefore, the combination of "a plurality of reception data + status data" is stored in the reception FIFO4.
A plurality of data blocks are accumulated according to the number of stages.

In the reception FIFO 4, a final data flag indicating the end of one data block is added to the octetized received data based on the output data of the final data detection circuit 3. That is, each stage of the reception FIFO 4 is composed of 8-bit reception data and 1-bit final data flag.

The final data flag is "1" only when the final data of one data block is stored in the reception FIFO 4, and is "0" otherwise. When the final data flag is "0", it indicates that the reception data of the reception FIFO 4 is normal reception data.

When the final data flag is "1", it indicates that the reception data of the reception FIFO 4 is the final data of one data block, and that the data following the final data is status data. .

The received data accumulated in the receiving FIFO 4 as described above is read by the CPU 8 connected to the serial data receiving device. When the reception data is sequentially read from the reception FIFO 4 and the final data of one data block is read, the reception status control circuit 5 stores the status data output from the reception FIFO 4 subsequent to the final data in the reception status register 6. Works like.

That is, the reception status control circuit 5 confirms the final data flag of the reception data read from the reception FIFO 4, and when the final data flag is "0", the reception FI
The CPU 8 is requested to read the received data from the FO 4.

When the final data flag is "1", the reception status control circuit 5 requests the CPU 8 to read the reception data from the reception FIFO 4, and the reception data is the final data of one data block. Is notified to the CPU 8.

After this, the reception status control circuit 5 recognizes the data next to this final data as the status data, and automatically receives the status data without requesting the CPU 8 to read the data. To the reception status register 6. After that,
When a plurality of data blocks are stored in the reception FIFO 4, the reception status control circuit 5 reads the next reception data from the reception FIFO 4.

When the status data stored in the reception status register 6 indicates that a reception error has occurred,
The reception status read request circuit 7 issues a read request for the reception status register 6 as an interrupt request to the CPU 8.
When the CPU 8 reads the status data from the reception status register 6, the CPU 8 performs a reception error process according to the content of the status data.

A series of data blocks have been successfully received,
When the status data does not indicate that a reception error has occurred, the reception status read request circuit 7 does not generate an interrupt requesting the CPU 8 to read the reception status data. Therefore, the CPU 8 does not need to read the status data every time, and the load on the CPU 8 is reduced.

For example, when no reception error occurs, it is assumed that the status data values are all "0".
If the value of the status data corresponding to the error content is "1" when any reception error occurs, the reception status read request circuit 7 receives even one "1" bit in the status data. If there is, a status read request is output to the CPU 8 as an interrupt request.

The reception error is a CRC error due to the fact that the CRC data sent by the communication partner for the error check of the reception data does not match the CRC data calculated from the reception data by the serial data receiving device. Abort frame reception error due to interruption of transmission, short packet error when received packet does not reach the specified number of data, fractional bit error when received packet is not an integer multiple of 8 bits (octets), etc. There is.

FIG. 3 is a flow chart showing the operation of one embodiment of the present invention. The series of processing operations will be described with reference to FIG.

The received serial data format received data is converted to parallel data format by the serial / parallel conversion circuit 1 (steps S1 and S2 in FIG. 3), and the received error detection circuit 2 has an error in the serial data format received data. It is checked whether or not (step S3 in FIG. 3).

The reception data converted into the parallel data format by the serial / parallel conversion circuit 1 is written in the reception FIFO 4 (step S4 in FIG. 3), and the final data detection circuit 3
Then, it is judged whether or not it is the final data (step S5 in FIG. 3). The above steps S1 to S5 are repeatedly executed until the final data of one data block is received.

When the final data detection circuit 3 detects the final data, a bit "1" indicating the final data is written in the final data flag portion 4a of the reception FIFO 4 corresponding to the received data.

After the final data is written in the reception FIFO 4, status data, which is the result of error check of the reception data by the reception error detection circuit 2, is received FIFO 4
Is written in (step S6 in FIG. 3).

Next, the CPU 8 sequentially reads the reception data from the reception FIFO 4 up to the final data of one data block (steps S7 and S8 in FIG. 3). In this case, receive F
Whether the received data read from the IFO 4 is the final data can be confirmed by the content of the final data flag. The reception status control circuit 5 confirms whether the reception data read from the reception FIFO 4 is the final data.

After the final data is read from the reception FIFO 4, the reception status control circuit 5 reads the status data from the reception FIFO 4 and receives the reception status register 6.
(Step S9 in FIG. 3). At this time, the reception FI
The reception status control circuit 5 determines whether the data from the FO 4 is reception data or status data.

The reception status read request circuit 7 judges the status data written in the reception status register 6 and judges whether there is a reception error (step S10 in FIG. 3). When the reception status read request circuit 7 determines that there is no reception error, the reception of the data block of one frame is completed.

On the other hand, when the reception status read request circuit 7 determines that there is a reception error, the reception status read request circuit 7 requests the CPU 8 to read the status data. In response to the request, the CPU 8 reads the status data from the reception status register 6 (step S11 in FIG. 3) and performs error processing according to the status data (step S12 in FIG. 3). After that, the reception of the data block of one frame is completed.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, in a serial data receiving apparatus according to another embodiment of the present invention, the reception error detection circuit 2 outputs the status data flag (F) information to the reception FIFO 9, and the reception status control circuit 10 outputs the status data of the reception FIFO 9. The configuration is the same as that of the serial data receiving apparatus according to the embodiment of the present invention shown in FIG. 1, except that it is determined whether the data from the receiving FIFO 9 is received data or status data based on the content of the flag. Therefore, the same components are denoted by the same reference numerals. The operation of the same component is similar to that of the embodiment of the present invention.

The reception status control circuit 10 receives the reception FIF.
When data is read from O9, the contents of the status data flag read simultaneously from the reception FIFO 9 are judged,
If "1" is set in the status data flag, it is determined to be status data and the status data is moved to the reception status register 6.

Thereafter, the reception status control circuit 10 judges the status data written in the reception status register 6, and if there is a reception error, requests the CPU 8 to read the status data.

FIG. 5 is a diagram showing the structure of the reception FIFO 9 of FIG. In the figure, the reception FIFO 9 has a status data flag section 9a for storing a bit indicating whether or not the status data is from the reception error detection circuit 2, and a serial
The parallel conversion circuit 1 includes a data section 9b for storing the received data converted into the parallel data format in the order of reception.

In the status data flag portion 9a of the reception FIFO 9, "0" is stored if the received data is not status data, and "1" is stored if the received data is status data. Status data flag section 9
If "1" indicating that the data is status data is stored in a, "1" is stored in the status data flag portion 9a.
Status data is stored in the data portion 9b in which is stored.

As described above, the received data in the serial data format is converted into the parallel data format by the serial / parallel conversion circuit 1 and temporarily stored in the reception FIFOs 4 and 9, and the reception error is received in the reception FIFOs 4 and 9. The status data from the detection circuit 2 is temporarily stored, and the reception FIFO is controlled under the control of the reception status control circuit 5.
The status data is read from O4, 9 and moved to the reception status register 6, and only when the status data held in the reception status register 6 indicates that an error has occurred in the reception data
By outputting a status data read request to 8, a plurality of data blocks can be stored in the reception FIFO together with the corresponding status data, and the status data can be read only when an error occurs.

Thus, in the present invention, the reception FIFO is
It is possible to store a plurality of packet data in the reception FIFOs 4 and 9, though it depends on the number of stages of 4 and 9. Therefore, even if the CPU 8 that reads the received data from the reception FIFOs 4 and 9 is busy with other processing, it is possible to store a plurality of reception packet data in the reception FIFOs 4 and 9 as long as the reception FIFOs 4 and 9 have a free space. Received when the processing of CPU 8 is not busy
The received data can be read from O4,9.

Further, in the present invention, a plurality of stages of status data registers indicating error information of received data are not required, and a plurality of packet data are accumulated in the reception FIFOs 4 and 9 by one status data register. It is possible to leave. In other words, in the method of storing the status data in the register separately from the reception data, when it is desired to receive a plurality of packet data, the same number of reception status registers as the receivable number of packet data must be prepared. The reception status register 6 can receive a plurality of packet data.

Furthermore, in the present invention, it is not necessary to read the reception status data when no error has occurred in the reception packet data. That is, in the method in which the received data and the status data are stored in the same reception FIFO, the status data is always received in the reception FIFO every time one block of packet data is read from the reception FIFO.
It needs to be read from the FO.

However, since the frequency of occurrence of errors in the received data is much lower than that in the case of receiving normal data, that is, the probability that an error will occur in the received data during communication is as low as about 10 ^-7 , so that it is usually almost normal. It is not necessary to read the status data of.

[0081]

As described above, according to the present invention, the received serial data is converted into parallel data and temporarily stored in the receive buffer of the first in first out format, and the error of the serial data received in this receive buffer is also stored. By temporarily storing information, extracting error information from the data read from the receive buffer, moving it to a register, and outputting a register read request only when the error information held in the register indicates that serial data error has occurred. The advantage is that a plurality of data blocks can be stored in the reception buffer together with the corresponding error information, and the error information can be read only when an error occurs.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a reception FIFO of FIG.

FIG. 3 is a flowchart showing the operation of one embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

5 is a diagram showing a configuration of a reception FIFO of FIG.

FIG. 6 is a block diagram showing a system configuration of a serial data receiving device.

FIG. 7 is a block diagram showing a configuration of a conventional example.

FIG. 8 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 serial-parallel conversion circuit 2 reception error detection circuit 3 final data detection circuit 4, 9 reception FIFO 5, 10 reception status control circuit 6 reception status register 7 reception status read request circuit 8 CPU

Claims (4)

[Claims] 1. A serial data receiving device for converting serial data into parallel data and receiving the parallel data, and detecting error information of the serial data, wherein the parallel data and the error information are temporarily stored in first-in first-out. Format reception buffer, a register for holding the error information, a means for taking out the error information from the data read from the reception buffer and transferring the error information to the register, and the error information held in the register is the serial data. And a means for outputting a read request for reading the error information held in the register only when an error occurs is indicated. 2. The serial receiving apparatus according to claim 1, wherein the receiving buffer is configured to store the error information continuously to the final receiving data of one data block of the serial data. . 3. The receiving buffer is configured to add the information indicating the end of the data block to the last received data of one data block of the serial data and store the data. Or claim 2
The serial data receiving device described. 4. The serial data reception according to claim 1, wherein the reception buffer is configured to store the error information by adding information indicating the error information to the error information. apparatus.