JPS61278238A - Address deciding circuit for transmitter terminal equipment - Google Patents

Abstract

PURPOSE:To attain high speed processing with miniaturization independently of the quantity of decision by providing plural circuits storing a destination address of a received frame at each unit quantity. CONSTITUTION:A station receiving a frame applies serial/parallel conversion converting a frame of a transmission line being a serial data 10 into a parallel data at each unit quantity. A destination address DA in the data converted into the parallel data 12 is transferred into to an address discrimination circuit 14 and stored sequentially alternately to a storage circuit 18 and a storage circuit 19 at each unit quantity converted by a serial/parallel conversion circuit 11. Two storage circuits per unit quantity of the destination address are stored and data are stored alternately, then the holding time of data per one storage circuit is double in comparison with one storage circuit employed. Thus, the decision processing is applied in a double time range, then the decision exceeding the processing time range per unit quantity is processed sufficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an address determination circuit in a transmission system in which a plurality of stations are connected to a transmission path.

[Conventional technology]

BACKGROUND OF THE INVENTION Data transmission systems exist between multiple terminals within a campus or between terminals across multiple campuses.

For example, LAN (local area network)
is one of them. For example, ``Data Communication Handbook'' (Electronic School Yoshin, published October 30, 1980, 1
(See page 21).

An example of a transmission system is shown in FIG. FIG. 3 has three loop-shaped transmission lines 50, 51, and 52, and the loop-shaped transmission line 50 is connected to a computer 50A and terminals 50B and 50G. The computer 50A may also be considered a terminal in a broad sense.

Terminals 51A, 51B were connected to the loop-shaped transmission line 51, and it was coupled to other loop-shaped transmission lines via the terminal 50C. The loop-shaped transmission line 52 has terminals 52A, 52B, 52
A loop-shaped transmission line 50 is connected to C and via a terminal 50B.
combined.

The loop-shaped transmission lines 50, 51, and 52 are called rings.

Data transmission in this transmission system is performed in units of frames, and the data format of one frame is shown in FIG. A delimiter DEL serving as a synchronization code is placed at the beginning and end of one frame, and then a destination address section DA,
Sender address section SA, transmission information, check code F
A CS was established.

In this frame structure, address parts DA and SA each consist of several bytes. The reason why these several bytes are required is that each ring has an address, each station (terminal) address is required within the ring, and the ring is specified by group and the stage is specified by group. , etc.

A specific detailed configuration of the destination address section DA is shown in FIG. DA consists of the following:

0 Station type address IGA that specifies whether the transmitted frame is addressed to a single station or all stations (or whether it is addressed to a single station or a group specification destination that specifies multiple stations) Ring address that specifies the ring to which the partner station belongs Number address LA.

0 Station address STA of the destination station.

Furthermore, as shown in FIG. 6, the LA specifies whether it is a single ring or all rings, and the STA specifies whether it is individual, group, or all stations.

As described above, since there are many types of addresses, each terminal station has a problem with how to efficiently determine addresses.

A conventional address determination procedure will be explained with reference to FIG.

In order to determine whether the destination address DA is addressed to the local station,
DA itself is further divided into DAI, DA2.
..., like DAn. This division is, for example, a basic unit amount for address display, and is divided into one byte, for example.

Each one byte indicates a ring, a station, etc., and also indicates whether it is a group or an individual.

On the other hand, each terminal has a reference address MA for address comparison. This reference address MA indicates the terminal's own address, etc., and is a value unique to the terminal. For this MA, MAL,
MA2. ....

Divide into M A n.

These divided D A 1 to D A n and M A 1 to M
Between A n, DAI and MAL → DA2 and MA2 →
Address comparisons are performed sequentially as follows. Comparison by this division requires a long comparison procedure, and if i is different for each divided subaddress D A i and M A i, the content of the comparison process is not uniform but diverse. have characteristics.

FIG. 8 shows a series of processes for such address determination. In FIG. 8, three determination processes are shown. How to read this diagram is one D
This means that A is divided into three parts, and that different address determination processing is performed for each division unit.

In determination process 1, it is determined whether the ring is 1 individual or a group, whether it is the own ring, whether it is all (a 2 Q 1), and whether it is oats 1zo (au120) or not. In process 2, whether the message is addressed to the user or not. anQl or not, aQQo or not,
In process 3, processing is performed to determine whether or not the packet is addressed to the own station.

That is, in determination processing 1, it is determined whether the received frame is addressed to an individual or a group, and if it is addressed to an individual, whether or not it matches the address of the receiving station itself, or whether it is a broadcast frame, and if it is addressed to a group, it is determined whether the received frame is addressed to an individual or a group. , it is necessary to judge whether the address matches the group address to which the receiving station belongs, but in judgment processes 2 to 4, based on the result of judgment process 1, if it is an individual address, it is necessary to judge whether the address matches the group address to which the receiving station belongs. Comparing and checking whether it is a broadcast frame or not, and if it is addressed to a group, it is only necessary to determine whether it is addressed to the group to which the receiving station belongs, so compared to determination process 1, the determination can be made with less processing and the time required for determination is shorter. Become. FIG. 9 shows the time required for the determination process.

The interval T0T1 is the time required for frame transmission for each unit amount. That is, the frame receiving station receives T. Data for each unit amount will come in at intervals of Ti, and it is necessary to complete the judgment process within the time T, T□, but the judgment process 1
As in, when the amount of processing per unit amount increases, T. If it cannot be determined within the time T1 and the time frame is exceeded (T.

T,). Therefore, when configuring an address determination circuit, it is necessary to buffer the difference in determination time due to the amount of determination as described above and to reduce the size of the circuit.

As a conventional method 1, as shown in FIG. 10, there is a method of providing a storage circuit capable of storing all the destination addresses of received frames in units of units. With this method, the entire destination address can be retained until the next frame is received, so
Although the difference in determination time due to the amount of determination can be buffered, there is a drawback that the amount of circuitry increases as the amount of noise of the destination address DA increases.

Further, as a conventional method 2, as shown in FIG. 11, there is a method in which destination addresses of received frames are successively stored in one storage circuit for each unit amount.

With this method, the address judgment circuit can be made smaller, but it is necessary to perform one judgment process within a certain amount of time. There is a drawback that it cannot be determined in time.

[Purpose of the invention]

An object of the present invention is to provide a station that receives a transmission frame as described above, compares the destination address of the frame with its own address, and determines whether or not the frame is addressed to its own station.
It is an object of the present invention to provide an address determination circuit that is small and capable of processing at high speed regardless of the amount of determination.

[Summary of the invention]

The present invention provides a plurality of circuits for storing the destination address of the received frame in units of units when a station receiving a frame determines whether the frame is addressed to the station itself.
By sequentially storing data, the data retention time for each storage circuit is extended, and the determination time that differs for each unit quantity is buffered. Further, by minimizing the number of memory circuits, the size of the circuit is reduced.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the station receiving apparatus of the present invention.

This station receiving device is individually provided for each station.

The station receiving device includes a serial-to-parallel conversion circuit 11. shift register 1
3. It consists of an address conversion circuit 14.

The address conversion circuit 14 includes a conversion detection circuit 152, a selection circuit 16. Inverter 17B, AND gate 17A, 17
C, flag registers 22, 23. Memory circuits 18, 19.
Comparison circuit 20. Receiving station address setter (register) 21
Consists of.

The station that receives the frame performs serial-to-parallel conversion to convert the frame on the transmission line, which is serial data 1o, into parallel data unit by unit. The data converted into parallel data 12 by the serial/parallel conversion circuit 11 is sent to the shift register 13.
The address is sequentially transferred to the reception buffer, but it is the address that determines whether or not to transfer it to the reception buffer, that is, whether or not the received frame is addressed to the own station, and outputs the transfer permission signal 23 to the reception buffer. This is the determination circuit 14. Of the data converted to parallel data 12, destination address DA is transferred to shift register 13 in the same way.

It is also transferred to the address determination circuit 14. The destination address DA14 transferred to the address determination circuit 14 is converted by the serial-to-parallel conversion circuit 11 for each unit amount converted by the storage circuit 18. The data are sequentially and alternately stored in the memory circuit 19. The memory circuit to be stored is selected by the selection circuit 16 which generates and outputs the memory circuit selection signal 17.

That is, the memory circuit selection signal 17 output from the selection circuit 16
By changing the logical value of D to 1 or O, the destination address D per unit amount is transferred from the serial/parallel conversion circuit 11 to the address determination circuit 14 as parallel data 12.
A14 is distributed to the memory circuit 18 or the memory circuit 19. The logical value of the memory circuit selection signal 17 is changed by:
This is a selection circuit control signal 29 outputted from a comparison circuit 20 that compares the destination address DA for each unit quantity stored in the storage circuit 18 or 19 with the receiving station address 21 storing the address of the receiving station itself. For example, if the memory circuit 18 is selected when the logic value of the memory circuit selection signal 17 is 1, and the memory circuit 19 is selected when the logic value is 0, then the memory circuit selection signal 17 is set to the hourly capacity of the logic value 1. The divided destination address DA14 is stored in the memory circuit 18, and at the same time, a flag register 22 indicating that data has been stored in the memory circuit 18 is set, and a flag set signal 24 indicating that the flag register 22 is set is output to the comparator circuit 20. be done. The comparison circuit 20 detecting the setting of the flag register 22,
The selection circuit control signal 29 instructs the selection circuit 16 to change the logical value of the storage circuit selection signal 7 from 1 to 0.

Further, the flag 22 is cleared using the flag clear signal 30, the data stored in the storage circuit 18 is read, and the data is compared with the data of the receiving station address 21. By changing the logical value of the storage circuit selection signal 17 from 1 to 1 as described above, the next destination address DA divided as described above is
is stored in the memory circuit 19. In this way, the destination address DA is alternately stored in the two memory circuits for each unit amount,
Compare with own station address. As a result of the comparison, if the received frame is addressed to the local station, the comparison circuit 20 outputs a transfer permission signal 23 to the reception buffer. The reason for installing the shift register 13 here is to determine whether or not the received frame is addressed to the local station, and to send a transfer permission signal 23 to the reception buffer.
This is to save time until the frame is output, and to transfer only the frame addressed to the local station to the reception buffer.

By configuring the address determination circuit as described above, two advantages arise. The first advantage is that by installing two memory circuits, the data retention time of each memory circuit can be doubled, which buffers the difference in determination time due to the amount of processing per unit amount of destination address. and that the judgment can be made at a low speed.
The second advantage is the miniaturization of the circuit by minimizing the number of data storage circuits per unit amount of destination address.

First, the buffering of the difference in determination time, which is the first advantage, will be explained. The destination address DA is individual/as shown in Figure 6.
Address IOA indicating group and ring address LA
and a station address SA indicating the station number from which the frame should be received, and the station address SA includes information on an individual station address, a broadcast address, or a group address, as shown in FIG. The linking address LA includes the identification of a single ring or all rings. Further, when performing address determination, as shown in FIG. 7, the destination address is determined from the beginning DAI, DA2, . ... DAn is divided and compared with the receiving station's own address MA, but the amount of processing per divided unit amount differs depending on the information contained in the unit amount.

That is, the above-mentioned DAI includes Ilo indicating whether the received frame is addressed to an individual or a group, and a ring number indicating which ring the received frame is addressed to.

Therefore, when determining the DAI address, first it is determined whether the received frame is addressed to an individual or a group, and then the ring number is determined, as shown in determination process 1 in FIG. If it is recognized that the frame is addressed to an individual frame, then an individual ring number determination is performed to determine whether the frame is addressed to a ring to which the receiving station belongs. After performing individual ring number determination, it is determined whether the received frame is addressed to all rings (a Q Q 1 or and aΩΩ0
) That is, it is determined whether or not it is a broadcast frame. For example, if it is determined by individual ring number determination that the frame is addressed to the ring to which the receiving station belongs, it is necessary to recognize whether the frame is addressed to all rings. Also, even if it is determined by individual ring number determination that the destination is not the ring to which the receiving station belongs.

If the frame is addressed to all rings, the frame must be received. As described above, since there are various judgment conditions in DAI judgment, the judgment time becomes long, and the frame transmission time for each judgment unit amount, that is, T in FIG. 9, increases. An event occurs in which the determination process becomes impossible between -T1 and extends to T2.

On the other hand, in the judgment of DA2, since the judgment as to whether the frame received by DAI is addressed to an individual ring or a group has already been completed, as shown in judgment process 2 in FIG. Since it is only necessary to check whether or not the answer is T, as in determination process 2 in FIG. -T□
Judgment processing becomes possible between In this way, later on,
As shown in determination process 3 in FIG. 8, the determination amount gradually decreases until one determination time falls within the transmission time per frame unit, that is, between T0 and T□.

Here, if two memory circuits are installed per unit amount of destination address as shown in Figure 1, and data is stored alternately, the data retention time per memory circuit will be as shown in Figure 2. This is twice as much as in the case of one memory circuit. Therefore, since the determination process is also performed in twice the time frame, it is possible to sufficiently handle determinations that exceed the processing time frame per unit amount, as in determination process 1 in FIG. 9. Here, T o ” T x , T 1
~T2. T2~TfflT,~T4. ... is the time at which data for each unit amount comes in.

The second advantage will be explained in comparison with FIGS. 10 and 11. As mentioned above, in order to buffer the difference in determination time due to the amount of processing per unit amount of destination addresses, the 10th
As shown in the figure, a method of providing a memory circuit that can store all destination addresses can be considered, but this method is disadvantageous in reducing the size of the circuit because the amount of circuitry increases as the capacity of the destination address increases. On the other hand, if two memory circuits are installed and stored alternately as shown in Figure 1, the size will be approximately 50% smaller than the method of storing all destination addresses, while buffering the difference in determination time as described above. can be converted into

As a modification of the present invention, there is a method of determining the destination address DA and receiving station address MA of received data using software.

〔Effect of the invention〕

According to the present invention, when receiving a frame on a transmission path and comparing and determining the destination address of the frame and the receiving station's own address, it is possible to buffer the difference in processing time per unit amount of determination.

Further, according to the present invention, the address determination circuit can be reduced to about 1/2 of the conventional one.
2. It has the effect of being able to be made smaller.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation,
FIG. 3 is a diagram of the object side of the present invention, FIGS. 4, 5, and 6 are data format diagrams, FIG. 7 is a diagram of the determination processing side, FIG. 8 is a diagram showing the procedure of determination processing, and FIG. The figure shows the relationship between determination processing and time, and FIGS. 10 and 11 are diagrams of conventional examples. 50.51.52...Loop-shaped transmission line, 50A. 50B, 50C, 51A, 51B, 52A. 52B, 52C...terminal, 14...address determination circuit.

Claims (1)

[Claims] 1. A plurality of loop-shaped transmission paths, a terminal that connects each ring-shaped transmission path, a plurality of terminals that are connected to each ring-shaped transmission path, and a loop-shaped transmission path provided in each terminal in units of frames. In a transmission device, the circuit comprises an address determination circuit that determines multiple addresses sent via a frame, and each terminal performs a predetermined process based on the address determination result. first and second memory circuits that alternately distribute the respective addresses of the first and second memory circuits; a comparison circuit that successively compares the distributed addresses in the first and second memory circuits with the addresses of each terminal; 1. An address determination circuit for a transmission device, comprising: means for controlling the incorporation of frame information into a terminal to which it belongs in accordance with a comparison result so as to perform predetermined processing.