JP2511697B2 - Data receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data receiving apparatus capable of receiving data in an HDLC (High Level Data Link Control) format or a format similar thereto.

[Prior Art] The HDLC format is configured, for example, as shown in FIG. This format has one or more start flags, data to be received, and an error check code [FCS (Frame Check Sequence)] for the received data and 1
It consists of one or more closing flags. Here, when two frames of data are continuously received, the start flag of the first frame can also serve as the end flag of the second frame. When receiving such continuous data, the receiving circuit must start preparations for receiving the data of the second frame as soon as it finishes receiving the data of the first frame. Is required. Therefore, in the data receiving method disclosed in Japanese Unexamined Patent Publication (Kokai) No. 58-144402, a data storing section for storing data is arranged in front of the data receiving section, and when the start flag of the first frame is detected, the data is received. The data is stored in the data storage unit, and the received data is immediately transferred to the data receiving unit. However, when the termination flag is detected, the data of the second frame is stored in the data storage unit, but the data transfer to the data reception unit is stopped. On the other hand, the CPU controls the second frame while the second frame of data is stored in the data storage section.
Prepare to receive the frame data. Then, when the preparation for the second frame is completed, the data stored in the data storage unit is transferred to the data reception unit,
CPU handles.

[Problems to be Solved by the Invention] By the way, when an abnormality occurs in a CPU, it must be detected promptly to deal with the abnormality.

Therefore, an object of the present invention is to provide a data receiving device that can easily and quickly detect a CPU abnormality and notify the CPU of the abnormality.

[Means for Solving the Problems] The present invention for achieving the above object will be described with reference to the reference numerals of the drawings showing an embodiment. The receiving unit 1 connected to a data transmission line 1a and the receiving unit. Random number connected to the receiving unit 1 for storing the data received in 1.
An access memory 4, a control unit 3 for controlling data transfer from the receiving unit 1 to the random access memory 4, and a CPU 2 for controlling the entire device and having a function of coping with reception abnormality The received data RXD to be received by the receiver 1 from the data transmission line 1a is a plurality of frames arranged in series, and at least the first frame of the plurality of frames indicates at least the start of the frame. A start flag, one or more bytes of data, and an end flag indicating the end of a frame are included, and at least a frame after the first frame is at least,
The receiving unit 1 includes one or more bytes of data and a termination flag indicating the end of a frame, and the reception unit 1 includes a reception buffer 70, a flag detection means 40, a timing signal generation means 60, a reception end control means 50, and a reception preparation completion command signal generation means. 12, 100, 103, the receiving buffer 70 temporarily stores the data and transfers the data to the random access memory 4, and the data transfer line 1a and the random access memory 4 are provided. And a capacity capable of temporarily storing the plurality of bytes, and the flag detecting means 40 detects the start flag and the end flag of the plurality of frames of the reception data RXD. The timing signal generating means 60 indicates the writing of the data to the reception buffer 70 based on the start flag and the end flag. Is intended to create a reception end timing signal indicating the end of reception of data of one frame based on and the termination flag to form a timing signal, said reception preparation completion instruction signal generating means 12,100,1
Reference numeral 03 denotes a reception preparation completion command signal indicating that preparation for writing the next frame of data in the random access memory 4 is completed based on the write state of data in the random access memory 4. Yes, the reception end control means 50 has a reception end notification signal generation means 180 and reception abnormality determination means 186, 187, and the reception end notification signal generation means 180 is the reception end timing signal and the reception preparation completion command signal. In response to the above, a reception end notification signal INTR is created, and this reception end notification signal INTR is
The signal is sent to the CPU2, and the reception end notification signal INTR is changed from the first voltage state to the second voltage state in which the data transfer is prohibited in synchronization with the reception end timing signal,
The reception end notification signal creating means 180 is formed so as to return from the second voltage state to the first voltage state in response to the reception preparation completion command signal, and the reception abnormality determining means 186, 187 A reception abnormal signal ABINT is created in response to the reception end timing signal and the reception end notification signal INTR, and the reception abnormal signal ABINT is sent to the CPU2, and the reception is performed at the leading edge of the reception end timing signal. In the data receiving device, the reception abnormality determining means 186, 187 is formed so as to generate the reception abnormality signal ABINT indicating reception abnormality when the end notification signal INTR is in the second voltage state. It is related.

[Operation and Effect of the Invention] In the present invention, the timing signal creation means 60 creates the reception end timing signal based on the flag detection by the flag detection means 40, and the random access memory 4
A reception ready instruction signal indicating that the preparation for writing the next data in the random access memory 4 is completed based on the write state of the data, and a reception end timing signal and a reception preparation instruction signal are generated. In response to the reception end notification signal INTR, responding to the reception end notification signal INTR in response to the reception preparation completion command signal to change from the second voltage state to the first voltage state, and receiving at the leading edge of the reception end timing signal. When the end notification signal INTR is in the second voltage state, the reception abnormality signal ABINT indicating abnormality is generated. In the present invention, the reception abnormality signal ABIMT indicating abnormality is generated based on the fact that the reception preparation completion command signal is not obtained even though the writing of the data to the reception buffer 70 is completed. The reception ready command signal is created based on the write state of the random access memory 4, and the write state of the random access memory 4 changes depending on the operation of the CPU2. Contains information indicating whether is normal or abnormal. Therefore, the abnormality of the CPU 2 can be detected easily and quickly.

[Embodiment] Next, a data receiving apparatus according to an embodiment of the present invention will be described with reference to FIGS. 1A to 9.

(Outline of Data Receiving Device) As shown in FIG. 1A, this data receiving device includes an HDLC receiving unit 1, a CPU 2, a DMA control unit 3 and an R, which are connected to each other.
It consists of AM (random access memory) 4. Explaining each unit in detail, the HDLC receiving unit 1 is for receiving high-speed data in a format corresponding to HDLC and storing the received data in a receiving buffer in the HDLC receiving unit 1. CP
U2 is for controlling the entire apparatus, is a microcomputer including a microprocessor, memory, etc., and controls the HDLC receiver 1, the DMA controller 3 and the RAM 4. The DMA control unit 3 DMAs the received data stored in the reception buffer of the HDLC reception unit 1 into a DMA (Direct Memory Acces
s) for controlling to transfer to RAM4 by using a commercially available LSI (NEC μPD71071) or the like. RAM4 is a memory for storing received data. The line 1a connected to the HDLC receiver 1 is the receive data RX
The D is supplied to the receiving unit 1. Received data RXD is
It is accompanied by flags at the beginning and end of each frame as shown in Figure 1B.

The line 1b connected to the receiving unit 1 is the reception clock RXCLK
Is supplied to the receiving unit 1. This receive clock RX
CLK is composed of clock pulses having a predetermined cycle as shown in FIG. 1B, and has a function of determining the reception timing and transmission rate of received data. In addition, 9.6kbps, 19.2kbps, 16kbp
It is possible to set the transmission speed such as s, 64kbps.

The HDLC receiver 1, the CPU 2, the DMA controller 3 and the RAM 4 are connected to each other by a data bus DB, an address bus AB and various control lines. Line 3a transmitting read control signal RD as a control line for interconnection
And a line 3b for transmitting the write control signal WR. Further, the reception unit 1 and the DMA control unit 3 receive a reception request signal (hereinafter, DRQ
Signal 1) and DMA stop signal E
It is connected with line 1d for transmitting ND. A line that transmits the reception end notification signal INTR between the receiver 1 and the CPU 2.
It is connected by 1e and line 1f for transmitting ABINT. The transmission line 2a of the hold confirmation signal HAK derived from the CPU 2 is connected to the DMA controller 3 and the receiver 1. The transmission line 3c of the hold request signal HRQ derived from the DMA control unit 3 is connected to the CPU 2.

The HDLC receiver 1 samples the received data RXD on the line 1a at the falling edge of RXCLK and monitors the start flag at the beginning of one frame. The flag is composed of 8 bits of "01111110" as shown at the top of FIG. 1B, and when this flag is detected, the data following the flag is stored in the receiving buffer in units of 8 bits. When the data is stored in the reception buffer, the DLC signal is output from the HDLC reception unit 1 and the DMA control unit 3 is requested to DMA transfer the reception data. In response to this, D
The MA control unit 3 outputs the HRQ signal to the CPU2, and the CPU2
Request hold. When CPU2 detects this signal, it stops its own operation, and the address bus AB and data bus D
B, line 3a of read signal RD, line 3b of write signal WR
Is released to enter the hold state, and an HAK signal indicating that the hold has been confirmed is output to the DMA control unit 3.

When the HAK signal is output, DMA transfer is started. DMA
The control unit 3 outputs a read control signal RD for reading the data in the reception buffer to the HDLC reception unit 1. HDLC receiver 1
If the HAK signal is “H” and the RD signal is input,
The contents of the receiving buffer are output to the data bus DB in the order of receiving one byte at a signal timing. On the other hand, the DMA controller 3 outputs the address bus AB indicating the memory address for storing the received data in the RAM4 and the write control signal WR indicating the timing of writing to the RAM4, and writes the received data on the data bus DB to the RAM4. .

When there is no more data in the receive buffer, the DRQ signal, HRQ signal and HAK signal are set to "L", whereby the CPU 2 releases the hold state and resumes the operation.

The above operation is repeated until one frame of data is received. The end of reception of one frame is made by detecting a flag (end flag) after receiving data of 1 byte or more. Since the memory address for storing data must be a different value for each byte, the DMA control unit 3
The address to be stored is incremented by 1 each time the byte DMA transfer is completed.

When one frame of data has been received, the HDLC receiver 1 sends a line 1e to notify the CPU 2 of the end of reception.
The INTR signal is output, and the DMA transfer stop signal END is output to the line 1d connected to the DMA control unit 3.

When the CPU2 recognizes the end of reception, one frame of data is stored in the RAM4, so the data is processed, the memory address for receiving the data of the next frame is set, and the DMA control unit 3 is reconfigured. To start. However, when the number of received data of the first frame is large and the start flag of the second frame also serves as the end flag of the first frame, the processing time for the above becomes short and the CPU2 is required to operate at high speed. .

Therefore, in this embodiment, the capacity of the reception buffer is set to a plurality of bytes, and the HDLC reception unit 1 temporarily stores data in this buffer until the CPU 2 can prepare. And
When the CPU2 is ready, the DMA transfer of the second frame data can be resumed. The CPU 2 notifies the HDLC receiving unit 1 as a reception preparation completion instruction by using the address bus AB and the write control signal WR that the second frame is ready, and sets the INTR signal to "L". Therefore, the HDLC receiver 1 prohibits the output of the DRQ signal to temporarily store the data when the INTR signal is “H”, and the DRQ signal when the INTR signal becomes “L”.
Output signal and restart DMA transfer.

When the HDLC receiving unit 1 determines that the CPU2 is not ready to receive the second frame when the second frame has been received, the CPU2 regards it as an abnormality of the CPU2 and sends an ABINT signal (abnormal signal) to the CPU2. . In addition, even if the INTR signal indicates the end of reception but the receive buffer built in the HDLC receiver 1 overflows, the HDLC receiver 1 will not
Send T signal to CPU2. Upon receiving the ABINT notification, the CPU 2 creates a signal for controlling the transmitting side, for example.

FIG. 1B shows the state of each signal in FIG. 1A in principle. FCS
Are included in the received data RXD. Usually n
The -1st byte and the nth byte of data are FCS. This F
CS is for performing error detection using a 16th-order generator polynomial or the like. An erroneous received frame is called an invalid frame and this frame is discarded. In FIG. 1B, the DRQ is intermittently given to the DMA controller 3. DMA controller 3
HRQ is given to CPU2 in response to DRQ. In response to HRQ, the CPU 2 notifies the DMA controller 3 and the HDLC receiver 1 of bus release by HAK. The DMA control unit 3 sends the read control signal RD and the write control signal WR in response to HAK, sets the address bus AB and the data bus DB in the operating state, and DMA-transfers the data of the HDLC receiving unit 1 to the RAM 4. .

(HDLC Receiver) The HDLC receiver 1 of FIG. 1A is configured as shown in FIG. 2A and operates as shown in FIG. 2B. Ie HDLC
The reception unit 1 includes a CPU bus control circuit 10, an 8-bit serial-in / parallel-out shift register (S / P register) 20, an FCS arithmetic circuit 30, a flag detection circuit 40, a reception end control circuit 50, It comprises a reception timing circuit 60, a reception buffer 70, an AND gate 80, and a NOT circuit 90.

The CPU bus control circuit 10 includes an address bus AB, a data bus DB, a read control signal line 3a, and a write control signal line.
3b and HAK signal line 2a are connected respectively. The CPU bus control circuit 10 creates a reception data read signal from the HAK signal and the RD signal and sends it to the line 11. In response to this signal, the reception buffer 70 outputs the reception data on the line 15. The received data on line 15 is output to the data bus DB. The CPU bus control circuit 10 decodes the signal of the address bus AB and the write control signal WR to create a reception preparation completion command signal, which is received via the line 12 to the reception end control circuit 50.
Send to Receive data line 1 to 8-bit S / P register 20
The a and the reception clock line 1b are connected. This S / P
The register 20 samples and stores the reception data RXD at the falling edge of the reception clock RXCLK, and outputs the reception data to the bus 21 in parallel format. The shaded portion in the waveform showing the state of the bus 21 in FIG. 2B is the effective output period of the reception data, and the data must be stored in the reception buffer 70 within this period. The S / P register 30 outputs to the line 22 a serial signal in which the received data RXD is sent in 8 bits.

The FCS arithmetic circuit 30 is a circuit for checking whether or not the received data has a transmission error. An 8-bit delayed reception data line 22 and a reception clock line 1b are connected to the FCS arithmetic circuit 30. The FCS operation circuit 30 has a built-in 16-bit linear feedback shift register, and stores the reception data delayed by 8 bits at the falling edge of the reception clock RXCLK. If there is an error in the received data RXD, a high level “H” is output as an FCS error signal on line 31.
Is output to the reception end control circuit 50.

Flag detection circuit 4 connected to S / P register 20 via bus 21
Reference numeral 0 is a circuit that detects whether or not there is a flag in the received data. When a flag is detected, a high level "H" flag detection signal is output to the line 41 as shown in FIG. 2B.

The receive buffer 70 is a buffer memory that stores received data and is a multi-byte FIFO (first-in first-out type).
It is composed of memory. The parallel-converted received data given on line 21 is written into the buffer at the rising edge of the received-data write signal given by line 62, which is derived from the receiving timing circuit 60, and is transferred at the timing of the received-data read signal on line 11 to the bus. Output to 15. The reception buffer 70 forms a reception buffer status display signal and outputs it to the line 71. The receive buffer status indication signal on line 71 goes high when there is data in receive buffer 70. When the reception buffer clear signal is given from the reception end control circuit 50 to the reception buffer 70 via the line 51, the reception buffer 70 is cleared and the reception data is discarded. When the received data is discarded in this way,
Since the reception buffer 70 becomes empty, the reception buffer status display signal 71 on the line 71 becomes low level "L". Receive buffer
An overrun signal line 72 derived from 70 informs the reception end control circuit 50 whether or not the reception buffer 70 has overflowed, and the overrun signal becomes a high level "H" at the time of overflow.

Receive clock signal line 1b and flag detection signal line
The reception timing circuit 60 to which 41 is connected is composed of a counter and a circuit for decoding the count value, and based on the reception clock signal RXCLK and the flag detection signal, the HDLC
A reception end signal in the receiving section 1 is created and output to the line 61, and at the same time, a reception data write signal is output to the line 62. The reception end signal is given to the reception end control circuit 50 by the line 61. The reception end signal on the line 61 is a signal output at the end of one frame. The receive buffer write signal on line 62 is a signal for writing the receive data in the receive buffer.

The reception end control circuit 50 to which the lines 12, 31, 51, 61 are connected creates a reception end notification signal INTR and outputs it to the line 1e, and also creates an abnormal signal ABINT and outputs it to the line 1f. The DMA stop signal END is created and output to the line 1d. The reception end notification signal INTR is a signal which becomes high level “H” at the rising edge of the reception end signal on the line 61,
Notify CPU2 of the reception end. The reception end notification signal INTR is low level “L” in response to the line 12 ready-to-receive command signal.
become. The DMA stop signal END is output at the rising timing of the reception end signal of the line 61 when the reception end notification signal INTR is at the low level "L", and stops the DMA control unit. The abnormal signal ABINT changes to IN at the time t4 when the reception end signal on the line 61 rises from the low level to the high level.
If the TR signal is still high, it goes high and CPU2
Notify the reception abnormality. If the INTR signal is low level at time t4, the abnormal signal ABINT is
It is also output when there is an FCS error in response to the error signal, and also when there is overrun in the reception buffer 70 in response to the overrun signal on line 72. In FIG. 2B, the rise of the reception end notification signal INTR from the first voltage level (low level) to the second voltage level (high level) of the timing signal of the reception end signal line 61 at the time points t2 and t4. Although the outline is written so as to coincide with the rising edge, the reception end notification signal INTR is formed based on the timing signal on the reception end signal line 61. Slightly behind the rising edge (leading edge) of.

Further, the reception end control circuit 50 creates a reception buffer clear signal, outputs it to the line 51, and gives it to the reception buffer 70. The receive buffer clear signal on this line 51 is
When the reception end signal of 61 rises from a low level to a high level, the INTR signal is at a high level, and the FCS error signal is output at a high level indicating an error or at a high level indicating an overrun of the line 72. .

Receive buffer status display signal line 71 and INTR signal line
When the INTR signal is at the high level "H", the AND gate 80 connected to 1e blocks the receive buffer status display signal on line 71 and outputs the receive request signal DRQ until the receive ready signal is input from CPU2. This is to prevent the output on line 1c.

 Next, each block in FIG. 2A will be described in more detail.

(CPU Bus Control Circuit) As shown in FIG. 3, the CPU bus control circuit 10 includes a decoder 100, an AND gate 101, an 8-bit 3-state buffer 102, and an AND gate 103. The reception ready instruction signal on line 12 is a signal obtained by ANDing the signal obtained by decoding the address bus AB by the decoder 100 and the write control signal WR on line 3b by the AND gate 103. The receive buffer read signal on line 11 is the read control signal RD on line 3a and the line
It is a signal obtained by ANDing the hold confirmation signal HAK of 2a by the AND gate 101. The signal on the data bus DB is a signal obtained by outputting the received data on line 15 from the 8-bit 3-state buffer 120 at the timing of the received data read signal on line 11.

(S / P register circuit) The 8-bit S / P register circuit 20 is an 8-bit S / P register.
In addition to 120, a D flip-flop 121 and a NOT circuit 122 are built in. The register 120 samples and stores the reception data RXD of the line 1a by the reception clock RXCLK, converts it into parallel, and outputs it to the bus 21. Output terminal Q7 of register 120
Is input to the flip-flop 121, the received data with an 8-bit delay can be obtained on the line 22.

(FCS Arithmetic Circuit) As shown in FIG. 5, the FCS arithmetic circuit 30 comprises a 16-bit linear feedback shift register 130, a comparator 131, a comparison pattern generator 132 and a NOT circuit 134. In this FCS operation circuit 30, 8-bit delayed reception data of line 22 is sampled at the falling edge of RXCLK and stored in a 16-bit linear feedback shift register 130 for realizing a 16th-order generator polynomial. The comparator 131 compares the output signal of the line 133 of the register 130 with the comparison pattern obtained from the comparison pattern generator 132 when there is no reception error, and if the comparison result is erroneous, the line 31 Set the FCS error signal to high level “H”.

(Flag Detection Circuit) The flag detection circuit 40 comprises a comparator 140 and a comparison pattern generator 141 as shown in FIG. In the flag detection circuit 40, the comparator 140 compares the received data of the parallel output line 21 and the comparison pattern (“01111110” in this embodiment) generated from the comparison pattern generator 141 bit by bit, and the result is When they match, the flag detection signal on the line 41 is set to the high level “H”.

(Reception Buffer) The reception buffer 70 is, as shown in FIG.
It consists of 0 and a D flip-flop 151. FIFO memory 150
Is composed of ICs such as RCA CD40105. The received data input in parallel from the line 21 is written at the timing of the received data write signal on the line 62. When data is stored in the FIFO memory 150, the receive buffer status display signal on the line 71 becomes high level “H”. The reception data is output to the bus 15 at the timing of the reception buffer read signal on the line 11. The signal on line 152 is the signal output when the buffer is full. The flip-flop 151 is for storing that an overrun has occurred in the reception buffer, and when the reception buffer write signal is input to the line 62 when the signal on the line 152 is full, the flip-flop 151 is overwritten on the line 72. A run signal is output. When the receive buffer clear signal is input to the line 51, the FIFO memory 150 is cleared, the receive buffer 70 becomes empty, and the overrun signal is also cleared.

(Reception Timing Circuit) The reception timing circuit 60 includes a counter 160, a flip-flop 161, a decoder 162, a D flip-flop 163, two AND gates 164 and 165, and a NOT circuit 171, as shown in FIG. 8A. It operates as shown in Figure 8B. That is, the octal counter 160 counts at the rising edge of RXCLK and loads 0 into the counter 160 by the flag detection signal on the line 41. The signal on the output line 166 of the counter 160 is decoded by the decoder 162, and the signal to be output when the count value is 7 is obtained on this output line 167. The signal on the line 167 is re-timed by the flip-flop 163 and sent to the output line 168. Another flip-flop 161
The signal on the output line 169 is a signal indicating the state in which the HDLC receiver 1 is receiving data or the flag. When the signal on this line 169 is at the high level "H", it is in the state of receiving data, and when it is at the low level "L", it is in the state of detecting the flag, that is, the reception of data is suspended. It is in a state. Receive buffer write signal on line 62 It is obtained by outputting the signal on line 168 through AND gate 164 only when the signal on line 169 is high level "H". The reception end signal on line 61 is line 17
It is obtained by outputting the signal on the line 168 through the AND gate 165 only when the signal obtained at 0 is at the high level "H".

(Reception End Control Circuit) As shown in FIG. 9, the reception end control circuit 50 includes five D
Flip-flops 180, 181, 182, 183, 187 and eight AND gates 184, 185, 189, 190, 193, 194, 192, 196
And three OR gates 186, 191, and 195 and one NOT circuit
It consists of 188 and. In this reception end control circuit 50, line 6
The reception end signal of 1 is latched by the flip-flop 180 and IN
Use as TR signal. This signal is cleared by the receive ready command signal on line 12. The flip-flop 181 indicates whether or not there is an FCS error, and latches the FCS error signal on the line 31 at the timing of the reception end signal on the line 61. The output of the flip-flop 183 is a signal indicating the state of overrun of the reception buffer, and the occurrence of overrun is latched by the reception end signal on the line 61. Flip-flop 182 is for temporarily latching the overrun signal on line 72. The overrun signal on line 72 is a signal that is output when data is written to the receive buffer and is canceled by reading the receive buffer.
The overrun state may not be retained until the end of reception. Therefore, the flip-flop 182 holds the overrun state until the end of reception.

The abnormal reception signal ABINT on the line 1f informs the abnormal condition if at least one of the following conditions (a), (b) and (c) is satisfied at the time of rising of the reception end signal on the line 61 from the low level to the high level. High level “H”.

(A) INTR is "H".

(B) INTR is "L" and there is an FCS error (line 197 is "H").

(C) INTR is “L” and overrun (line 19
8 is “H”).

These logics are AND gates 184, 185 and OR gate 18
It is realized by 6 and flip-flop 187.

The DMA transfer stop signal END on the line 1d is DMA when the reception end signal on the line 61 rises from a low level to a high level and at least one of the following conditions (a), (b) and (c) is satisfied. It goes to high level "H", which indicates the transfer is stopped.

(A) INTR is “L”.

(B) INTR is "H" and there is no FCS error (line 199 is "H").

(C) INTR is "H" and overrun (line 20
0 is not "H").

These logics are realized by the AND gates 189, 190, 192, the OR gate 191, and the NOT circuit 188.

The reception buffer clear signal on line 51 is a high level indicating clear when at least one of the following conditions (a) and (b) is satisfied at the time when the reception end signal on line 61 rises from low level to high level. It becomes “H”.

(A) INTR is "H" and there is an FCS error (line 197 is "H").

(B) INTR is “H” and overrun (line
200 is "H").

These logics are implemented in AND gates 193, 194, 196 and OR gate 195.

If the FCS error occurs regardless of whether the INTR signal is low level or high level, the received frame is an invalid frame. If an overrun occurs, it means that the reception is abnormal. Further, that the INTR signal is still at the high level at the time when the reception end signal on the line 61 changes from the low level to the high level should be generated at the time t3 even at the time t4 in FIG. 2B, for example. This means that the line 12 ready-to-receive command signal has not been generated yet. This can be regarded as an abnormality of CPU2. Therefore, in this embodiment, the reception end control circuit 50 of the HDLC receiver 1 is
Sends an ABINT signal (abnormal signal) to CPU2. CPU2 is ABINT
When the signal is received, for example, the data transmitting side is requested to retransmit the data.

 This embodiment has the following effects.

(1) If the INTR signal is at a high level and a signal indicating an FCS error is generated from the FCS calculation circuit 30 at the time when the reception end signal is generated on the line 61, the reception end control circuit 50 receives the signal. A buffer clear signal is given to the reception buffer 70 to clear it. When the INTR signal is at a high level at the time when the reception end signal is generated on the line 61 and the overrun signal indicating the overflow of the reception buffer 70 is generated on the line 72, the reception end control circuit 50 causes the reception buffer clear signal. To occur. As a result, the CPU 2 does not execute useless processing. Therefore, the CPU 2 can be effectively used. In other words, a low-speed CPU can process high-speed data.

(2) CPU2 cannot detect or is difficult to detect
It is possible to detect the abnormality on the HDLC receiving side 1 side and notify the CPU 2 of the abnormality. That is, if the INTR signal is high level at the rising timing of the reception end signal on line 61, the CP
U2 side judges that it is abnormal and notifies CPU2 of this. As a result, the CPU 2 requests the data transmitting side to retransmit the data, etc., and highly reliable data transmission can be achieved.

(3) At the rising edge of the reception end signal on line 61,
The ABINT signal is sent to the CPU 2 when the INTR signal is low and an FCS error is detected or an overrun is detected. As a result, the CPU 2 can quickly deal with the reception abnormality.

(4) The reception buffer 70 is configured to be capable of accumulating a plurality of bytes, and in response to the detection of the flag by the flag detection circuit 40, the reception timing circuit 60 outputs a reception end signal at time t2 in FIG. 2B. The signal is sent out and the reception end notification signal INTR is generated from this time point until the reception ready command signal is generated at the time point t3, and this is given to the CPU2. During the period when the reception end notification signal INTR is generated, DMA transfer is prohibited and the CPU 2 is in operation. During the generation period t2 to t3 of the reception end notification signal INTR in which the DMA transfer is prohibited, even if the received data RXD is input to the HDLC receiver 1, it cannot be DMA-transferred to the RAM4. However, since the receive buffer 70 of the HDLC receiver 1 can store multiple bytes, t2 ~
Receive data RXD for t3 period is stored, and after t3, R
DMA transfer to AM4. As a result, the CPU 2 is not required to perform high-speed processing even when the first frame and the second frame are continuously received. Therefore, it becomes possible to use a low-speed CPU in a system that receives high-speed received data.

[Modification] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(1) In this embodiment, when a transmission error due to FCS or a reception buffer overrun occurs, it is determined that the frame is invalid and the reception end control circuit 50 generates a reception abnormal signal (ABINT) or a reception buffer clear signal. However, this type of invalid frame is only an example, and for example, a flag and a circuit for determining whether the data length surrounded by the flag is less than or equal to a predetermined value are provided, and an invalid frame is indicated when the data length is less than or equal to the predetermined value. A signal (reception buffer clear signal or ABINT signal) may be generated. Further, even if a circuit for determining whether the data length is an integer multiple of 8 bits is provided and a signal indicating an invalid frame (reception buffer clear signal or ABINT signal) is generated when the data length is not an integer multiple of 8, Good.

(2) The flag pattern can be set to “01101000”, for example.

(3) The transmission error detection method may be parity check, sum check, or the like.

(4) The bit length of FCS may be 8 bits.

(5) In the present embodiment, the received data is transferred by the DMA, but if the processing speed of the CPU2 is in time, the CPU2 is not used.
Can also retrieve data directly from the receive buffer. In this case, the reception request signal DRQ is connected to the interrupt terminal of the CPU2.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a block diagram showing in principle the data receiving apparatus of one embodiment of the present invention, FIG. 1B is a waveform diagram showing the state of each part of FIG. 1A, and FIG. 1A is a block diagram showing the HDLC receiver, FIG. 2B is a waveform diagram showing the state of each part of FIG. 2A, FIG. 3 is a circuit diagram showing the CPU bus control circuit of FIG. 2A, and FIG. 4 is 2A. FIG. 5 is a circuit diagram showing the S / P register circuit of FIG. 5, FIG. 5 is a circuit diagram showing the FCS arithmetic circuit of FIG. 2A, FIG. 6 is a circuit diagram showing the flag detection circuit of FIG. 2A, and FIG. FIG. 8A is a circuit diagram showing the receive buffer in FIG. 8, FIG. 8A is a circuit diagram showing the receive timing circuit in FIG. 2A, FIG. 8B is a waveform diagram showing the state of each part in FIG. 8A, and FIG. 9 is reception in FIG. 2A. FIG. 10 is a circuit diagram showing a termination control circuit, and FIG. 10 is a diagram showing a frame structure of received data. 1 ... HDLC receiver, 2 ... CPU, 3 ... DMA controller, 4 ...
… RAM, 30 …… FCS operation circuit, 40 …… Flag detection circuit, 50
...... Reception end control circuit, 60 …… Reception timing circuit, 70
…… Receive buffer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-55-55643 (JP, A) JP-A-62-220048 (JP, A) JP-A-61-234149 (JP, A)

Claims (1)

(57) [Claims] 1. A receiver (1) connected to a data transmission line (1a) and a random access connected to the receiver (1) for storing data received by the receiver (1). A memory (4), a control unit (3) for controlling data transfer from the receiving unit (1) to the random access memory (4), and a function for controlling the entire device and coping with reception abnormality The receiving data (RXD) to be received by the receiving unit (1) from the data transmission line (1a) is obtained by arranging a plurality of frames in series. At least the first frame of
At least a start flag indicating the start of a frame, at least one byte of data, and an end flag indicating the end of the frame are included, and the frames after the first frame have at least one byte of data and the end of the frame. The reception unit (1) includes a reception buffer (70), a flag detection unit (40), a timing signal generation unit (60), a reception end control unit (50), and a reception preparation completion command signal generation unit. (12, 10
0, 103), the reception buffer (70) temporarily stores the data and transfers the data to the random access memory (4), and the data transfer line (1a) and the random access memory (4). A capacity connected to the access memory (4) and capable of temporarily storing the plurality of bytes, and the flag detecting means (40) stores the plurality of frames of the reception data (RXD). The timing signal creating means (60) detects the start flag and the end flag, and forms the timing signal indicating the writing of the data to the reception buffer (70) based on the start flag and the end flag. And creating a reception end timing signal indicating the end of reception of one frame of data based on the end flag. The number creating means (12, 100, 103) is ready to write the data of the next frame in the random access memory (4) based on the write state of the data in the random access memory (4). The reception end control means (50) has a reception end notification signal generation means (180) and a reception abnormality determination means (186, 187), An end communication signal creating means (180) creates a reception end notification signal (INTR) in response to the reception end timing signal and the reception preparation completion command signal, and outputs the reception end notification signal (INTR) to the CPU ( 2), wherein the reception end notification signal (INTR) is changed from the first voltage state to the second voltage state in which the data transfer is prohibited in synchronization with the reception end timing signal, and the reception preparation is performed. Complete Responsive to said second from said voltage state first the reception end acknowledgment signal producing means to return to the voltage state command signal (18
0) is formed, the reception abnormality determination means (186, 187) creates a reception abnormality signal (ABINT) in response to the reception end timing signal and the reception end notification signal (INTR), and receives the reception end signal (ABINT). An abnormal signal (ABINT) is sent to the CPU (2), and the reception indicating the reception abnormality is shown when the reception end notification signal (INTR) is in the second voltage state at the leading edge of the reception end timing signal. A data receiving apparatus, characterized in that the reception abnormality determining means (186, 187) is formed so as to generate an abnormality signal (ABINT).