JP3098056B2 - Cell data transfer method by ATM multiplex transmission - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an ATM (Asynchronous
More specifically, the present invention relates to a cell data transfer method using a buffer circuit configuration using a procedure for writing / reading transmission cell data to / from a buffer circuit.

The ATM multiplex transmission method is a technique in which information is decomposed into fixed-length blocks called cells, and data is transmitted in units of cells only when information occurs. According to this technique, the presence or absence of information is determined, and if no information is generated, the transmission of cell data is stopped, whereby data is efficiently transmitted. Further, since data of several channels is transmitted by ATM multiplexing, if the line capacity is smaller than the number of channels, a buffer circuit for temporarily storing cell data before transferring to the data multiplexing unit is required. .

In the above-described buffer circuit, since the generation timing of the cell data to be written and the cell data read timing of the multiplexing unit are performed asynchronously, a buffer circuit configuration that does not compete with the write operation and the read operation is provided. is necessary.

[0004]

2. Description of the Related Art Conventionally, one cell data in the ATM multiplex transmission is composed of 53 bytes, 5 bytes are used as a header, and 48 bytes are used as a data area. In the audio data, three bytes of 48 bytes in the data area are used as the ADP header.

FIG. 5 shows the configuration of a voice codec that generates ATM cells by encoding voice data, and FIG. 6 shows the operation thereof. Note that in this example, the audio encoding is μ
-Performed by PCM, and the access cycle from the multiplexing unit is shorter than the cell generation time. That is, the cell data generation time is coded sampling 125 μs × data area 45 bytes = 5.625 ms, and the multiplexing unit access cycle is 5.000 ms.
It is assumed that the processing is performed in a cycle of ms.

In FIG. 5 and FIG. 6, input audio data is A / D-converted by an A / D converter 1, subjected to μ-PCM encoding by an encoding processor 2, and processed by a cell generator 3.
Is converted to a cell. Next, for the cellized data, an information bit indicating validity of the cell is generated by the information bit generation unit 4, and the generated information bit is transferred to the buffers 5 and 6 together with the cell data.
The data is alternately written to the buffers 5 and 6 at the timing of the cell write clock generated by. The cell data is read from the buffers 6 and 5 alternately in accordance with the cell read request from the multiplexing unit and transferred to the multiplexing unit.

However, the read cycle is shorter than the write cycle, and cell data is not generated unless information is generated. Using the information bits generated by the generation unit 4, whether it is valid (one cell buffer) or invalid (no buffer cell) is determined, and the result is read and transferred to the clock generation unit 10.

The cell read clock generated by the read clock generator 10 is switched from the buffers 5 to 6 and from the buffers 6 to 5 to read cell data alternately when the validity of the validity decision sections 8 and 9 is valid. . In addition, when the cell data is invalid, the read clock is not switched, so that the process waits until the next cell read request. Executing the above operation has prevented the contention between writing and reading of the buffer circuit.

[0009]

However, in the above-mentioned conventional cell data transfer system, the buffer circuit has a double buffer configuration in order to prevent competition between writing and reading, so that the circuit size becomes large and the cell data transfer method is disadvantageous. There is a disadvantage that it takes a long time to read the data. In addition, there is a disadvantage that write / read errors of the buffer circuit cannot be detected. The present invention has been made in view of the above circumstances, and provides a cell data transfer system capable of reducing the circuit scale of a buffer circuit for storing generated cell data in an ATM multiplex transmission system.

[0010]

SUMMARY OF THE INVENTION The present invention provides an ATM multiplex.
In a cell data transfer method by encrypted transmission, a cell generation unit
And 1 for storing the cell data generated by the cell generation unit.
One buffer circuit and writing to the buffer circuit are completed
Signal to generate a cell write enable signal
Signal generation unit and cell reading for generating a cell reading clock
Output clock generator and the cell data to the buffer circuit.
Information bit that adds information bits to cell data during writing
Packet generation unit, and writes or writes cell data to the buffer.
Comprises an error detection unit for detecting a read error,
The permission signal generation unit transmits the cell write permission signal to a cell.
After transferring to the read clock generator, the cell read clock
A lock generation unit, the multiplexing unit
Arbitration with the incoming cell request signal
A cell read clock is generated and this cell read clock is generated.
Read cell data from the buffer circuit
And the error detector is read from the buffer circuit.
By detecting information bits added to the cell data,
Cell data error is determined.
Cell data transfer method by ATM multiplex transmission
Things. FIG. 1 is a block diagram showing the principle of the present invention. In the figure, the present invention is applied to an ATM multiplex transmission system .
In the cell data transfer method , the buffer circuit 3 for storing the cell data generated by the cell generation unit 1 is composed of one circuit, and the writing / reading procedure is performed by a cell write permission indicating the transfer state of the cell data. A signal is transferred to the cell read clock generator 2, and the cell read clock generator 2 arbitrates between the cell write enable signal and the cell request signal input from the multiplexer, and then generates a cell read clock. cell data forwarding method according to the ATM multiplexing transmission system, characterized in that defined as to read cell data from the buffer circuit 3
Is the law .

That is, the present invention is a cell data transfer system in which a signal indicating that one cell has been generated is sent to the opposite side, and the opposite side reads the cell data after receiving the signal. This method pays attention to the fact that writing / reading of cell data is performed alternately in the buffer circuit 3, that it takes 5.625 ms to generate one cell, and that writing (overwriting) is not performed at the time of reading. It was realized. That is, the present invention is characterized in that the conventional double buffer configuration is reduced to one buffer by arbitrating write and read.

Further, if an information bit is added to the cell data and written to the buffer circuit 3 and the information bit is detected at the time of reading, an error in writing or reading the cell data can be detected. .

[0013]

According to the present invention, after the cell data generated by the cell generator 1 is written into the buffer circuit 3 for one cell, the cell request signal and the cell write enable signal are arbitrated, and then arbitration is performed. The cell data is read out. This eliminates the need for the buffer circuit 3 to have a double buffer configuration as in the related art, thereby reducing the circuit scale.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited by this. FIG. 2 is a block diagram showing one embodiment of the present invention. In FIG. 1, input audio data is converted into cells via an A / D converter 10, an encoding processing unit 11, and a cell generation unit 12 and transferred to a buffer unit 13. The signal generated as the information bit by the information bit generation unit 14 indicates the first byte of the cell, and the information bit is transferred to the buffer unit 13 together with the cell data, and is generated by the cell write clock generation unit 15. The data is written to the buffer unit 13 by the cell write clock.

The cell write enable signal generation unit 16 monitors the cell write clock output from the cell write clock generation unit 15, and after generating 53 write clocks, ie, counting one cell, The write enable signal is set to Low. That is, the cell write enable signal is transferred to the cell read clock generation unit 17 as the end of the cell write. On the other hand, in the cell read clock generation section 17, the cell data read clock is monitored, and after the cell data read is completed, the cell write enable signal is set to High. That is, the cell write enable signal is released.

As described above, the cell read clock generator 17 generates a cell read clock when the cell write enable signal is input and an input cell request is generated from the multiplexer, and transfers the cell data from the buffer 13. Read and transfer to multiplexing unit. See the time chart shown in FIG.

In the error detecting section 18, the buffer section 1
Since a shift register is used for No. 3, the information bit read from the buffer unit 13 is similarly compared with the number of cell read clock generations, and if the information bit is not read for the first time, It is detected that a write / read error has occurred in the buffer unit 13. FIG.
See the time chart shown.

[0018]

As described above, according to the present invention, in the ATM multiplex transmission system, the buffer circuit for storing the generated cell data does not need to have a double buffer configuration, so that the circuit scale is reduced. be able to. Further, an abnormal state of the buffer circuit can be easily detected.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing the principle of the present invention.

FIG. 2 is a configuration diagram showing one embodiment of the present invention.

FIG. 3 is a time chart of the embodiment.

FIG. 4 is a time chart of the embodiment.

FIG. 5 is a configuration diagram of a conventional example.

FIG. 6 is a time chart of a conventional example.

[Explanation of symbols]

 1 cell generation unit 2 cell read clock generation unit 3 buffer unit

Claims (1)

(57) [Claims] 1. A cell data transfer method based on ATM multiplex transmission, wherein a cell generator, one buffer circuit for storing cell data generated by the cell generator, and completion of writing to the buffer circuit are indicated. A permission signal generator for generating a cell write permission signal, a cell read clock generator for generating a cell read clock, an information bit generator for adding information bits to the cell data when writing the cell data to the buffer circuit, An error detection unit that detects an error in writing or reading data to or from the buffer, and after the enable signal generation unit transfers the cell write enable signal to the cell read clock generation unit, the cell read clock generation unit Arbitration between the cell write enable signal and the cell request signal input from the multiplexer A cell read clock is generated by the cell read clock, the cell data is read from the buffer circuit by the cell read clock, and the error detector detects information bits added to the cell data read from the buffer circuit, thereby detecting the cell data. A cell data transfer method using ATM multiplex transmission, which determines the occurrence of an error.