JP3711730B2 - Interface circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interface circuit provided for transferring data between two circuits, and is particularly suitable for transferring data at high speed between circuits operating asynchronously.
[0002]
[Prior art]
Many systems that process digital data proceed with processing while exchanging data between a plurality of circuits. When a circuit for outputting data and a circuit for inputting data operate asynchronously, it is necessary to provide an interface circuit having a buffer for temporarily storing data between the two circuits so as to synchronize.
[0003]
As such an interface circuit, one in which writing to or reading from a buffer is performed in synchronization with a clock used in one circuit is disclosed in Japanese Patent Laid-Open No. 9-222988. This interface circuit is characterized in that the write address designating the buffer write position and the read address designating the read position to the buffer are completely synchronized, and both addresses are synchronized at the clock timing used for synchronization. And the data accumulation degree of the buffer is always detected. Therefore, according to this technique, by constantly monitoring the data accumulation degree, the write operation can be started without waiting for the buffer to become completely empty, and it becomes completely full. The read operation can be started without waiting.
[0004]
[Problems to be solved by the invention]
By the way, in the interface circuit disclosed in Japanese Patent Application Laid-Open No. 9-2222988, in order to completely synchronize the read address and the write address, a certain relationship is required between the clock sclk of the output circuit and the clock mclk of the input circuit. It was said. That is, as described in paragraph No. 0064 of Japanese Patent Laid-Open No. 9-2222988, the cycle of the clock sclk is required to be 1.5 times or more the cycle of the clock mclk. The interface circuit could be configured by the circuit. If the cycle of the clock sclk is less than 1.5 times the cycle of the clock mclk, a high-speed clock needs to be generated by another circuit for synchronization.
Therefore, in the prior art, there is a problem that there is a restriction on the clock period used for two circuits that operate asynchronously, and there is a problem that the circuit configuration becomes complicated if there is no restriction on the clock period. there were.
[0005]
The present invention has been made in view of the above-described circumstances, and provides an interface circuit capable of high-speed data transmission with a simple circuit configuration without any restriction on the clock cycle used for two circuits operating asynchronously. The purpose is to do.
[0006]
[Means for Solving the Problems]
  In order to solve the above-described problem, the present invention is provided between a first circuit synchronized with a first clock signal and a second circuit synchronized with a second clock signal. An interface circuit for transferring data between a circuit and the second circuit, wherein the data supplied from the first circuit is written and the stored data is read and output to the second circuit Storage means for generating, based on the first clock signal, write address generation means for generating a write address indicating a write position of the storage means, and on the basis of the second clock signal, the storage A read address generating means for generating a read address indicating a read position of the means; and the write address and the read address based on the first clock signal and the second clock signal; Timing detection means for detecting the timing to be determined simultaneously, and based on the write address and the read address at the timing detected by the timing detection means, the write operation of the first circuit and the second circuit Control means for controlling reading operationThe stored data number detecting means for detecting the number of stored data in the storage means by comparing the read address and the write address with the predetermined read setting value. A control means having a comparison means and a read control means for controlling a read operation of the second circuit based on a comparison result of the comparison means, wherein the read set value is read from the storage means. The maximum number of data that may be read during a period from the start of data reading to the time when the read control operation for the second circuit is performed based on the read address that has changed, and the control means Is determined in advance based on the maximum number of data that may be read from the time when the second circuit is instructed to stop reading until the second circuit stops the reading operation.It is characterized by that.
  In another aspect of the invention, the first circuit is provided between a first circuit synchronized with a first clock signal and a second circuit synchronized with a second clock signal. Is an interface circuit for transferring data between the first circuit and the second circuit, writing data supplied from the first circuit, reading the stored data, and outputting the data to the second circuit Storage means; Write address generation means for generating a write address indicating a write position of the storage means based on the first clock signal; and Storage means based on the second clock signal The write address and the read address are simultaneously confirmed on the basis of read address generation means for generating a read address indicating the read position of the first clock signal and the second clock signal. Timing detection means for detecting the timing to perform, a write operation of the first circuit and a read operation of the second circuit based on the write address and the read address at the timing detected by the timing detection means And a storage means for detecting the number of stored data in the storage means by comparing the read address and the write address, and a predetermined reading of the number of stored data. Control means comprising: comparing means for comparing with a set value; and writing control means for controlling a writing operation of the first circuit based on a comparison result of the comparing means. The set value is obtained during a period from the start of data writing to the storage means until a write control operation is performed on the first circuit based on the changed write address. The maximum number of data that can be written and the possibility that data will be written after the control means instructs the first circuit to stop writing until the first circuit stops writing operation. It is characterized in that it is predetermined based on a certain maximum number of data.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
A. First embodiment
Hereinafter, a data transmission system using an interface circuit according to an embodiment of the present invention will be described.
1. Configuration of the first embodiment
1-1: Overall configuration
FIG. 1 is a circuit diagram of a data transmission system using an interface circuit according to an embodiment of the present invention. In the figure, 10 is a first circuit that operates in synchronization with the first clock signal 100, 11 is a second circuit that operates in synchronization with the second clock signal 101, and an interface between these circuits. A circuit 1 is provided. In this example, data is transferred from the first circuit 10 to the second circuit 11. The period of the first clock signal 100 and the second clock signal 101 is arbitrary, but in this example, the period of the first clock signal 100 is the period of the second clock signal 101 in order to facilitate understanding. Longer than that.
[0008]
The first circuit 10 is supplied with a write request signal 114. During the valid period of the write request signal 114 (for example, during a low level period), the first circuit 10 The write data 102 and the write enable signal 103 are output in synchronization with one clock signal 100. On the other hand, the read permission signal 112 is supplied to the second circuit 11, and during the effective period of the read permission signal 112 (for example, during the low level period), the second circuit 11 The read enable signal 103 is output in synchronization with the second clock signal 101 and the read data 106 is captured.
[0009]
Next, the interface circuit 1 includes a buffer 12, a write signal generator 13, a WR address counter 14, a read signal generator 15, an RD address counter 16, an address comparison timing generation circuit 17, and an address comparison circuit 19. .
[0010]
First, the buffer 12 is configured by, for example, a 2-port RAM so that writing and reading can be performed simultaneously. Write data 102 from the first circuit 10 is written into the buffer 12, and this is read as read data 106 at a predetermined timing and supplied to the second circuit 11.
[0011]
Next, the write signal generator 13 generates a write signal 104 based on the first clock signal 100 and the write enable signal 103. The write signal generator 13 is composed of, for example, an OR circuit, and the logical sum of the first clock signal 100 and the write enable signal 103 is output as the write signal 104. The write signal 104 acts as a clock for writing the write data 102 to the buffer 12.
[0012]
Next, the WR address counter 14 outputs the count value as the write address 105. A write enable signal 103 is supplied to the enable input terminal of the WR address counter 14, and the first clock signal 100 is supplied to the clock input terminal. Therefore, when the write enable signal 103 is valid, the write address 105 is incremented in synchronization with the first clock signal 100.
[0013]
Next, the read signal generator 15 generates a read signal 108 based on the second clock signal 101 and the read enable signal 107. Like the write signal generator 13, the read signal generator 15 is configured by, for example, an OR circuit. The read signal 108 acts as a clock for reading the read data 106 from the buffer 12.
[0014]
Next, the RD address counter 16 outputs the count value as the read address 109. In the RD address counter 16, the read address 109 is incremented in synchronization with the second clock signal 101 when the read enable signal 107 is valid.
[0015]
Next, the address comparison timing generation circuit 17 generates first and second comparison timing signals 110 and 111 based on the first clock signal 100. The address comparison timing generation circuit 17 is constituted by, for example, a toggle circuit that divides the first clock signal 100, and the toggle signal and an inverted signal thereof are output as the first and second comparison timing signals 110 and 111. It has come to be.
[0016]
Next, the address comparison circuit 19 compares the write address 105 with the read address 109 and generates a write enable signal 113 and a read enable signal 112 in synchronization with the second clock signal 101 based on the comparison result. Is configured to do. The write permission signal 113 permits the write data 102 to be written to the buffer 12 when the value is low level. Further, the read permission signal 112 permits the read data 106 to be read from the buffer 12 when the value thereof is at a low level.
[0017]
Next, the write REQ generation circuit 18 generates a write request signal 114 in which the write permission signal 113 is synchronized with the first clock signal 100. The write REQ generation circuit 18 is configured by, for example, a D flip-flop.
[0018]
1-2: Configuration of the address comparison circuit
Next, a specific configuration of the address comparison circuit 19 will be described. FIG. 2 is a circuit diagram of the address comparison circuit. As shown in this figure, the address comparison circuit 19 includes an A register 21, a comparison circuit 22, a flip-flop 23, a B register 24, and a C register 25, and the number of data stored in the buffer 12 is thereby reduced. The read permission signal 112 and the write permission signal 113 are generated based on the detection result.
[0019]
First, the A register 21 generates an A address 200 based on the write address 105, the first comparison timing signal 110, and the first clock signal 100. Specifically, when the first comparison timing signal 110 is valid (high level in this example), the write address 105 is latched at the rising edge of the first clock signal 100, and the A address 200 is generated. The In this case, since the first comparison timing signal 110 is given as a toggle signal obtained by dividing the first clock signal 100 as described above, the A address 200 is obtained by propagating the write address every two clocks. Become.
[0020]
Next, the comparison circuit 22 detects the number of data stored in the buffer 12 based on the read address 109 and the A address 200, and compares it with a predetermined value to determine the first and first values. Two comparison results 201 and 202 are generated. The first comparison result 201 indicates whether data can be read from the buffer 12, and the second comparison result 202 indicates whether data can be written to the buffer 12. The comparison method will be described later.
[0021]
Next, the flip-flop 23 latches the second comparison timing signal 111 with the second clock signal 101, so that the second comparison timing signal 111 synchronized with the first clock signal 100 is A third comparison timing signal 203 is generated in synchronization with the clock signal 101.
[0022]
Next, when the first comparison result 201 and the third comparison timing signal 203 are supplied to the B register 24 and the third comparison timing signal 203 is valid (high level in this example), the second clock The first comparison result 201 is read at the rising edge of the signal 101 to generate the read permission signal 112.
[0023]
Next, when the second comparison result 202 and the third comparison timing signal 203 are supplied to the C register 25 and the third comparison timing signal 203 is valid (high level in this example), the second clock is output. The second comparison result 202 is read at the rising edge of the signal 101 to generate the write permission signal 113.
[0024]
2. Operation of the first embodiment
Next, the operation of the data transmission system of the first embodiment will be described with reference to the drawings.
2-1; Write operation
FIG. 3 is a timing chart showing an example of timing when the write data 102 is written from the first circuit 10 to the buffer 12. If the write request signal 114 shown in FIG. 3B is supplied to the first circuit 10 in synchronization with the first clock signal 100 shown in FIG. 3A, the first circuit 10 Data is written in a period during which the write request signal 114 is valid (in this example, a low level period).
For example, if the write data D1 to D4 and D5 to D7 shown in FIG. 3D are written in the buffer 12, the first circuit 10 generates the write enable signal 103 shown in FIG. The write enable signal 103 is valid at a low level.
[0025]
When the write enable signal 103 is supplied to the write signal generator 13, the write signal generator 13 generates the write signal 104 shown in FIG. 3E based on the write enable signal 103 and the first clock signal 100. Generate. When the write enable signal 103 is supplied to the WR address counter 14, the WR address counter 14 counts at the rising edge of the first clock signal 100 when the write enable signal 103 is valid (at the low level). And is generated as a write address 105 shown in FIG.
[0026]
As shown in FIG. 3F, when the write address 105 changes as “1 → 2 → 3 → 4 → 5 → 6 → 7”, the write data D1 is a storage area corresponding to the address value “1”, the write data D2 is sequentially stored such as a storage area corresponding to the address value “2”. In this way, four consecutive write data D1 to D4 are written, and thereafter three consecutive write data D5 to D7 are written.
As described above, data writing to the buffer 12 can be performed by a burst write operation, so that high-speed data transfer can be supported.
[0027]
2-2: Read operation
Next, FIG. 4 is a timing chart showing an example of timing at which the second circuit 11 reads the read data 106 from the buffer 12. If the read permission signal 112 shown in FIG. 4B is supplied to the second circuit 11 in synchronization with the second clock signal 101 shown in FIG. 4A, the second circuit 11 Data is read in a period during which the signal 112 is valid (in this example, a low level period).
[0028]
For example, assuming that the second circuit 11 outputs the read enable signal 107 shown in FIG. 3C, the read signal generator 15 generates the read enable signal 107 based on the read enable signal 107 and the second clock signal 101 in FIG. The read signal 108 shown in d) is generated.
[0029]
When the read enable signal 107 is supplied to the RD address counter 16, the RD address counter 16 increments the count value at the rising edge of the second clock signal 101 when the read enable signal 107 is at a low level. This is generated as a read address 109 shown in FIG.
[0030]
The read address 109 changes from “0 → 2 →... → 9” as shown in FIG. 4F, and the data stored in the storage area of the buffer 12 corresponding to each address is D0 to D9, respectively. Then, as shown in FIG. 4E, first, the data D0 to D4 are continuously read, and then the data D5 to D8 are read.
As described above, data reading from the buffer 12 can be performed by a burst read operation, so that high-speed data transfer can be supported.
[0031]
2-3: Address comparison operation
Next, FIG. 5 is a timing chart showing an example of operation timing of address comparison. First, the address comparison timing generation circuit 17 divides the first clock signal 100 shown in FIG. 5A to divide the first and second comparison timing signals 110 and 111 (FIGS. 5C and 5E). Reference) is generated and output to the address comparison circuit 19. In the A register 21 of the address comparison circuit 19, when the first comparison timing signal 110 is valid (in this example, at a high level), the write address 105 (FIG. 5B) at the rising edge of the first clock signal 100. )) Is latched to generate an A address 200. Therefore, the A address 200 is obtained by updating the write address 105 at a rate of once every two clocks as shown in FIG. 5D, and the value is “6 → 7 → 9 → A → B”. To change.
[0032]
On the other hand, when the second comparison timing signal 111 is supplied to the flip-flop 23, the flip-flop 23 latches the second comparison timing signal 111 at the rising edge of the second clock signal 101 shown in FIG. Then, the third comparison timing signal 203 shown in FIG. As a result, the second comparison timing signal 111 is synchronized with the second clock signal 101.
[0033]
Next, when the read address 109 and the A address 200 shown in FIG. 5 (h) are supplied to the comparison circuit 22, the comparison circuit 22 compares the two addresses with a predetermined set value and performs a first comparison. A result 201 and a second comparison result 202 are generated.
Here, an example of a method for obtaining the comparison result will be described. For example, it is assumed that the storage capacity of the buffer 12 is 32 words and each storage area can be specified by a 5-bit address. The WR address counter 14 and the RD address counter 16 are both 6-bit counters, and the lower 5 bits of the count value are supplied to the buffer 12. The address comparison circuit 19 has a 6-bit write address 105 and a read address 109. , And a 6-bit read address 109 and an A address 200 are input to the comparison circuit 22.
[0034]
First, the comparison circuit 22 obtains a difference value between the A address 200 and the read address 109 in order to detect the number of data accumulated in the buffer 12. By the way, since the buffer 12 is composed of a cyclic memory, the value of the read address 109 may exceed the value of the A address 200. Therefore, the number of accumulated data is detected under the following conditions.
(1) When A address ≥ Read address
In this case, since the write address (A address) precedes, the number of accumulated data is given by the following equation.
Number of stored data = A address-read address
(2) When A address <read address
In this case, since the read address precedes, it is necessary to calculate the number of data in consideration of the storage capacity of the buffer 12. For this reason, the number of data is given by the following equation.
Number of stored data = (A address + 64) −read address
When the number of accumulated data calculated in this way is “0”, the buffer 12 is in an empty state, and when the number of accumulated data is “32”, the buffer 12 is in a full state.
[0035]
The first comparison result 201 is generated by comparing the number of accumulated data with a predetermined read setting value. When the accumulated data number is equal to or larger than the read setting value, the first comparison result 201 is “0”, and the accumulated data number is read. When it is less than the set value, it is “1”.
The read setting value is a value provided so that the second circuit 11 does not validate the read enable signal 107 when the buffer 12 is empty, and the number of data that can read the read data 106 normally. Set to Specifically, a delay until the read permission signal 112 is reached through address comparison after the end of one read operation, from when the read permission signal 112 becomes invalid until the second circuit 11 stops the read operation. And the read operation timing specification of the second circuit 11 are taken into consideration, and the maximum number of words read during these delays is determined.
[0036]
In this example, the delay to reach the read permission signal 112 after the end of the read operation is 3 clocks (second clock signal 101) at the maximum. Here, there is no delay until the second circuit 11 stops the read operation after the read permission signal 112 becomes invalid, and the second circuit 11 may read in every cycle. The lead setting value may be “3”. If the second circuit 11 reads at a rate of once every two cycles, the read setting value may be “2”. FIG. 6 shows a truth table when the read set value is “3”. In this case, if the number of accumulated data is 3 or more, that is, if data of 3 words or more remains in the buffer 12, the first comparison result 201 is '0', and if it is 2 words or less, it is '1'. .
[0037]
Next, the second comparison result 202 is generated by comparing the number of accumulated data with a predetermined write setting value, and becomes “1” when the accumulated data number is equal to or larger than the write setting value. When the number is less than the write set value, it becomes “0”.
The write setting value is a value provided so that the first circuit 11 does not validate the write enable signal 103 when the buffer 12 is full, and is set to the number of data that can normally write the write data 102. The Specifically, 1) after one write operation is completed, a write permission signal 113 is generated through address comparison, and the write REQ generation circuit 18 synchronizes the write permission signal 113 with the first clock signal 100. 2) Delay until the write request signal 114 is generated 2) Delay until the first circuit 10 stops the write operation after the write request signal 114 becomes invalid 3) Write operation of the first circuit 10 The timing specification is taken into consideration based on the maximum number of words written during these delays.
[0038]
In this example, there is a delay of up to 2 clocks (first clock signal 100) until the write address 105 is propagated to the A address 200 after the write operation is completed, and the comparison result between the A address 200 and the read address 109 is written. When the delay until propagation to the write enable signal 113 is converted with respect to the first clock signal 100, there is a delay of less than 3 clocks at the maximum. There is a one clock delay when synchronizing to the first clock signal 100 via. Further, in the first circuit 10, if the delay from when the write request signal 114 becomes invalid until the write operation is stopped is 1 clock, the total of these delays is 6 clocks. Although the maximum value of the number of words written to the buffer 12 during 6 clocks depends on the timing specification of the write operation of the first circuit 10, it is assumed here that there is a possibility of writing in all 6 clocks.
[0039]
Further, in the first circuit 10, a burst write operation for continuously writing a plurality of words (4 words in the example of FIG. 3) is performed. If the burst write operation is started at the same time as the write request signal 114 becomes invalid, four more words are written in the burst cycle. For this reason, after the write operation corresponding to the comparison address is performed, a maximum of 10 words may be written. Therefore, the write setting value is set to a value “22” obtained by subtracting “10” from “32” which is the data capacity of the buffer 12. A truth table when the light set value is “22” is shown in FIG. In this case, if the number of accumulated data is 22 or more, that is, if data of 22 words or more remains in the buffer 12, the second comparison result 202 is “1”, and if it is 21 words or less, it is “0”. .
[0040]
In this way, the first comparison result 201 and the second comparison result 202 are generated based on the read address 109 and the A address 200, and the first and second clocks that serve as the time reference for both addresses. Since the signals 100 and 101 are not synchronized, there is a timing at which the comparison result becomes unstable.
[0041]
For example, as shown in FIG. 5I, the first comparison result 201 takes an unstable value at the shaded portion. The same applies to the second comparison result 202. For this reason, the B register 24 and the C register 25 are connected to the first and second clocks at the rising edge of the second clock signal 101 during the period in which the third comparison timing signal 203 shown in FIG. The comparison results 201 and 202 are respectively latched to generate the read permission signal 112 and the write permission signal 113, respectively.
[0042]
In the example shown in FIG. 5, the first comparison result 201 shown in FIG. 5 (i) is read from the B register 24 at each timing indicated by the dotted line (timing when the address is determined). The read permission signal 112 shown in (j) is output to the second circuit 11.
[0043]
As described above, according to the first embodiment, there is no period limitation between the first clock signal 100 and the second clock signal 101, and the first circuit 10 is stable with a simple configuration. The write request signal 114 can be sent in synchronization with the first clock signal 100. In addition, a stable read permission signal 112 can be sent to the second circuit 11 in synchronization with the second clock signal 101.
[0044]
In addition, burst write operation and burst read operation can be performed on the buffer 12, and by appropriately monitoring the number of data stored in the buffer 12, it is possible to write without waiting for the buffer to become completely empty. The read operation can be started without waiting for it to become completely full. As a result, high-speed data transfer between the first and second circuits 10 and 11 can be realized.
[0045]
B. Second embodiment
Next, a data transmission system using an interface circuit according to the second embodiment of the present invention will be described. This data transmission system is different from the first embodiment in that data is transmitted from the second circuit 11 to the first circuit 10.
[0046]
FIG. 8 is a circuit diagram of a data transmission system using an interface circuit according to the second embodiment. In addition, the same code | symbol is attached | subjected to the component same as FIG. The read signal generator 63, RD address counter 64, write signal generator 65, and WR address counter 66 shown in FIG. 8 are the same as the read signal generator 15, RD address counter 16, and write signal generator 13 shown in FIG. , And the WR address counter 14, and is different only in whether it is provided on the second circuit 11 side or on the first circuit 10.
[0047]
In FIG. 8, an interface circuit 2 is provided between the first circuit 10 that operates in synchronization with the first clock signal 100 and the second circuit 11 that operates in synchronization with the second clock signal 101. It has been. In this example, it is assumed that the cycle of the first clock signal 100 is longer than the cycle of the second clock signal 101 as in the first embodiment.
[0048]
First, when the read enable signal 603 from the first circuit 10 is input to the read signal generator 63, the read signal generator 63 outputs the read signal 604 when the read enable signal 603 is valid. The RD address counter 64 increments the read address 605 using the first clock signal 100 when the read enable signal 603 is valid. When the read signal 604 is input to the buffer 12, the read data 602 is read from the position indicated by the read address 605 and output.
[0049]
Next, when the write enable signal 607 from the second circuit 11 is input to the write signal generator 65, the write signal generator 65 outputs the write signal 608 when the write enable signal 607 is valid. The WR address counter 66 increments the write address 609 using the second clock signal 101 when the write enable signal 607 is valid. When the write signal 608 is input to the buffer 12, the write data 606 is written at the position indicated by the write address 609.
[0050]
Next, the address comparison timing generation circuit 17 outputs the first comparison timing generation signal 110 and the second comparison timing generation signal 111 in synchronization with the first clock signal 100. The address comparison circuit 19 compares the read address 605 and the write address 609 and outputs the write permission signal 612 and the read permission signal 613 in synchronization with the second clock signal 101.
[0051]
Next, the read REQ generation circuit 68 latches the read permission signal 613 with the first clock signal 100 and generates a read request signal 614 that is synchronized with the first clock signal 100.
[0052]
A circuit diagram of the address comparison circuit 19 is shown in FIG. When the read address 605, the first comparison timing signal 110, and the first clock signal 100 are supplied to the A register 21, the A register 21 detects when the first comparison timing signal 110 is valid (in this example, , The read address 605 is latched at the rising edge of the first clock signal 100 to generate the A address 200. In this case, the first comparison timing signal 110 is given as a toggle signal obtained by dividing the first clock signal 100. Therefore, the A address 200 is obtained by propagating the read address 605 every two clocks.
[0053]
Next, the comparison circuit 22 detects the number of data stored in the buffer 12 based on the write address 609 and the A address 200, and compares this with a predetermined value, thereby determining the first and first values. Two comparison results 201 and 202 are generated. The first comparison result 201 indicates whether data can be written to the buffer 12, and the second comparison result 202 indicates whether data can be read from the buffer 12. The comparison method is the same as that of the first embodiment described above. The read address 109 of the first embodiment is set to the A address 200 of the second embodiment, and the A address 200 of the first embodiment is set to the second embodiment. The write address 609 may be replaced.
[0054]
Next, the flip-flop 23 latches the second comparison timing signal 111 with the second clock signal 101, so that the second comparison timing signal 111 synchronized with the first clock signal 100 is A third comparison timing signal 203 is generated in synchronization with the clock signal 101.
[0055]
Incidentally, since the A address 200 and the write address 609 are synchronized with the first and second clock signals 100 and 101, respectively, the first and second comparison results 201 and 202 are similar to the first embodiment. There is an unstable timing. For this reason, a B register 24 and a C register 25 are provided to obtain a comparison result at a timing when the values of both addresses are stable. The B register 24 is supplied with the first comparison result 201 and the third comparison timing signal 203, and when the third comparison timing signal 203 is valid (high level in this example), the second clock signal 101 The first comparison result 201 is propagated at the rising edge, and the write permission signal 612 is generated. On the other hand, when the second comparison result 202 and the third comparison timing signal 203 are supplied to the C register 25 and the third comparison timing signal 203 is valid (high level in this example), the second clock signal The second comparison result 202 is propagated at the rising edge of 101 to generate the read permission signal 613. Thereby, the write permission signal 612 and the read permission signal 613 can be stabilized.
[0056]
As described above, according to the second embodiment, there is no period limitation between the first clock signal 100 and the second clock signal 101, and the first circuit 10 is stable with a simple configuration. The read request signal 614 can be sent in synchronization with the first clock signal 100. In addition, a stable write permission signal 612 can be sent to the second circuit 11 in synchronization with the second clock signal 101.
[0057]
In addition, burst write operation and burst read operation can be performed on the buffer 12, and by appropriately monitoring the number of data stored in the buffer 12, it is possible to write without waiting for the buffer to become completely empty. The read operation can be started without waiting for it to become completely full. As a result, high-speed data transfer between the first and second circuits 10 and 11 can be realized.
[0058]
C. Modified example
The embodiment according to the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various modifications described below are possible.
(1) In each of the embodiments described above, both the first comparison timing signal 110 and the second comparison timing signal 111 are not necessarily required from the address comparison timing generation circuit 17. Since these signals are only inverted from each other, one signal can have both implications by reversing either effective level.
[0059]
(2) The interface circuits 1 and 2 of each embodiment described above can be used in a computer system. FIG. 10 is a block diagram of a computer system using the interface circuits 1 and 2. In the figure, a first circuit 10 exchanges data D with a CPU via a PCI bus. Data transmission in this case may be executed using a burst transfer mode of the PCI bus. The interface circuits 1 and 2 described above are provided between the first circuit 10 and the second circuit 11, and data processing is performed between the first and second circuits 10 and 11 operating asynchronously. It has come to be. In this case, since the interface circuits 1 and 2 can perform data transfer at high speed, it is possible to construct a computer system with high processing capability.
[0060]
(3) In each of the above-described embodiments, the timing at which the write address 105 and the read address 109 are simultaneously determined in the address comparison circuit 19 among the first comparison result 201 and the second comparison result 202 (in FIG. 5). The comparison result in (dotted line timing) is extracted by the B register 24 and the C register 25.
In this case, the timing determined simultaneously is the third comparison timing signal 203 obtained by synchronizing the second comparison timing signal 111 generated based on the first clock signal 100 with the second clock signal 101, and the second comparison timing signal 203. However, the timing may be generated by another method. That is, when the write address 105 is synchronized with the first clock signal 100 and the read address 109 is synchronized with the second clock signal 101 as in the above-described embodiment, the change timings of both addresses are the first and first. Since it depends on the second clock signal 100, 101, the timing at which the write address 105 and the read address 109 are simultaneously determined may be detected based on the first and second clock signals 100, 101.
[0061]
(4) Further, the comparison circuit 22 of each of the embodiments described above compares the read address 109 with the write address 105 (A address 200), detects the number of stored data, and stores the number of stored data and the read. You may grasp | ascertain as a 1st comparison means which compares a setting value, and a 2nd comparison means which compares the number of accumulation | storage data, and a write setting value. The B register 24 synchronizes the comparison result of the first comparison means with the second clock signal 101, and the C register 25 synchronizes the comparison result of the second comparison means with the first clock signal 100. Of course, it is possible to grasp each as a means to make it.
Further, the accumulated data number detecting means may detect the accumulated data number only at the timing when the address is determined simultaneously. Further, the first and second comparison means may perform the comparison operation only at the timing when the addresses are determined simultaneously. In short, as long as the write / read operation of the first and second circuits 10 and 11 is controlled on the basis of the write address 105 and the read address 109 at the timing when the addresses are determined simultaneously, any method may be used. .
[0062]
【The invention's effect】
As described above, according to the specific matters of the present invention, the write operation of the first circuit and the read operation of the second circuit are controlled based on the read address and the write address at the timing when the addresses are determined simultaneously. As described above, it is possible to provide an interface circuit capable of high-speed data transmission with a simple circuit configuration without any restriction on the clock cycle used for two circuits operating asynchronously.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a data transmission system according to a first embodiment using an interface circuit according to the present invention.
FIG. 2 is a circuit diagram of an address comparison circuit according to the same embodiment;
FIG. 3 is a timing chart showing an example of timing when write data is written from the first circuit to the buffer in the embodiment;
FIG. 4 is a timing chart showing an example of a timing at which a second circuit reads read data from a buffer in the embodiment.
FIG. 5 is a timing chart showing an example of operation timing for address comparison in the embodiment;
FIG. 6 is a diagram showing a truth table for obtaining a first comparison result when the read setting value is “3” in the embodiment.
FIG. 7 is a diagram showing a truth table for obtaining a second comparison result when the write setting value is “22” in the embodiment.
FIG. 8 is a circuit diagram of a data transmission system using an interface circuit according to a second embodiment.
FIG. 9 is a circuit diagram of an address comparison circuit according to the same embodiment;
FIG. 10 is a block diagram showing a configuration example of a computer system using an interface circuit according to the first and second embodiments.
[Explanation of symbols]
1,2 ... Interface circuit
10: First circuit
11 ... Second circuit
12 ... Buffer (storage means)
14 ... WR address counter (write address generation means)
16... RD address counter (read address generating means)
17 ... Address comparison timing generation circuit (timing detection means)
22... Comparison circuit (accumulated data number detection means, comparison means)
24 B register (reading control means)
25 ... C register (write control means)
19 ... Address comparison circuit (control means)
100: First clock signal
101: Second clock signal
103: Write enable signal
105: Write address (write address)
109 ... Read address (read address)
107: Read enable signal
114: Write request signal (write control signal)
112 ... Read permission signal (read control signal)

Claims (8)

Provided between the first circuit synchronized with the first clock signal and the second circuit synchronized with the second clock signal, and transfers data between the first circuit and the second circuit An interface circuit that
Storage means for writing data supplied from the first circuit, reading the stored data and outputting the data to the second circuit;
Write address generating means for generating a write address indicating a write position of the storage means based on the first clock signal;
A read address generating means for generating a read address indicating a read position of the storage means based on the second clock signal;
Timing detection means for detecting a timing at which the write address and the read address are simultaneously determined based on the first clock signal and the second clock signal;
Control means for controlling a write operation of the first circuit and a read operation of the second circuit based on the write address and the read address at the timing detected by the timing detection means ; An accumulated data number detecting means for comparing the read address and the write address to detect the accumulated data number in the storage means; a comparing means for comparing the accumulated data number with a predetermined read setting value; Control means comprising: reading control means for controlling the reading operation of the second circuit based on the comparison result of the comparing means;
With
The read setting value is
A maximum number of data that may be read during a period from when data reading from the storage means is started to when a read control operation is performed on the second circuit based on the read address changed, and the control A predetermined number based on the maximum number of data that may be read from when the means instructs the second circuit to stop reading until the second circuit stops the reading operation. A featured interface circuit. The read control means outputs a comparison result corresponding to a timing at which the read address and the write address are simultaneously determined from the comparison results of the comparison means based on the timing detected by the timing detection means. 2. The interface circuit according to claim 1, wherein the interface circuit extracts and controls a read operation of the second circuit based on the extracted comparison result. 2. The accumulated data number detecting means detects the number of accumulated data in the storage means by comparing the read address and the write address at the timing detected by the timing detecting means. Interface circuit described in 1. The interface circuit according to claim 1, wherein the comparison unit compares the number of accumulated data at the timing detected by the timing detection unit with a predetermined read setting value. Provided between the first circuit synchronized with the first clock signal and the second circuit synchronized with the second clock signal, and transfers data between the first circuit and the second circuit An interface circuit that
Storage means for writing data supplied from the first circuit, reading the stored data and outputting the data to the second circuit;
Write address generating means for generating a write address indicating a write position of the storage means based on the first clock signal;
A read address generating means for generating a read address indicating a read position of the storage means based on the second clock signal;
Timing detection means for detecting a timing at which the write address and the read address are simultaneously determined based on the first clock signal and the second clock signal;
Control means for controlling a write operation of the first circuit and a read operation of the second circuit based on the write address and the read address at the timing detected by the timing detection means ; An accumulated data number detecting means for comparing the read address and the write address to detect the accumulated data number in the storage means; a comparing means for comparing the accumulated data number with a predetermined read setting value; Control means comprising: a writing control means for controlling a writing operation of the first circuit based on a comparison result of the comparing means;
With
The write setting value is
A maximum number of data that may be written during a period until a write control operation is performed on the first circuit based on the changed write address after the start of data writing to the storage means; And a predetermined number of data that may be written before the first circuit stops the writing operation after the control means instructs the first circuit to stop writing. An interface circuit characterized by that .   The write control means, based on the timing detected by the timing detection means, the comparison result corresponding to the timing at which the read address and the write address are simultaneously determined from the comparison results of the comparison means 6. The interface circuit according to claim 5, wherein a write operation of the first circuit is controlled based on the extracted comparison result.   6. The accumulated data number detecting means detects the number of accumulated data in the storage means by comparing the read address and the write address at the timing detected by the timing detecting means. Interface circuit described in 1.   6. The interface circuit according to claim 5, wherein the comparison unit compares the number of accumulated data at the timing detected by the timing detection unit with a predetermined write setting value.

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