JP3093583B2 - Memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO (first-in first-
out) The present invention relates to a memory control circuit for controlling a memory, and more particularly to a memory control circuit for reading data by controlling the memory with a read clock having a different speed from a write clock.

[0002]

2. Description of the Related Art For example, in digital exchanges,
There is a type that employs a FIFO memory that sequentially accumulates data such as incoming packets and reads and transfers the data in the order of arrival. In such a FIFO memory,
Data is written in synchronization with a write clock at a predetermined speed, and data is read out at a read clock faster than the write clock, for example, at twice or more the speed of the write clock in order to recover delay due to transmission.

In such a memory control circuit of a FIFO memory, the latest write address is compared with the read address to detect the amount of accumulated data at any time, and to determine whether to continue reading, and to determine whether to continue reading. Read control is performed. In this case, the write address driven by the write clock and the read address driven by the read clock must be synchronized and then compared.

Conventionally, when a write address and a read address are compared in synchronization with each other, for example, a write address is converted so as to be synchronized with a read clock, and the read address is compared with the following synchronous conversion method. It has been known. First, write addresses supplied to the FIFO memory are sequentially detected, and these are sequentially passed through a plurality of serial delay elements to gradually give a phase difference to each write address. A write address having a different phase from each delay element and a write address to which no phase is given are respectively held by one hold circuit. In this case, the maximum delay period of the write address is set to be at least one cycle or less of the write clock. The difference between the delay periods of the write addresses is longer than the sum of the minimum required times of the setup time and the hold time of the hold circuit, and at least one type of signal that does not meet the requirements of the setup period and the hold period of the hold circuit. Set to only.

When each write address is held by the hold circuit, the hold circuit is driven by a read clock, and write addresses having a plurality of phase differences are output so as to be synchronized with any one of the read clocks. . A plurality of addresses from these hold circuits are supplied to a significant signal determination unit. The significant signal determination unit selects a matching address from among the plurality of addresses as a significant write address normally synchronized with the read clock.
That is, for example, when an address to which no phase is applied matches an address to which one delay is applied, it is determined that the signal satisfies both the setup time and the hold time of the hold circuit. Selected as a valid write address. If the addresses do not match and the addresses with one delay and two delays match, it is determined that either the setup time or the hold time does not satisfy the regulation at the address to which no phase is given. Then, an address given one delay is selected from addresses given one delay and two delays determined to satisfy the respective rules. Similarly, two delays, three delays, four delays ...
Select the matching address from the addresses sequentially given. In this case, an address with a small number of delays close to the current write address is preferentially selected. As a result, one of the plurality of write addresses is read as a signal accurately synchronized with the read clock, and the read address is compared with the read address to detect the remaining data amount.

[0006]

However, in the above-mentioned conventional technique, an unstable delay time such as a gate delay and a wiring delay due to a change in the operating environment is added to the delay period of the write address. There is a problem that the judgment may be erroneous. In order to reduce errors, it is conceivable to increase the number of delay stages to increase the number of addresses to be compared. However, this only complicates the circuit, and the previous instability remains, making it unsuitable for high-speed processing. There was a problem.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned drawbacks of the prior art and to provide a highly reliable memory control circuit which is less affected by the circuit operating environment and suitable for high-speed processing.

[0008]

In order to solve the above-mentioned problems, a memory control circuit according to the present invention is a memory control circuit for controlling writing and reading of data to and from a data storage section. A write control unit for generating a write address that sequentially advances in synchronization with the write clock of the write control unit and supplying the generated write address to the data storage unit; and sequentially synchronizing with a read clock having a speed different from the speed of the write clock from the write control unit. A read control unit that generates a read address to be incremented and supplies it to the data storage unit, and detects a data storage amount of the data storage unit as needed based on a write address from the write control unit and a read address from the read control unit. And a read determination unit for determining the start and stop of data reading in the read control unit. A synchronous conversion unit that detects a bit address of a write address synchronized with the read clock, and corrects the error while correcting the error. A synchronous converter for forming an address, and a write address synchronized with a read clock from the synchronous converter and a read address synchronized with the read clock from the read controller are compared to detect a remaining amount of data in the data storage unit. And a remaining amount detection unit.

In this case, the synchronous conversion unit latches the write address from the write control unit and sequentially inputs the write address in synchronization with the read clock, and a bit error of the write address synchronized with the read clock from the input unit. Error correcting means, and output means for outputting an error-corrected write address from the error correcting means in synchronization with the read clock, wherein the error correcting means includes a current write address input through the input means. In response to the adjacent bit and the write address at the time before output from the output means,
It is preferable to correct the bit error of the current write address based on these.

Preferably, the input means and the output means are a plurality of flip-flop circuits which operate in synchronization with a read clock provided corresponding to each bit of the write address. Further, the error correction means is provided corresponding to each bit of the write address,
A plurality of combinational logic circuits for obtaining respective logic output bits (E) obtained by E = A · B ~ + C · D ~ (where B ~ and D ~ represent inverted B and inverted D, respectively) , The input (C) is connected to the output of the corresponding input side flip-flop circuit,
(B, D) are connected to the outputs of the input-side flip-flop circuits adjacent to the corresponding flip-flop circuits, respectively.
A combination in which the input (A) is connected to the flip-flop circuit on the output side of the bit adjacent to the corresponding bit, and the logical output (E) in which the bit error of the input (C) is corrected is supplied to the corresponding flip-flop circuit on the output side It may be a circuit.

On the other hand, in the memory control circuit of the present invention, any one bit is set to "1" in order to compare the address signals from the write control unit and the read control unit with the remaining amount detection unit. It is preferable to have a decoding unit that decodes the address signal into a predetermined form that takes a value and supplies the address signal to the remaining amount determination unit.

In this case, the read clock includes a clock generated at twice or more the speed of the write clock,
Decoding means that each address signal is a decimal "
When "0" is represented, each bit value is A0 = 1, A1 to A
N = 0, A0 = 0, A1 = 1, A2 to AN = 0 when the address signal represents decimal "1", and A0 to A when the address signal represents decimal "N" It is preferable to decode the address signals A0 to AN such that (N-1) = 0 and AN = 1.

Further, the read clock includes a clock supplied at a speed of M times or more the write clock, and the decoding means determines that each address signal is a decimal "0".
When representing "M", the respective bit values are A0 = 1, A1
~ AN = 0, and when the address signal represents decimal "M + 1" to "2M", A0 = 0, A1 = 1, A2 to AN = 0, and the address signal is decimal "2M + 1" A0, A1 = 0, A2 = 1,
A3 ~ AN = 0, and the address signal is decimal ("(N-1) M + 1")
It is preferable to decode the address signals into A0 to AN, where A0 to A (N-1) = 0 and AN = 1 when represented by .about. "NM".

[0014]

According to the memory control circuit of the present invention, the write addresses sequentially incremented in response to the write clock are supplied from the write control unit to the data storage unit, and the data is sequentially stored at each address. Go. When a predetermined amount of data is stored in the data storage unit, a read address that is sequentially increased in response to a read clock at a different speed from the write clock in the read control unit is supplied to the data storage unit, and the data is sequentially stored. The data is read in the order in which the data was written in the section. At this time, the write address output from the write control unit and the read address output from the read control unit are sequentially compared by the read determination unit, and the remaining amount of data in the data storage unit is detected. In this case, the read determination unit converts the write address detected by the synchronous conversion unit into an address synchronized with the read clock, and compares this with the read address in the remaining amount detection unit.

When the write address is synchronized with the read clock by the synchronous conversion unit, the write address of the current input is once synchronized with the read clock, and the current write address is changed to the previous time before the write address is advanced. In comparison with the write address output in synchronization with the read clock, duplicate and missing bits of the stepped bits are detected, the erroneous bits are corrected at the current write address, and further synchronized with the read clock. It is sequentially supplied to the remaining amount detection unit. Thus, the remaining amount detection unit compares the write address synchronized with the bit-corrected read clock with the read address at that time, and if the addresses match, for example, sends a signal to the read control unit to stop reading. To pause the reading of data.

Thereafter, when a predetermined amount of data is again stored in the data storage unit, a read address synchronized with a read clock is supplied from the read control unit to the data storage unit, and data reading is started. And the read address are compared to determine whether to stop reading while detecting the remaining amount of data.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a memory control circuit according to the present invention; FIG. 1 shows a FIFO (First-in Firs) to which a memory control circuit according to the present invention is applied.
One embodiment of a t-out) memory device is shown.

The memory control circuit of the present embodiment sequentially advances the write address WA synchronized with the write clock WCL and writes data in the data storage section 60 in address order, and outputs the data to the read clock RCL having a shorter cycle than the write clock WCL. This is a control circuit of a FIFO memory that reads data from the data storage unit 60 in the order in which synchronous read addresses are sequentially increased and written. In particular, in the present embodiment, the write address WA and the read address RA are compared to determine whether to continue reading while detecting the remaining amount of data. At this time,
A memory control having a remaining amount detection function that synchronously converts a write clock WCL to a read clock RCL, forms a write address accurately and synchronously converted while detecting and correcting the bit error, and compares the write address with the read address. Circuit.

More specifically, the memory control circuit according to the present embodiment comprises:
A write control unit 10, a read control unit 20, decoders 30 and 40,
In particular, the read determination unit 50 includes a synchronization conversion unit 52 and a remaining amount detection unit 54. The write clock WCL supplied to the write control unit 10 is, for example, a clock synchronized with the input transfer clock of the data IN, and is supplied to the write control unit 10 at a predetermined speed from an external device that supplies data. The write control unit 10 includes an address counter that sequentially advances in accordance with a write clock WCL, and generates an address that supplies the multi-stepped write address WA to the data storage unit 60 in parallel in synchronization with the write clock WCL. Department. The number of bits of the write address WA is set according to the storage capacity of the data storage unit 60. In this embodiment,
For example, the data IN is written in the data storage unit 60 in units of 1 byte, and the write address WA is an address for sequentially specifying the logical address.

The read clock RCL is equal to the write clock WC
A clock having a period equal to or less than one half of L, that is, a clock having a speed twice or more, may be formed by dividing the write clock WCL, for example, and the speed may be arbitrarily determined according to the device used. Is set. The read control unit 20 includes an address counter that sequentially advances in accordance with the read clock RCL, and supplies the read multiple-bit read address RA to the data storage unit 60 in parallel in synchronization with the sequential read clock RCL. The read address RA is a logical address that is set to the same number of bits as the write address WA, and that is sequentially advanced like the write address WA to read the data OUT from the data storage unit 60 in byte units.

The data storage unit 60 has an RA having a predetermined capacity.
A memory circuit such as M (Random Access Memory), in which data IN is sequentially written to an address activated at a write address WA from the write control unit 10, and data OUT is output from an address activated at a read address RA. Form a FIFO memory circuit that is read sequentially.

The decoders 30 and 40 perform an address conversion for decoding the write address WA from the write control unit 10 or the read address RA from the read control unit 20 into address signals X and Z of a predetermined form for respective comparisons. In this embodiment, the address signals A0 to AN (N is a natural number) in which only one bit is set to "1" for the address WA, RA incremented by the write control unit 10 and the read control unit 20. This is an address decoder that converts the data into an address. For example, when the address value represents "0" in decimal, A0 of the address signals represented by A0 to AN
When only bits are "1" and "1" is represented in decimal
Only the A1 bit is set to "1", and when representing "N" in decimal, only the AN bit is set to "1".

The read judging section 50 is a judging circuit for judging the start time and the stop time of the read in the read control section 20, and based on the address signals X, Z converted by the decoders 30, 40, the data storage section. The remaining amount determination unit detects the amount of accumulated data of 60 and supplies the determination signal R to the read control unit 20. In this embodiment, a synchronous conversion section 52 outputs the write address X supplied via the decoder 30 as a write address Y synchronously converted to the read clock RCL, and the synchronously converted write address Y and the synchronous address are supplied via the decoder 40. And a remaining amount detection unit 54 for comparing the read address Z from the read control unit 20 and supplying the determination result to the read control unit 20.

In particular, the synchronous conversion section 52 of this embodiment detects errors for each bit when the input write address X is synchronously converted, and corrects these errors while replacing them with the read clock RCL to perform the write operation. An error correction function to be supplied to the remaining amount detection unit 54 as the address Y is included. This synchronous converter 52
For example, as shown in FIG. 2, a plurality of input-side flip-flop circuits (input FFs) F1 to Fm, a plurality of combinational logic circuits K1 to Km, and a plurality of output-side flip-flop circuits (output
FF) G1 to Gm.

The input-side flip-flop circuits F1 to Fm latch the respective bits X (1) to X (m) of the write address X and temporarily synchronize the current address signals W (1) to W (1) to X (m) with the read clock RCL. Each is a first clock converter that forms W (m). More specifically, it is a one-input one-output logic circuit formed by a D (Delay) -flip-flop, and a write address supplied via a decoder 30.
It has an input terminal (D) for latching X (1) to X (m), a clock terminal to which a read clock RCL is supplied, and an output terminal (Q) for reading each bit latched in synchronization with the input terminal (D). Each is a latch circuit.

Similarly, output-side flip-flop circuits G1 to G1
Gm is 1 formed by each D-flip-flop.
An input terminal (D) for latching outputs E (1) to E (m) from combinational logic circuits K1 to Km.
A clock terminal to which a read clock RCL is supplied;
An output Q terminal (Q) for reading out each bit latched in synchronization with this, the address signals E (1) to E (m) corrected by the combinational logic circuits K1 to Km are latched and Write addresses Y (1) to Y synchronized with read clock RCL
(m) is a second clock converter.

The combinational logic circuits K1 to Km output the output E (1) in which the bit errors of the address signals W (1) to W (m) from the input side flip-flops F1 to Fm are corrected based on a predetermined combinational logic. EE (m). In this embodiment, the error correction circuit obtains an error-corrected output based on the temporal change of the value of the previous bit and the value of the next bit. More specifically, each of the logic circuits has four inputs and one output.
The output (E) of the result calculated by the logical expression E = A ・ B ~ + C ・ D ~ (where B ~ and D ~ represent inverted B and inverted D, respectively) based on the values of the two inputs A to D ). In this case, the outputs (Q) of the output-side flip-flop circuits Gm, G1 to Gm-1 of the preceding bit of the corresponding bit are respectively connected to the first input (A), and the second input (B) is connected to the second input (B). The outputs (Q) of the input flip-flops Fm, F1 to Fm-1 of the previous bit are respectively connected, and the outputs (Q) of the corresponding input flip-flops F1 to Fm are connected to the third input (C), respectively. And the fourth input (D) has input-side flip-flops F2 to Fm, Fm of the next bit.
1 outputs (Q) are connected. The internal configuration is a logic circuit that satisfies the above-mentioned logical formula, for example, combining logic elements such as a NOT circuit, an AND circuit and an OR circuit or a NAND circuit or a NOR circuit.

By the way, the first item on the right side of the logical expression E (A.B ~)
Indicates whether or not the value has changed from the previous time in the previous bit, and the second item (C ・ D か) indicates whether or not the value has changed in the corresponding bit and the next bit. Is obtained, a value E in which a bit error that is duplicated or missing between adjacent bits is corrected is obtained. That is, the write addresses W (1) to W (m) supplied from the input-side flip-flops F1 to Fm are based on the latch timing of the addresses X (1) to X (m) and the read clock at each time.
Depending on the timing of the occurrence of RCL, bit errors such as out-of-sync may occur as shown in FIGS.
The waveform shown in FIG. 3 represents the write addresses X (k) and X (k + 1) synchronized with the write clock WCL, and the waveform of FIG. 4 shows the write address W normally synchronized with the read clock RCL. (k) and W (k + 1), and the waveform in FIG. 5 shows a state where the write addresses W (k) and W (k + 1) overlap when synchronized with the read clock RCL. The waveform similarly shows a state where there is a gap between the write addresses W (k) and W (k + 1) when the synchronous conversion is performed.

The combinational logic circuit Kk obtains a logical output E (k) obtained by correcting such a bit error of the write address W (k) by the combinational logic. In this case, the output E (k, t) at the time t is represented by the following equation (1). E (k, t) = Y (k, t + 1) = Y (k-1, t) ・ W ~ (k-1, t) + W (k, t) ・ W ~ (k + 1, t ) (1) where, in the equation (1), when k = 1, Y (k-1, t) = Y (m,
t), W (k-1, t) = W (m, t-1) and when k = m, W (k + 1, t) = W (1, t)
It is. FIG. 7 shows, for example, the address W when m = 3.
(k), E (k), and Y (k) are shown. For example, at time t3, second bit W (2) overlaps with first bit W (1).
In this case, from the first output Y (1) = "1" and the first bit W (1) = "1" at the previous time indicated by the broken line, AB is "0". Also the second
From the bit W (2) = "1" of the first bit and the third bit W (3) = "0", CD · =
1 ". As a result, the logical output E which is the logical sum of them is
(2) = "1". Similarly, the first bit W (1) is obtained from the third output Y (3) = "0" and the third bit W (3) = "0" at the previous point in time by AB.
= "0", first bit W (1) = "1" and second bit W (2) = "
From 1 ", C ・ D ~ =" 0 ", and the resulting logical output E (1) =" 0 "
Becomes As a result, the address that is duplicated at time t3
W (1) and W (2) become logical output E (1) = "0" and logical output E (2) = "1", and error correction is performed. The logical outputs E (1) and E (2) are latched by the output flip-flops G1 and G2, and output bits delayed by one clock at the next clock t4 as shown by the broken line.
Output as Y (1), Y (2).

Returning to FIG. 1, the remaining amount detection unit 54 is a synchronous conversion unit.
An instruction circuit for instructing the read control unit 20 to start and stop reading data based on the write address Y from the read address 52 and the read address Z from the decoder 40;
A counter for counting the value of the write address X from 52 and a comparison circuit for comparing the counter with the read address Z from the decoder 40 are included. For example, at the start of data accumulation, the write address X counts until it reaches a predetermined value, and when the count reaches a predetermined value, a determination signal R instructing the start of reading is output. Is a determination circuit that outputs a determination signal R indicating read stop to the read control unit 20 when the result of the comparison is equal.

Next, the operation of the memory control circuit according to the present embodiment having the above configuration will be described. First, data IN is FI
When sequentially transferred to the FO memory, for example, a write clock WCL corresponding to the transfer clock is supplied to the write control unit 10. As a result, the write address WA sequentially incremented in response to the write clock WCL is supplied from the write control unit 10 to the data storage unit 60. As a result, data IN is sequentially stored at each address. At this time, the read determination unit 50 receives the write address X from the write control unit 10 via the decoder 30, and when the write address X reaches a predetermined value, the determination signal R instructing the read control unit 20 to start reading.
Supply.

In the read control unit 20, which has received the signal R indicating the start of reading, the read address RA sequentially stepped up in response to the read clock RCL at twice or more the speed of the write clock WCL.
Is generated and supplied to the data storage unit 60. This allows
The data stored in the data storage unit 60 is read out in the order of the addresses in response to the speed of the read clock RCL. At this time, the read address RA output from the read control unit 20 is sequentially converted into a predetermined address Z by the decoder 40.
Remaining amount detection unit of read determination unit 50 as a signal decoded to
The data remaining in the data storage section 60 is detected by sequentially comparing the write address Y supplied to the write address Y, which is similarly decoded and synchronously converted.

In this case, the write address Y is
The write address X from 30 is converted by the synchronous converter 52 so as to be synchronized with the read clock RCL, a bit error occurring at that time is detected, and the error-corrected write address Y is supplied to the remaining amount detector 54. doing. For more information,
The write address X is read by the synchronous converter 54 and the read clock RC
When synchronizing to L, each bit X (1) to X (m) of the write address X of the current input is
It is sequentially latched at F1 to Fm. Next, when the read clock RCL is supplied to each of the flip-flops F1 to Fm, each of the latched bits W (1) is synchronized with this.
WW (m) are output to the combinational logic circuits K11Km. At this time, the read clocks are output from the output side flip-flops G1 to Gm.
The previous write addresses Y (1) to Y (m) are output in synchronization with RCL, and supplied to the inputs (A) of the combinational logic circuits K1 to Km. As a result, the logic circuits K1 to Km obtain the operation results from the inputs A to D at the logical outputs E = A.B to + C.D.
(1) to E (m) are supplied to output side flip-flops G1 to Gm, respectively. The resulting outputs E (1) to E (m) are outputs in which bit errors such as the out-of-sync of the current addresses W (1) to W (m) have been corrected.

For example, as shown in FIG. 7, assuming that 3-bit addresses X (1), X (2), and X (3) are supplied to the synchronous conversion unit 52, each of them becomes the first at the time t1. Bits W (1), W (2),
Output as W (3) = "1,0,0". At this time, the bits Y (1), Y (2), Y
(3) Outputs "0,0,1". Thereby, the combinational logic circuit K
1 to K3 are logical outputs, respectively, E (1) = Y (3) ・ W ~ (3) + W (1) ・ W ~
(2) and E (2) = Y (1) ・ W ~ (1) + W (2) ・ W (3) and E (3) = Y (2) ・ W ~
(2) + W (3) · W ~ (1) is obtained. Since the output of this result does not include bit errors such as duplication and omission in the addresses W (1), W (2) and W (3), the same logical outputs E (1) and E (2) , E (3) = "1,
0,0 ". These are output flip-flops G1
~ G3, and Y (1), Y (2), Y (3) at the next clock
Is output as

Next, when the second clocks are supplied at time t2, the bits W (1), W (2) and W (3) remain unchanged, and the outputs Y (1) and Y (1) (2), Y (3) is changed from E (1), E (2), E (3) obtained at the previous time to "1,0,0" as shown by the broken line and output. You. But the logical result is that the address W
Since there are no bit errors in (1), W (2), W (3), the logical output E (1),
E (2), E (3) = "1,0,0" remain. That is, the logical expression E
(1) = Y (3) ・ W ~ (3) + W (1) ・ W ~ (2) changes Y (3) from "1" to "0", but bit W (1), W ~ Since (2) remains "1" and "0", E
(1) = "1" does not change. E (2) = Y (1) ・ W ~ (1) + W (2) ・ W (3)
And E (3) = Y (2) · W ~ (2) + W (3) · W ~ (1) do not include Y (3), so E (2) = "0", E ( 3) The state of "0" remains.

Next, when the third clocks are respectively supplied at time t3, the second bit W (2) changes from "0" to "1".
To overlap with the first bit W (1). In this case, since the output Y (1), Y (2), Y (3) at the previous time is 1,0,0, the logical output E (2) = Y (1) · W ~ (1) + W (2) · W (3) = 1 · 1 to + 1.0 · = “1”. Similarly, logic output E (1) = Y (3) ・ W ~ (3) + W (1) ・ W ~ (2) = 0 ・ 0
~ + 0 · 0 ~ = "0". As a result, logical outputs E (1) and E (2) in which the duplication error between the first bit and the second bit is corrected are obtained. In this case, the rising of the second bit W (2) does not synchronize with the read clock at the previous time, and the falling of the first bit W (2) does not synchronize with the time t3.
Since it is considered that the clock is synchronized with the delay of the clock, the logical output E (1) is corrected to "0" at the time t3, and the logical output is
The result of raising E (2) to "1" is considered to have returned to the correct value.

Next, at time t4, the first bit W (1)
0 ", and the previous outputs Y (1) and Y (2) are" 0 "and" 1 "respectively.
Changes to The logical outputs E (1), E (2), and E (3) of this result are "0, 0" since the input bits W (1), W (2), W (3) have no bit errors.
1,0 ". Similarly, at time t5, each bit remains unchanged and the state at time t4 is continued.
Next, at time t6, the second bit W (2) changes from "0" to "1", but the next third bit W (3) is not synchronized and does not rise, and the second bit W (2) does not rise. A missing error has occurred with the third bit. The output of this result is E (2) = Y (1) · W ~
(1) + W (2) ・ W (3) = 0 ・ 0 ~ + 0 ・ 0 ~ = "0", E (3) = Y (2) ・ W ~
(2) + W (3) · W (1) = 1 · 0 to + 0 · 0 to = “1” This is a result that when the second logical output E (2) falls, the third logical output E (3) rises, and a missing error between them is corrected. In this case, the third bit W (3) is not synchronized with the clock at time t6 but is delayed later than the possibility that the falling of the second bit W (2) is earlier synchronized with the clock.
Since it is considered to be synchronized with the clock of t7, at time t6, the second logical output E (2) falls, and the third logical output E (3) is corrected and started. It is considered to have been returned to.

Next, at time t7, the third bit W (3) normally becomes "1", but at time t6, E (3) becomes "1". The states of (1), E (2), and E (3) are maintained and become normal outputs. Hereinafter, at times t8 and t9, the input remains unchanged and the output remains unchanged. In this case, since there are three inputs, the state change returns to time t1 again, and thereafter, each time the write address WA advances, the input bits X (1), X (2), X (3) are sequentially set to "1". Is supplied alternately and repeatedly. This is temporarily input by the input side latch circuits F1 to F3.
Bits W (1), W read in synchronization with read clock RCL
Combinational logic circuit that forms (2) and W (3) and uses bit errors at that time
Correction based on adjacent bits W (1), W (2), W (3) and Y (1), Y (2), Y (3) representing the logic output of the previous time point in K1 to K3 , To the output latch circuits G1 to G3. As a result, the output Y of the synchronous converter 52 is sequentially supplied to the remaining amount detector 54 as a write address Y accurately converted synchronously with the read clock RCL.

As described above, in the remaining amount detector 54 receiving the write address Y and the read address Z synchronized with the read clock RCL, for example, when they match, the determination signal R indicating stop of the read is sent to the read controller 20. To temporarily stop reading data from the data storage unit 60. Thereafter, when the data is further written in the write control unit 20 and the data storage amount reaches a predetermined value, the read determination unit 50 that detects the write address X sends a determination signal R to start reading again. The data is sent to the read control unit 20, and the reading of the data OUT is stepped to the next read address RA at which the reading was previously stopped, and the data reading is started again. Thereafter, the stop and start of the read are repeated while comparing the write address Y and the read address Z in the same manner as described above, and the first-in first-out control of the data in the data storage unit 60 is sequentially and effectively repeated.

As described in detail above, according to the memory control circuit of the present embodiment, the write address WA sequentially incremented
Is decoded to an address X in which one bit is sequentially set corresponding to the address value, and this is temporarily synchronized with only one latch to an address signal W synchronized with the read clock RCL, and this is synchronized with the adjacent bit and the previous time. Address Y (t
-1), the remaining amount is detected by the remaining amount detection unit 54 as an accurate write address Y synchronized with the read clock RCL.
To perform synchronous conversion that is hardly affected by changes in the operating environment. As a result, highly reliable memory control can be realized.
Further, the synchronization conversion unit 52 of the present embodiment can easily synchronize the input and output flip-flop circuits F1 to Fm, G1 to Gm and the combinational logic circuits K1 to Km with the same clock at all clock terminals. It can be composed of simple circuits.

FIG. 8 shows the synchronous converter of this embodiment.
To clarify the advantages of 52, an example of a conventional synchronization converter 70 is shown. In this example, the write address X supplied in parallel is divided into three delay elements connected in series.
At 2, 4, and 6, delays are given during one cycle of the write clock WA, and these are supplied to the inputs A ^{-1 to} D ^-1 of the hold circuit 8 together with the address A ^-1 to which no delay is given. . The hold circuit 8 outputs the plurality of held addresses A ^{-1 to} D ^-1 in synchronization with the read clock RCL. In this case, the delay difference between the delay elements 2, 4, and 6 is set longer than the sum of the minimum required time of the setup time and the hold time of the hold circuit 8. As a result, a plurality of write addresses including a phase difference due to delay
Any one of A ^{-1 to} D ^-1 has the same phase and is supplied to the significant signal determination unit 9. This significant signal determining section 9 has 4
The two addresses are compared with each other, and the matching addresses A to D are detected by a logic such as an exclusive OR, and these are selected as a significant write address Y and supplied from the output Q to the remaining amount detection unit 54 and the like. I do. In this case, an address with a small delay is preferentially selected.

As described above, in the comparative example shown in FIG. 8, since the address is delayed by the delay elements 2, 4, 6, etc., the address signal is transferred from the write control unit 10 to the synchronous conversion unit 70. The delay of various gates and lines must be taken into account, and circuit design becomes difficult. In this case, since each factor changes the delay time depending on the operating environment of the circuit, the circuit configuration becomes more difficult, and expensive materials, such as materials and elements of each part, which are not easily affected by the environment, must be used. . In this embodiment,
Since a bit error due to the influence of the change in the circuit configuration and the environment is corrected, the bit error is hardly affected by the correction and the circuit can be realized with a simple circuit configuration. In the comparative example, if the number of delay elements is increased and the number of addresses to be compared is increased, the influence of changes in the operating environment can be reduced. Since a plurality of bit addresses are compared, the circuit scale becomes large and the operation speed becomes slow. In this embodiment, an address can be input one by one and an output can be obtained only by a simple logical calculation. Therefore, an address synchronized with the read address RCL can be obtained quickly and accurately. As described above, the memory control circuit according to the present embodiment can realize accurate and high-speed memory control with a simple configuration.

In the above embodiment, one bit is set to "1" each time the address WA, RA is incremented by one in the decoders 30, 40, but in the present invention, For example, if the read clock has a speed that is M times or more as fast as the write address, in order to perform the address comparison at a high speed, only the address A0 bit is set to "1" when the address value represents a decimal number "0" to "M". When the address value represents decimal "M + 1" to "2M", only the A1 bit is set to "1", and when the address value represents decimal "2M + 1" to "3M"
Only the A2 bit is set to "1". Thereafter, when the address value represents a decimal number from "(N-1) M + 1" to "NM", only the AN bit is set to "1".
May be decoded to address signals A0 to AN.

In the above embodiment, the combinational logic circuit K1
Although the example in which the internal configuration of ~ Kk is formed by a logic element such as an AND circuit or an OR circuit has been described, the present invention is not limited to this. For example, an RS flip-flop circuit or
A combinational logic circuit that performs the operation of the above logical expression may be configured by combining logic circuits such as a JK flip-flop circuit.

[0045]

As described above, according to the memory control circuit of the present invention, when a write address generated in synchronization with a write clock is replaced with a read clock, bit errors due to duplication or omission of adjacent bits are caused. The write address synchronized with the read clock is formed while correcting the error, and the remaining amount of data is detected, so that the processing can be executed at high speed and accurately without being substantially affected by changes in the operating environment. it can. In addition, since error correction and synchronous conversion are performed for each address, the circuit configuration can be made simple and small. Therefore, an excellent effect that a small, high-speed memory control circuit with high reliability can be realized is achieved.

[Brief description of the drawings]

FIG. 1 is a FIFO to which a memory control circuit according to the present invention is applied;
FIG. 2 is a block diagram showing one embodiment of a memory device.

FIG. 2 is a block diagram showing an internal configuration of a synchronization converter according to the embodiment of FIG.

FIG. 3 is a time chart showing a normal write address synchronized with a write clock in the embodiment of FIG. 1;

FIG. 4 is a time chart showing write addresses that have been normally synchronously converted in the embodiment of FIG. 1;

FIG. 5 is a time chart showing a write address where a duplicate bit appears when synchronous conversion is performed in the embodiment of FIG. 1;

FIG. 6 is a time chart showing a write address at which a missing bit appears when synchronous conversion is performed in the embodiment of FIG. 1;

FIG. 7 is a time chart showing an address waveform of a main part in the embodiment of FIG. 2;

FIG. 8 is a block diagram illustrating a comparative example of the synchronous conversion unit of the present embodiment.

[Explanation of symbols]

 10 Write control unit 20 Read control unit 30, 40 Decoder 50 Read determination unit 52 Synchronization conversion unit 54 Remaining amount detection unit 60 Data storage unit F1 to Fm Input side flip-flop G1 to Gm Output side flip-flop K1 to Km Combinational logic circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-189955 (JP, A) JP-A-61-283925 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 7/00 318 G06F 5/06 WPI (DIALOG)

Claims (7)

(57) [Claims] 1. A memory control circuit for controlling writing and reading of data to and from a data storage section, wherein the circuit generates a write address that sequentially advances in synchronization with a write clock at a predetermined speed, and generates the write address. A write control unit for supplying a read address which sequentially increases in synchronization with a read clock having a speed different from the speed of the write clock from the write control unit and supplying the read address to the data storage unit Unit, based on the write address from the write control unit and the read address from the read control unit, detects the amount of data stored in the data storage unit as needed, and starts the data read by the read control unit and A read judging unit for judging a stop, wherein the read judging unit detects write addresses sequentially output from the write control unit, and reads each of the read addresses. A synchronous converter for converting the write address in synchronization with the click,
A synchronous converter for detecting a bit error of the write address synchronized with the read clock, forming a write address subjected to clock synchronous conversion while correcting the error, and a write address synchronized with the read clock from the synchronous converter. A memory control circuit, comprising: a remaining amount detection unit that compares a read address synchronized with a read clock from the read control unit and detects a remaining amount of data in the data storage unit. 2. The memory control circuit according to claim 1, wherein said synchronization conversion unit sequentially latches a write address from said write control unit and inputs the write address in synchronization with a read clock; Error correction means for correcting a bit error of a write address synchronized with a read clock from the means; and output means for sequentially latching the write address from the error correction means and outputting the write address in synchronization with the read clock. The correction means receives adjacent bits of the current write address input through the input means and the previous write address output from the output means, and based on these, corrects a bit error of the current write address. A memory control circuit characterized by correcting. 3. The memory control circuit according to claim 2, wherein said input means and output means operate in synchronism with a read clock provided corresponding to each bit of a write address. A memory control circuit including a circuit. 4. The memory control circuit according to claim 3, wherein said error correction means is provided corresponding to each bit of a write address, and a logical expression E = AAB ~ + C ・ D ~ ( Here, B ~ and D ~ are a plurality of combinational logic circuits for obtaining respective logical output bits (E) obtained by inverting B and D), and an input (C) corresponds to the corresponding input side. The inputs (B, D) are connected to the outputs of the flip-flop circuits, the inputs (B, D) are connected to the respective outputs of the input-side flip-flop circuits adjacent to the corresponding flip-flop circuit, and the input (A) is connected to the bit adjacent to the corresponding bit. A memory control circuit connected to an output flip-flop circuit and comprising a combinational logic circuit for supplying a logical output (E) in which a bit error of an input (C) is corrected to a corresponding output flip-flop. 5. The memory control circuit according to claim 1, wherein said memory control circuit sends each address signal from said write control unit and said read control unit to said remaining amount detection unit. A memory control circuit, comprising: decoding means for decoding to a predetermined form of an address signal in which one bit takes a value of "1" for comparison and supplying the address signal to the remaining amount determination unit. 6. The memory control circuit according to claim 5, wherein said read clock includes a clock generated at a speed twice or more as high as said write clock, and said decoding means outputs a signal having a value of 10 or more. When representing a decimal "0", the respective bit values are A0 = 1, A1 to AN = 0, and when the address signal represents a decimal "1", A0 = 0, A
1 = 1, A2 to AN = 0, and the address signal becomes A0 to A (N-1) = 0, AN = 1 when the address signal represents decimal "N"
A memory control circuit characterized by decoding to A0 to AN. 7. The memory control circuit according to claim 5, wherein said read clock includes a clock supplied at a speed of M times or more higher than said write clock, and said decoding means outputs a signal having a value of 10 or more. Hexadecimal "0" ~ "
M ", each bit value is A0 = 1, A1 ~ A
When N = 0 and the address signal represents the decimal number "M + 1" to "2M", A0 = 0, A1 = 1, A2 to AN = 0 and the address signal becomes 10
A0, A1 = 0, A2 = 1, A3-when representing base 2M + 1 to 3M
AN = 0, and the address signal is in decimal "(N-1) M + 1" to "NM"
A memory control circuit for decoding to address signals A0 to AN having values of A0 to A (N-1) = 0 and AN = 1 when expressed by: