JP4569163B2 - Data input / output device and data input / output method - Google Patents

Description

  The present invention relates to a data input / output device that includes a first-in first-out (FIFO) memory and temporarily outputs input data after being stored in the FIFO memory, and a data input / output method in the data input / output device.

  The FIFO memory is used, for example, to realize data transfer between two bus systems having different transfer speeds. That is, in order to absorb the difference in transfer speed between the two buses, data is temporarily written in the FIFO memory, the written data is read from the FIFO memory, and the data is output to the output side bus.

  In Patent Document 1, in a data input / output device using a FIFO memory, a write address pointer indicates whether or not a predetermined number of data is written in the FIFO memory in order to increase data transfer efficiency and data bus use efficiency. And a read address pointer, and a data transfer request is generated until a predetermined number of data written in the FIFO memory becomes empty. Further, it is determined whether or not there is room for writing a predetermined number or more of data in the FIFO memory, and a data write request is generated until the FIFO memory is full.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique that enables continuous data writing even in a data input / output device using a single port memory that performs data writing and reading at the same port.

JP-A-6-187123 JP 2003-271378 A

  However, when data is written to and read from a memory in which single-port memories or FIFO memories are connected in multiple stages, data may not be output due to a delay generated in the memory. That is, when data is written in a memory in which a single port memory or FIFO memory is connected in multiple stages, it takes time to output the data because of the multistage configuration. Therefore, even if a read request signal is issued immediately after data is written, this data cannot be read.

For example, if one word of data is written in a FIFO memory in which five FIFO memories are connected in multiple stages, and a data read request is generated at the written location, the data can be read with a delay corresponding to the connected multiple stages, so the data can be read out. There may not be.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a data input / output device capable of reliably reading data even in a FIFO memory that causes a delay from data writing to data reading. To do.

In order to achieve this object, the data input / output device according to claim 1 includes a multi-stage FIFO memory, and sequentially records the input data from the first-stage FIFO memory to the subsequent-stage FIFO memory, and from the last-stage FIFO memory. A data input / output device for reading and outputting data, the input data number counting means for counting the number of data input to the multi-stage FIFO memory, and the number of output data for counting the number of data output from the multi-stage FIFO memory First determination means for determining whether or not a predetermined number or more of data is recorded in the multi-stage FIFO memory based on the count number of the count means, and the input data number count means and the output data number count means As a result of the determination by the first determination means, a predetermined number of data is recorded in the multi-stage FIFO memory. It is the determination result that is not, in the case where the predetermined number or more of data is changed to the determination result that has been recorded, based on an instruction of the count start sent from the first determining means, said multi-stage FIFO From the first delay means that counts the delay count number according to the number of memory stages, and the determination result of the first determination means that the determination result that the predetermined number or more data is not recorded in the multi-stage FIFO memory, wherein the predetermined number or more of data is changed to the determination result that has been recorded, after the first delay means has counted the number of the delay count, the read permission means for permitting the reading of data from the multi-stage FIFO memory And continuously reading data from the multi-stage FIFO memory .

In the first aspect of the invention, the first determination means determines whether or not a predetermined number of data is recorded in the multi-stage FIFO memory, and the determination result indicates that the predetermined number of data or more is not recorded. If the determination result is changed to a determination result indicating that more than a predetermined number of data is recorded, data reading from the multi-stage FIFO memory is permitted after the count of the delay count, so the multi-stage FIFO memory The data can be read continuously from .

In the data input / output device, when the read permission unit inputs a data end signal indicating the end of data to be input to the multistage FIFO memory , the determination result of the first determination unit is the result of the multistage FIFO memory. to be the determination result of the yarn a predetermined number or more of data is not been recorded, the by first counting the number of delay count delay means, when the first delay means for counting the number of the delay count, the multi-stage It is preferable to allow data read from the FIFO memory.

According to the second aspect of the present invention , even if a predetermined number of data or more is not recorded in the multistage FIFO memory, the data can be reliably read from the multistage FIFO memory.

In the data input / output device, it is determined whether or not a predetermined number of data can be recorded in the multi-stage FIFO memory based on the count numbers of the input data number counting means and the output data number counting means. Second determination means, second delay means for counting a delay count number corresponding to the number of stages of the multi-stage FIFO memory, and a determination result of the second determination means is greater than the predetermined number in the multi-stage FIFO memory. When the determination result that data recording is impossible is changed to the determination result that data recording of the predetermined number or more is possible, the second delay means counts the delay count number, and the delay count number Recording permission means for permitting the recording of data in the multi-stage FIFO memory after counting.

According to the third aspect of the present invention, when the determination result that the predetermined number or more of data cannot be recorded in the multi-stage FIFO memory is changed to the determination result that the predetermined number or more of data can be recorded. Since the data input to the multistage FIFO memory is performed after the count of the delay counts, it is possible to reliably record a predetermined number or more of data in the multistage FIFO memory.

In the data input / output device, the multi-stage FIFO memory may be a synchronous FIFO memory or an asynchronous FIFO memory.

The data input / output method according to the present invention includes a multi-stage FIFO memory, and sequentially records input data from a first-stage FIFO memory to a subsequent-stage FIFO memory, and reads and outputs data from the last-stage FIFO memory. A data input / output method for a device, the step of counting the number of data input to the multi-stage FIFO memory, the step of counting the number of data output from the multi-stage FIFO memory, and the input / output to the multi-stage FIFO memory Determining whether or not a predetermined number of data is recorded in the multi-stage FIFO memory based on the count number of data to be processed, and the result of the determination is a predetermined number or more in the multi-stage FIFO memory The determination that no data is recorded is changed to the determination that more than the predetermined number of data is recorded. Once the steps of counting the number of delay count corresponding to the number of stages of the FIFO memory of the multi-stage, after the count of the delay count, and a step of permitting the data read from the multi-stage FIFO memory, wherein It is characterized by executing continuous reading of data from a multi-stage FIFO memory.

  When the FIFO memory is composed of a single-port RAM and a FIFO memory in which a plurality of FIFO memories are connected in multiple stages as in the invention described in claim 6, data output is delayed. The data input / output device according to any one of claims 1 to 4 can reliably read data and write data.

  According to the present invention, even if the FIFO memory causes a delay from data writing to reading, the written data can be read reliably.

  Next, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

  First, the configuration on the reading side of the data input / output device 1 will be described with reference to FIG. As shown in FIG. 1, a RAM controller 2, a 1-port RAM 3, and a read timing control unit 20 are provided on the read side of the data input / output device 1.

As shown in FIG. 1, data (also referred to as Data) is input to the RAM controller 2 in accordance with a write signal (hereinafter also referred to as WE). Further, data is output from the 1-port RAM 3 to the RAM controller 2 in accordance with a read signal (hereinafter also referred to as RE). When the 1-port RAM 3 is full and new data cannot be written, the RAM controller 2 outputs a full flag (hereinafter also referred to as FULL) indicating that the 1-port RAM 3 is full. Further, when data cannot be read when the 1-port RAM 3 is empty, an empty flag (hereinafter also referred to as EMP) indicating that the 1-port RAM 3 is empty is output.

The read timing control unit 20 determines whether or not a predetermined number of data has been written in the 1-port RAM 3, and if a predetermined number or more of data has been written, a read permission that permits reading after a predetermined time has elapsed. Set the flag.

  Next, the configuration of the read timing control unit 20 will be described with reference to FIG. As shown in FIG. 2, the read timing control unit 20 includes a write counter 21, a comparison circuit 22, a read counter 23, a delay counter 24, and a read permission flag generation circuit 25.

  The write counter 21 counts the number of data written to the 1-port RAM 3 (hereinafter referred to as the number of write data) based on the write signal (WE) and the full flag from the RAM controller 2. Similarly, the read counter 23 counts the number of data read from the 1-port RAM 3 (hereinafter referred to as the number of read data) by the read signal (RE) and the empty flag from the RAM controller 2.

  The comparison circuit 22 subtracts the read data number of the read counter 23 from the write data number of the write counter 21 and outputs the data count value of the subtraction result to the read permission flag generation circuit 25.

The read permission flag generation circuit 25 reads a read word number indicating the number of words read continuously from the 1-port RAM 3 (hereinafter also referred to as RSIZE) and a read delay count number (hereinafter also referred to as RDELAY) to be counted by the delay counter 24. ) to enter and.

  The read permission flag generation circuit 25 compares the subtraction result obtained by subtracting the read data number of the read counter 23 from the write data number of the write counter 21 with the read word number (RSIZE). The number of read words (RSIZE) is a determination value for determining whether or not a predetermined number of data can be read from the 1-port RAM 3. When the subtraction result obtained by subtracting the read data number of the read counter 23 from the write data number of the write counter 21 becomes larger than the read word number (RSIZE), data of the read word number (RSIZE) or more can be read from the 1-port RAM 3. Judge that it is possible. When the read permission flag generation circuit 25 determines that data of a predetermined number (RSISE) or more can be read, the delay counter 24 counts a predetermined count number and then reads a read permission flag for permitting reading from the 1-port RAM 3. Set to 1.

  The delay counter 24 starts a delay count in response to a count start instruction signal from the read permission flag generation circuit 25. The read delay count number (RDELAY) counted by the delay counter 24 is instructed from the read permission flag generation circuit 25 in advance. The delay counter 24 outputs the count value to the read permission flag generation circuit 25.

  Next, the data write and read timing control of the read permission flag generation circuit 25 will be described with reference to the signal output timing chart shown in FIG. Data is input to the RAM controller 2 in accordance with a write signal (WE) generated in synchronization with the reference clock (WCLK). The RAM controller 2 sequentially writes data (Data) to the address (Waddr shown in FIG. 3) of the 1-port RAM 3.

  The read timing controller 20 uses the write counter 21 and the read counter 23 to count the number of data written to the 1-port RAM 3 and the number of read data, and whether or not a predetermined number of data is written in the 1-port RAM 3. Detect whether or not. The comparison circuit 22 subtracts the count number of the read counter 23 from the count number of the write counter 21 and outputs the subtraction result to the read permission flag generation circuit 25.

  The read permission flag generation circuit 25 compares the data count value obtained by subtracting the read data number of the read counter 23 from the write data number of the write counter 21 with the read word number (RSIZE). If the data count value is smaller than the number of read words (RSIZE), a predetermined number (RSIZE) of data cannot be read from the 1-port RAM 3, and the read permission flag is kept at the low level (0). If the subtraction result is larger than the number of read words (RSIZE), it is determined that data of a predetermined number (RSIZE) or more has been written in the 1-port RAM 3, and a count disclosure instruction for instructing the delay counter 24 to start delay counting Output a signal.

  The delay counter 24 starts a delay count in response to a count start instruction signal from the read permission flag generation circuit 25. The read delay count number (RDELAY) counted by the delay counter 24 is instructed from the read permission flag generation circuit 25 in advance.

  When the read permission flag generation circuit 25 counts the read delay count number (RDELAY) (count number C shown in FIG. 3) by the delay counter 24, the read permission flag is set to a high level (1) and the 1-port RAM 3 Allow reading of data.

  When the read permission flag transitions to the high level, data (Data) is output from the 1-port RAM 3 to the RAM controller 2 in accordance with the input of the read signal (RE) generated in synchronization with the reference clock (WCLK). The RAM controller 2 sequentially outputs the input data (Data).

  For example, when a 1-word data read request is issued when 1 word is written in the 1-port RAM 3, the written data is not immediately output. Therefore, even if one word is read, one word of data cannot be read. In this embodiment, when it is determined that a predetermined number or more of data is written in the 1-port RAM 3, the delay counter 24 counts a predetermined time and then reads the data. For this reason, the data written in the 1-port RAM 3 can be read reliably.

  The present embodiment can be applied to a data input / output device having a configuration in which a plurality of FIFO (First In First Out) memories 4, 5, and 6 are connected in multiple stages as shown in FIG. Although not shown, the present invention can also be applied to a memory unit including a single port RAM 3 and a multistage FIFO. The FIFO memory may be a synchronous type that performs data input and output in synchronization, or may be an asynchronous type that performs data input and output asynchronously.

  It should be noted that the read delay count number (RDELAY) of the delay counter 24 is set in consideration of the delay time required until the data read in the 1-port RAM 3 in the configuration using the 1-port RAM 3 shown in FIG. Further, in the case of a memory unit having a configuration in which the FIFO memories 4, 5, and 6 shown in FIG. 4 are connected in multiple stages, the setting can be made according to the number of FIFO memories connected in multiple stages. Of course, in the case of a memory unit composed of 1-port RAM 3 and multi-stage FIFO memories 4, 5 and 6, the delay time required for data reading that occurs in 1-port RAM 3 and the number of stages of FIFO memories connected in multi-stages It can be set accordingly.

  In this embodiment, the read delay count number (RDELAY) of the delay counter 24 and the data number (RSIZE) that can be continuously read from the 1-port RAM 3 can be arbitrarily set from the outside. The software writes the read delay count number (RDELAY) and the data number (RSIZE) to a register (not shown), and notifies the read timing control unit 20 of the register value by the host device.

  Next, the configuration of the second embodiment will be described with reference to FIG. FIG. 5 shows the configuration on the writing side of the data input / output device 1 of this embodiment. The data input / output device 1 shown in FIG. 5 includes a RAM controller 2 that controls writing and reading of data to and from the 1-port RAM 3, a 1-port RAM 3 that performs writing and reading of data through the same port, and a 1-port RAM 3 A write timing control unit 10 for determining whether or not there is room for writing a predetermined number or more of data and setting a write permission flag that permits writing after a predetermined time if there is room for writing a predetermined number or more of data. have.

  Next, the configuration of the write timing control unit 10 will be described with reference to FIG. As shown in FIG. 6, the write timing control unit 10 includes a write counter 11, a comparison circuit 12, a read counter 13, a delay counter 14, and a write permission flag generation circuit 15.

  The write counter 11 counts the number of data written to the 1-port RAM 3 (hereinafter referred to as the number of write data) by the write signal (WE) and the full flag from the RAM controller 2. Similarly, the read counter 13 counts the number of data read from the 1-port RAM 3 (hereinafter referred to as the number of read data) by the read signal (RE) and the empty flag from the RAM controller 2.

  The comparison circuit 12 subtracts the number of read data of the read counter 13 from the number of write data of the write counter 11 and outputs the data count value of the subtraction result to the write permission flag generation circuit 15.

The write permission flag generation circuit 15 includes a write word number indicating the number of words continuously written in the 1-port RAM 3 (hereinafter also referred to as WSIZE) and a write delay count number (hereinafter also referred to as WDELAY) to be counted by the delay counter 14. ) to enter and.

  The write permission flag generation circuit 15 subtracts the data count value of the comparison circuit 12 from the memory size of the 1-port RAM (hereinafter referred to as TSIZE), and compares the subtraction result with the number of write words (WSIZE). The number of write words (WSIZE) indicates the number of data to be written in the 1-port RAM 3, and is a determination value for determining whether there is room for writing a predetermined number or more of data in the 1-port RAM 3. When the value obtained by subtracting the data count value from TSIZE becomes larger than the number of write words (WSIZE), it can be determined that there is room for writing data of the number of write words (WSIZE) or more in the 1-port RAM 3. When the write permission flag generation circuit 15 determines that there is room for writing a predetermined number (WSIZE) of data, the write permission flag for permitting writing to the 1-port RAM 3 after the delay counter 14 counts the predetermined count number. Is set to 1.

  The delay counter 14 starts a delay count in response to a count start instruction signal from the write permission flag generation circuit 15. The write delay count number (WDELAY) counted by the delay counter 14 is instructed from the write permission flag generation circuit 15 in advance. The delay counter 14 outputs the count value to the write permission flag generation circuit 15.

  Next, data write and read timing control of the write timing control unit 10 will be described with reference to a signal output timing chart shown in FIG. The data (Data) of the input address (Raddr shown in FIG. 7) is output from the 1-port RAM 3 to the RAM controller 2 in accordance with the read signal (RE) generated in synchronization with the reference clock (hereinafter also referred to as WCLK). To do. The RAM controller 2 sequentially outputs the input data (Data) (DO shown in FIG. 7).

  The write timing control unit 10 uses the write counter 11 and the read counter 13 to count the number of data written to the 1-port RAM 3 and the number of read data, and there is room for writing a predetermined number or more of data in the 1-port RAM 3. Whether or not is detected. The comparison circuit 12 subtracts the count number of the read counter 13 from the count number of the write counter 11 and outputs the data count value of the subtraction result to the write permission flag generation circuit 15.

  The write permission flag generation circuit 15 subtracts the data count value of the comparison circuit 12 from the memory size TSIZE of the 1-port RAM 3. Next, the subtraction result is compared with the number of write words (WSIZE). If the subtraction result is smaller than the number of write words (WSIZE), it is assumed that there is no room for writing data of a predetermined number (WSIZE) or more in the 1-port RAM 3, and the write permission flag is kept at the low level (0). . If the subtraction result is larger than the number of written words (WSIZE), it is determined that there is room for writing data of a predetermined number (WSIZE) or more in the 1-port RAM 3, and the count for instructing the delay counter 14 to start delay counting is determined. A start instruction signal is output.

  The delay counter 14 starts a delay count in response to a count start instruction signal from the write permission flag generation circuit 15. The write delay count number (WDELAY) counted by the delay counter 14 is instructed from the write permission flag generation circuit 15 in advance.

  When the write permission flag generation circuit 15 counts the write delay count number (WDELAY) (count number C shown in FIG. 7) by the delay counter 14, the write permission flag is set to a high level and the data to the 1-port RAM 3 is transferred. Allow writing.

  When the write permission flag transitions to the high level, data (Data) is input to the RAM controller 2 in accordance with the input of the write signal (WE) generated in synchronization with the reference clock (WCLK). The RAM controller 2 sequentially writes the input data (Data) to the 1-port RAM 3.

  As described above, in this embodiment, when it is determined that there is room for writing a predetermined number (WSIZE) or more of data in the 1-port RAM 3, data writing to the 1-port RAM 3 is permitted after a predetermined time (WDELAY) has elapsed. Since data writing is permitted after a predetermined time has elapsed, a predetermined number of data can be reliably written.

  This embodiment can also be applied to a data input / output device having a configuration in which a plurality of FIFO (First In First Out) memories 4, 5, and 6 are connected in multiple stages as shown in FIG. Although not shown, the present invention can also be applied to a memory unit including a single port RAM 3 and a multistage FIFO. The 1-port RAM 3 and the FIFO memories 4, 5, and 6 may be of a synchronous type in which data input and output are performed synchronously, or asynchronously in which data input and output are performed asynchronously. It may be.

  In the configuration using the 1-port RAM 3 shown in FIG. 1, the write delay count number (WDELAY) of the delay counter 14 is set in consideration of the delay time taken until the data is read in the 1-port RAM 3. Further, in the case of a memory unit having a configuration in which the FIFO memories 4, 5, and 6 shown in FIG. 8 are connected in multiple stages, the setting can be made according to the number of FIFO memories connected in multiple stages. Of course, in the case of a memory unit composed of 1-port RAM 3 and multi-stage FIFO memories 4, 5 and 6, the delay time required for data reading that occurs in 1-port RAM 3 and the number of stages of FIFO memories connected in multi-stages It can be set accordingly.

  In this embodiment, the write delay count number (WDELAY) of the delay counter 14 and the data number (WSIZE) continuously written in the 1-port RAM 3 can be arbitrarily set from the outside. The software writes the write delay count number (WDELAY) and the data number (WSIZE) to a register (not shown), and notifies the write timing control unit 10 of the register value in the host device.

  This embodiment provides a configuration that can reliably read from the 1-port RAM 3 even if the last write data is fractional data less than a predetermined number. In this embodiment, as shown in FIGS. 9 and 10, an end signal (WEND) indicating the last write data from the write side is input to the read permission flag generation circuit 25 of the read timing control unit 20. As shown in the timing chart of FIG. 11, when the end signal (WEND) is input, the read permission flag generation circuit 25 forcibly forces even if the number of data written in the 1-port RAM 3 is less than a predetermined number. A count start instruction signal is output to the delay counter 24. When the delay counter 24 counts the read delay count (RDELAY), the read timing control unit 20 sets the read permission flag to a high level.

  As the read permission flag transits to a high level, data (Data) is output from the 1-port RAM 3 to the RAM controller 2 in accordance with the input of the read signal (RE).

  In this way, in this embodiment, even if the data is fractional data less than the predetermined number, it can be reliably read from the 1-port RAM 3.

  The present embodiment also provides a configuration that can reliably read from the 1-port RAM 3 even if the last write data is fractional data that is less than a predetermined number as in the third embodiment. In this embodiment, as shown in FIG. 12, when an end signal (WEND) indicating the last write data is input from the write side, the read timing control unit 20 delays the end signal for a predetermined time. Output to the output side. Here, a signal obtained by delaying the end signal by a predetermined time is referred to as a second end signal (also referred to as WEND2).

  FIG. 13 shows the configuration of this embodiment. In this embodiment, as shown in FIG. 13, a write end flag generation unit 26 for inputting an end signal (WEND) from the write side and a second delay counter 27 for counting a delay time are newly provided. As shown in FIG. 13, the write end flag generator 26 receives a read delay count (RDELAY) and an end signal (WEND). The write end flag generator 26 causes the second delay counter 27 to start a count operation when the signal level of the end signal (WEND) transitions (transitions to a high level). When the read delay count number (RDELAY) is counted by the second delay counter 27, the write end flag generator 26 outputs the second end signal (WEND2) to the output side. When the second end signal (WEND2) is output, the read operation is forcibly executed.

  As described above, even in this embodiment, even if the data is fractional data less than the predetermined number, it can be reliably read from the 1-port RAM 3.

  In the data input / output devices of the first to fourth embodiments described above, for example, as shown in FIG. 14, the data input to the line buffer 31 of the image input unit 30 of the image forming apparatus and the FIFO memory 34 of the image output unit 33 are performed. Used for input / output control. For example, the image data recorded in the memory 35 is decompressed by the image decompression processing unit 32, and the processed signal is input to the data input / output device of the image output unit 33 via the bus and the data to the FIFO memory 34 is input. Write and read.

  The above-described embodiment is a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention. For example, in the above-described embodiment, the write signal (WE) and the read signal (RE) are generated from the same reference clock (WCLK), and thus the signals have the same frequency, but the write signal (WE) And the read signal (RE) may be signals having different frequencies. In this case, the write delay count number (WDELAY) and the read delay count number (RDELAY) are determined based on the signal frequencies of the write signal (WE) and the read signal (RE).

FIG. 3 is a block diagram illustrating a configuration of a read side of the data input / output device according to the first exemplary embodiment. 3 is a block diagram illustrating a configuration of a read timing control unit 20 according to the first embodiment. FIG. FIG. 3 is a signal output timing diagram illustrating data read timing according to the first exemplary embodiment. It is a block diagram which shows the other structure of the read side of a data input / output device. FIG. 10 is a block diagram illustrating a configuration on a write side of a data input / output device according to a second embodiment. FIG. 6 is a block diagram illustrating a configuration of a write timing control unit 10 according to a second embodiment. FIG. 10 is a signal output timing diagram illustrating data write timing according to the second exemplary embodiment. It is a block diagram which shows the other structure of the write side of a data input / output device. FIG. 10 is a block diagram illustrating a configuration of a read side of a data input / output device according to a third embodiment. FIG. 10 is a block diagram illustrating a configuration of a read timing control unit 20 according to a third embodiment. FIG. 10 is a signal output timing diagram illustrating data read timing according to the third embodiment. FIG. 10 is a block diagram illustrating another configuration of the read side of the data input / output device of the fourth embodiment. FIG. 10 is a block diagram illustrating another configuration of the read timing control unit 20 according to the fourth embodiment. 1 is a diagram illustrating an image forming apparatus equipped with a data input / output device.

Explanation of symbols

1 Data Input / Output Device 2 RAM Controller 3 1 Port RAM 4, 5, 6 FIFO
DESCRIPTION OF SYMBOLS 10 Write timing control part 11, 21 Write counter 12, 22 Comparison circuit 13, 23 Read counter 14, 24 Delay counter 15 Write permission flag generation circuit 20 Read timing control part
25 read permission flag generation circuit 26 write end flag generation unit 27 second delay counter

Claims (6)

A data input / output device comprising a multi-stage FIFO memory, sequentially recording input data from a first-stage FIFO memory to a subsequent-stage FIFO memory, and reading and outputting data from the last-stage FIFO memory,
Input data number counting means for counting the number of data input to the multi-stage FIFO memory;
Output data number counting means for counting the number of data output from the multi-stage FIFO memory;
First determination means for determining whether or not a predetermined number or more of data is recorded in the multi-stage FIFO memory based on the count numbers of the input data number counting means and the output data number counting means;
The determination result of the first determination means is changed from a determination result that a predetermined number or more data is not recorded in the multistage FIFO memory to a determination result that the predetermined number or more data is recorded . A first delay unit that counts a delay count according to the number of stages of the multi-stage FIFO memory based on a count start instruction sent from the first determination unit .
The determination result of the first determination means is changed from a determination result that a predetermined number of data is not recorded in the multi-stage FIFO memory to a determination result that the predetermined number of data is recorded. , after the first delay means has counted the number of the delay count, a read permission means for permitting the reading of data from the multi-stage FIFO memory,
A data input / output device for continuously reading data from the multi-stage FIFO memory . When the read permission unit inputs a data end signal indicating the end of data to be input to the multi-stage FIFO memory , the determination result of the first determination unit indicates that a predetermined number or more of data is stored in the multi-stage FIFO memory. even recorded have such yarn determination result, the first is counting the number of delay count delay means, wherein the first delay means for counting the number of the delay count, the data read out from said multi-stage FIFO memory 2. The data input / output device according to claim 1, wherein the data input / output device is permitted. Second determination means for determining whether a predetermined number or more of data can be recorded in the multi-stage FIFO memory based on the count numbers of the input data number counting means and the output data number counting means;
Second delay means for counting a delay count according to the number of stages of the multi-stage FIFO memory;
The determination result of the second determination means is changed from the determination result that the predetermined number of data or more cannot be recorded to the multistage FIFO memory to the determination result that the predetermined number or more of data can be recorded. Then, recording permitting means for allowing the second delay means to count the delay count number, and permitting data recording to the multi-stage FIFO memory after counting the delay count number;
The data input / output device according to claim 1 or 2, characterized by comprising:   4. The data input / output device according to claim 1, wherein the multi-stage FIFO memory is a synchronous FIFO memory. 5.   4. The data input / output device according to claim 1, wherein the multi-stage FIFO memory is an asynchronous FIFO memory. 5. A data input / output method for a data input / output device comprising a multi-stage FIFO memory, sequentially recording input data from a first-stage FIFO memory to a subsequent-stage FIFO memory, and reading and outputting data from the last-stage FIFO memory. ,
Counting the number of data input to the multi-stage FIFO memory;
Counting the number of data output from the multi-stage FIFO memory;
Determining whether or not a predetermined number or more of data is recorded in the multi-stage FIFO memory based on a count number of data input to and output from the multi-stage FIFO memory;
When the result of the determination is changed from determination that a predetermined number of data or more is not recorded in the multistage FIFO memory to determination that the predetermined number or more of data is recorded, the multistage FIFO Counting a delay count according to the number of stages of the FIFO memory;
And a step of permitting data reading from the multi-stage FIFO memory after counting the delay count number, and continuously reading data from the multi-stage FIFO memory .

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