JPS6446829A - First-in/first-out memory - Google Patents

Abstract

PURPOSE:To realize a high-speed access to a multi-stage first-in/first-out FIFO memory by transmitting the input data at a high speed up to an output in a fixed time regardless of the number of stages of the FIFO memory that are independently decided by the number of input data writable memory means. CONSTITUTION:A 1st counter 34 is provided to perform its counting operation with a write request signal 42 and designates a writing subject memory means for input data 41, together with a 2nd counter 35 which performs its counting operation with read request signal 44 and designates a reading subject memory means, a selector 36, and a sequence control circuit 37. Then the data stored in one of memory means 30-0-31-7 is selected and delivered via the selector 36 in the form of the output data 45 given from an FIFO memory in accordance with the contents of the counter 35. At the same time, an output ready signal 46 and an input ready signal 47 that show the internal state of the FIFO memory are outputted via the circuit 37 in accordance with the contents of both counters 34 and 35. Thus an access is possible at a high speed to a multi-stage FIFO memory.