KR0173012B1 - Frame data conversion circuit - Google Patents

Abstract

The frame data conversion circuit of the present invention converts five frame data composed of 24 channels into four frame data composed of 32 channels.

According to the present invention, five serial / parallel shift registers 20 to 24 are paralleled by one byte in accordance with a clock signal 2048CLK of 24 channel five frame data (1T1, 2T1, 3T1, 4T1, 5T1) inputted in series. Data is converted into data and stored in four 64-byte buffers (40 to 43) according to the output signals of the five recording position counters (30 to 34) that count the clock signal (1/8 CLK) divided by 1/8. 5 parallel / serial shifts by outputting the data stored in the buffers 40 to 43 according to the output signals of the five read position counters 50 to 53 that count the clock signal (1/8 CLK) divided by 1/8. A clock signal (1/3 divided by 1/32 for writing and reading the buffers 40 to 43) and outputting the four frame data (1E1, 2E1, 3E1, 4E1) composed of 32 channels and input to the registers 60 to 63. 1/32 CLK), so that the recording position counters 30 to 34 and the reading position counters 50 to 53 do not access the buffers 40 to 43 at the same time. / 4CLK) to prevent the five recording position counters 30 to 34 from accessing one buffer 40 to 43 at the same time.

Description

Frame data conversion circuit

1 is a data conversion circuit diagram of the present invention.

(A)-(e) of FIG. 2 are operation waveform diagrams of each part of FIG.

3A to 3F show the state of data converted by the data conversion circuit of the present invention.

* Explanation of symbols for main parts of the drawings

10: Divider 20 ~ 24: Serial / Parallel Shift Register

30 ~ 34: Record position counter 40 ~ 43: Buffer

50 ~ 53: Read position counter 60 ~ 63: Parallel / serial shift register

FS: control signal

2048CLK, 1 / 4CLK, 1 / 8CLK, 1 / 32CLK: Clock Signal

1T1, 2T1, 3T1, 4T1, 5T1: 32 channel frame data

1E1, 2E1, 3E1, 4E1: 32 channel frame data

The present invention relates to a frame data conversion circuit for converting five frame data having 24 channels into four frame data having 32 channels.

In general, the TPT relay line, which is a CEPT method, is composed of five frame data of 24 channels, and the E1 relay line, which is an NA method, is composed of four frame data of 32 channels.

In order to be able to transmit such frame data of the T1 relay line and the E1 relay line, frame data must be matched.

That is, five frame data of 24 channels of the T1 trunk line should be converted into four frame data of 32 channels, and four frame data of 32 channels of the E1 trunk line should be converted into 5 frame data of 24 channels.

To this end, in the past, an integrated device dedicated to time switches was used at a portion where a T1 repeater line and an E1 repeater line were matched. However, an integrated device dedicated to a time switch is not only expensive but also requires a large number of products. In addition, the size of the printed circuit board is increased, which has a lot of problems in miniaturization of the product.

Therefore, an object of the present invention is to provide a frame data conversion circuit for converting five frame data composed of 24 channels into four frame data composed of 32 channels without using an integrated device dedicated to a time switch.

According to the present invention having the above-described purpose, five serial / parallel shift registers are outputted by converting five serial / parallel shift registers into one-byte data in parallel according to a clock signal. The output data is stored in four 64 byte buffers according to the output signals of the five recording position counters that count the clock signals divided by 1/8. The data stored in the buffer counts the clock signals divided by 1/8. It is output in accordance with the output signals of the four read position counters and converted into input and serial data in four parallel / serial shift registers.The write position counter and read out are controlled by controlling the writing and reading of the buffer with 1/32 divided clock signals. Do not allow the position counter to access the buffer at the same time, and five recording position counters can be operated simultaneously It is characterized by preventing access to the buffer.

Hereinafter, the frame data conversion circuit of the present invention will be described in detail with reference to the accompanying drawings.

1 is a data conversion circuit diagram of the present invention, as shown therein, by dividing the clock signal 2048CLK by 1/4, 1/8 and 1/32 while being cleared according to the control signal FS. A divider 10 that outputs 18CLK, 1 / 32CLK, and 24 channel frame data 1T1, 2T1, 3T1, 4T1, 5T1 of the T1 repeater line according to the clock signal 2048CLK, Serial / parallel shift registers 20 to 24 outputting in parallel by one byte according to (8CLK), and a recording position counter that clears the clock signal (1 / 8CLK) and specifies a recording position by clearing it according to the control signal FS. (30 to 34), and the recording position counter (30 to 34) designates the output signal of the serial / parallel shift registers (20 to 24) as the recording / reading state is converted in accordance with the clock signal (1 / 32CLK). The 64-byte buffers 40 to 43 stored in the position and the control signal FS are cleared and the clock signal 1 / 8CLK is counted. Read position counters 50 to 53 for reading the stored data by designating the read positions of the buffers 40 to 43, and the read data of the buffers 40 to 43 are input in accordance with the clock signal 1/8 CLK. It consists of parallel / serial shift registers 60 to 63 which output 32 channel frame data 1E1, 2E1, 3E1, and 4E1 in series by shifting in accordance with the clock signal 2048CLK.

The frame data conversion circuit of the present invention configured as described above has the frequency divider 10, the recording position counters 30 to 34, and the reading position counter according to the control signal FS input as shown in FIG. 50 to 53 are cleared to an initial state, and the input clock signal 2048CLK is divided into 1/4, 1/8 and 1/32 in the frequency divider 10 as shown in FIG. As shown in (c) to (e) of FIG. 2, clock signals 1 / 4CLK, 1 / 8CLK and 1 / 332CLK are output.

In this state, when five frame data (1T1, 2T1, 3T1, 4T1, 5T1) having 24 channels of the T1 relay line are input, the five frame data (1T1, 2T1, 3T1, 4T1, 5T1) are inputted. Each of them is inputted to the serial / parallel shift registers 20 to 24 according to the clock signal 2048CLK, and shifted. The buffers are outputted in parallel by 8 bits by 1 byte according to the clock signal (1 / 8CLK) output by the divider 10. 40 to 43, respectively.

The recording position counters 30 to 33 count the clock signal (1/8 CLK), output the count value to the recording position, and apply it to the buffers 40 to 43, so that the buffers 40 to 43 are serial / parallel shift registers. The output data of (20 to 23) are sequentially recorded at the recording positions designated by the recording position counters 30 to 33, and the recording position counter 34 counts the clock signal (1/8 CLK) and records the count value. Since the data is output to the position and applied to the buffers 40 to 43, the buffers 40 to 43 divide the output data of the serial / parallel shift register 24 and sequentially write to the recording positions designated by the recording position counter 34. .

In this state, the read position counters 50 to 53 count clock signals 1 / 8CLK to designate the read positions of the buffers 40 to 43, so that the buffers 40 to 43 store the data stored at the designated read positions. Outputs

Then, the read data output by the buffers 40 to 43 is input to the parallel / serial shift registers 60 to 63 according to the clock signal 1 / 8CLK in accordance with the read position output by the read position counters 50 to 53. The data input to the parallel / serial shift registers 60 to 63 are output in series while being shifted according to the clock signal 2048CLK, that is, into four frame data (1E1, 2E1, 3E1, 4E1) having 32 channels. Is output.

Here, in the present invention, the recording position counters 30 to 34 and the recording position counters 50 to 53 must block access to the buffers 40 to 43 at the same time. The signal 1 / 32CLK is applied to the buffers 40 to 43 to control writing and reading.

The recording position counters 30 to 33 and the reading position counter 34 should be blocked from simultaneously accessing the buffers 40 to 43. In the present invention, the clock signal 1 divided by the clock signal 2048CLK is divided into quarters. / 4CLK) to the buffers 40 to 43 to control the reading, that is, to control the reading of the recording position counters 30 to 33 and the recording position counter 34 in accordance with the clock signal 1 / 4CLK, and the clock signal. If the value of counting (2048CLK) is not 4N (where N is 0, 1, 2, 3, ...), the count value of the recording position counters 30 to 34 is not increased and the previous data is output as it is. Let's do it.

Therefore, according to the present invention, five frame data (1T1, 2T1, 3T1, 4T1, 5T1) having 24 channels inputted as shown in (b) of FIG. 3 according to the time slot shown in (a) of FIG. ) Is converted into four frame data (1E1, 2E1, 3E1, 4E1) having 32 channels and output as shown in (c) to (f) of FIG.

As described above, the present invention converts and outputs five frame data having 24 channels into four frame data having 32 channels, thereby simplifying the circuit configuration and making it compact and lightweight, and an expensive time switch. The production cost can be reduced by not using a dedicated integrated device.

Claims (3)

A divider 10 for clearing the clock signal 2048CLK and dividing the clock signal 2048CLK by 1/4, 1/8 and 1/32 and outputting the clock signals 1 / 4CLK, 18CLK, 1 / 32CLK according to the control signal FS; And serial / parallel shift registers (20 to 24) that output 24 channel frame data (1T1, 2T1, 3T1, 4T1, 5T1) in parallel by one byte according to the clock signal (1 / 8CLK) while shifting the clock signal (2048CLK). And a recording position counter (30 to 34) for designating a recording position by counting the clock signal (1/8 CLK) while being cleared according to the control signal (FS), and the output of the serial / parallel shift registers (20 to 24). The 64-byte buffers 40 to 43 storing the signals stored in the recording positions designated by the recording position counters 30 to 34, and are cleared in accordance with the control signal FS, and the clock signal 1 / 8CLK is counted. A read position counter 50 to 53 for reading stored data by designating a read position of 40 to 43, and the read data of the buffers 40 to 43 to the clock signal 1/8 CLK. Frame data conversion circuit comprising a parallel / serial shift register (60 to 63) for inputting in parallel and outputting 32-channel frame data (1E1, 2E1, 3E1, 4E1) in series by shifting according to a clock signal (2084CLK). . 2. The recording position and reading position counters 50 to 4 according to claim 1, wherein the buffers 40 to 43 are converted into the recording / reading state in accordance with the clock signal 1 / 332KLK, and are output by the recording position counters 30 to 34. And frame data conversion circuit for recording and storing data at a read position output by 53). The buffers 40 to 43 according to claim 1 or 2, wherein the buffers 40 to 43 set the read timings of the read positions of the recording position counters 30 to 33 and the recording position counter 34 in accordance with the clock signal 1 / 4CLK. Frame data conversion circuit, characterized in that the separation.