KR970002611A

KR970002611A - Frame data conversion circuit

Info

Publication number: KR970002611A
Application number: KR1019950017961A
Authority: KR
Inventors: 김영구
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-06-28
Filing date: 1995-06-28
Publication date: 1997-01-28
Also published as: KR0173012B1

Abstract

본 발명의 프레임 데이타 변환회로는 24채널로 구성된 5개의 프레임 데이타를 32채널로 구성된 4개의 프레임 데이타로 변환하는 것이다.The frame data conversion circuit of the present invention converts five frame data composed of 24 channels into four frame data composed of 32 channels.

본 발명은 직렬로 입력되는 24채널 5개의 프레임 데이타(1T1,2T1,3T1,4T1,5T1)를 클럭신호(2048CLK)에 따라 5개의 직렬/병렬 시프트 레지스터(20~24)가 각기 1바이트씩 병렬 데이타로 변환하여 출력하고, 1/8분주한 클럭신호(1/8CLK)를 카운트하는 5개의 기록위치 카운터(30~34)의 출력신호에 따라 4개의 64바이트 버퍼(40~43)에 저장하며, 버퍼(40~43)에 저장한 데이타를 1/8분주한 클럭신호(1/8CLK)를 카운트하는 5개의 독출위치 카운터(50~53)의 출력신호에 다라 출력하여 5개의 병렬/직렬 시프트 레지스터(60~63)에 입력 및 32채널로 구성된 4개의 프레임 데이타(1E1,1E2,1E3,1E4)로 출력하게 하며, 버퍼(40~43)의 기록 및 독출을 1/32분주한 클럭신호(1/32CLK)로 제어하여 기록위치 카운터(30~34) 및 독출위치 카운터(50~53)가 버퍼(40~43)를 동시에 엑세스하지 않도록 하며, 1/4분주한 클럭신호(1/4CLK)를 이용하여 5개의 기록위치 카운터(30~34)가 동시에 하나의 버퍼(40~43)를 엑세스하지 못하도록 한다.According to the present invention, five serial / parallel shift registers 20 to 24 are paralleled by one byte in accordance with the clock signal 2048CLK. Data is converted into data and stored in four 64-byte buffers (40 to 43) according to the output signals of the five recording position counters (30 to 34) that count the clock signal (1/8 CLK) divided by 1/8. 5 parallel / serial shifts by outputting the data stored in the buffers 40 to 43 according to the output signals of the five read position counters 50 to 53 that count the clock signal (1/8 CLK) divided by 1/8. A clock signal (1/3 divided into two frame data (1E1, 1E2, 1E3, 1E4) composed of 32 channels and input to the registers 60 to 63 and divided by 1/32 of writing and reading of the buffers 40 to 43) 1 / 32CLK) to prevent the recording position counters 30 to 34 and the reading position counters 50 to 53 from simultaneously accessing the buffers 40 to 43, and the 1/4 divided clock signal (1/4 CLK). Used to be the five recording counter (30-34) at the same time preventing access to one buffer (40 to 43).

Description

Frame data conversion circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 데이타 변환회로도.1 is a data conversion circuit diagram of the present invention.

Claims

The frequency divider 10 outputs clock signals 1 / 4CLK, 1 / 8CLK and 1 / 3CLK by dividing the clock signals 2048CLK 1/4, 1/8 and 1/32 while being cleared according to the control signal FS. ) And a serial / parallel / shift register (1T1, 2T1, 3T1, 4T1, 5T1) that outputs in parallel one byte in accordance with the clock signal (1 / 8CLK) while shifting the 24-channel frame data (1T1, 2T1, 3T1, 4T1, 5T1) according to the clock signal (2048CLK). 20 to 24, recording position counters 30 to 34 for clearing according to the control signal FS and counting clock signals 1/8 CLK to designate a recording position, and the serial / parallel / shift registers 20 to 24; Buffers 40 to 43 for storing the output signal of the signal 24 at the recording positions designated by the recording position counters 30 to 34, and are cleared according to the control signal FS, and the clock signals 1/8 CLK are counted. Read position counters 50 to 53 for reading the stored data by designating the read positions of the buffers 40 to 43 and inputting the read data of the buffers 40 to 43 according to the clock signal (1/8 CLK). And a parallel / serial shift register (60 to 63) for shifting in accordance with a high clock signal (CLK) and outputting in series 32 channel frame data (1E1, 2E1, 3E1, 4E1).

2. The recording position and reading position counters 50 to 4 according to claim 1, wherein the buffers 40 to 43 are converted into the recording / reading state in accordance with the clock signal 1 / 332KLK, and are output by the recording position counters 30 to 34. And frame data conversion circuit for recording and storing data at a read position output by 53).

The buffers 40 to 43 according to claim 1 or 2, wherein the buffers 40 to 43 set the read timings of the read positions of the recording position counters 30 to 33 and the recording position counter 34 in accordance with the clock signal 1 / 4CLK. Frame data conversion circuit, characterized in that the separation.

※ Note: The disclosure is based on the initial application.