KR920000069A - Memory IC with Parallel and Serial Output Conversion - Google Patents

Memory IC with Parallel and Serial Output Conversion Download PDF

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Publication number
KR920000069A
KR920000069A KR1019900015248A KR900015248A KR920000069A KR 920000069 A KR920000069 A KR 920000069A KR 1019900015248 A KR1019900015248 A KR 1019900015248A KR 900015248 A KR900015248 A KR 900015248A KR 920000069 A KR920000069 A KR 920000069A
Authority
KR
South Korea
Prior art keywords
parallel
memory
data
serial output
output conversion
Prior art date
Application number
KR1019900015248A
Other languages
Korean (ko)
Inventor
가즈나리 이노우에
Original Assignee
시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시 뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR920000069A publication Critical patent/KR920000069A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

내용 없음No content

Description

병렬, 직렬 출력 변환기능을 내장하는 메모리 ICMemory IC with Parallel and Serial Output Conversion

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 이 발명의 한 실시예인 메모리 IC의 개략구성을 표시하는 도면,1 is a diagram showing a schematic configuration of a memory IC which is one embodiment of the present invention;

제2도는 이 발명의 한 실시예인 출력버퍼부의 구성의 한 예를 표시하는 도면,2 is a view showing an example of the configuration of an output buffer unit which is an embodiment of the present invention;

제3도는 제1도 및 제2도에 표시하는 회로의 동작을 표시하는 신호파형도.3 is a signal waveform diagram showing the operation of the circuit shown in FIG. 1 and FIG.

Claims (1)

복수비트 단위에서 액세스 가능한 메모리 셀 어레이 상기 메모리 셀 어레이로부터 상기 복수 비트단위에서 데이터를 판독하는 수단, 상기 데이터 판독수단의 판독한 데이터를 병렬로 받는 제1의 수단, 및 상기 제1의 수단이 받은 데이터를 직렬로 판독하여 출력하는 제2의 수단을 구비하고, 상기 제2의 수단은, 클럭신호를 받는 수단, 상기 클럭신호를 카운트 하는 수단 및 상기 카운트 수단의 출력에 응답하여 상기 제1의 수단의 받은 데이터를 순차 선택하여 출력하는 수단을 포함하고 병렬-직렬 출력변환 기능을 내장하는 메모리 IC.Memory Cell Array Accessible in Multiple Bit Units Means for reading data from the memory cell array in multiple bit units, first means for receiving the read data of the data reading means in parallel, and received by the first means. A second means for reading and outputting data in series, said second means comprising: means for receiving a clock signal, means for counting said clock signal, and said first means in response to an output of said counting means; And a means for sequentially selecting and outputting the received data of the memory, and having a built-in parallel to serial output conversion function. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900015248A 1989-09-26 1990-09-26 Memory IC with Parallel and Serial Output Conversion KR920000069A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24961689 1989-09-26
JP1-249616 1989-09-26

Publications (1)

Publication Number Publication Date
KR920000069A true KR920000069A (en) 1992-01-10

Family

ID=17195678

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900015248A KR920000069A (en) 1989-09-26 1990-09-26 Memory IC with Parallel and Serial Output Conversion

Country Status (2)

Country Link
KR (1) KR920000069A (en)
DE (1) DE4023002A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112290922B (en) * 2020-11-09 2024-05-14 无锡舜铭存储科技有限公司 Parallel input serial output circuit and memory using the same
CN116597878B (en) * 2023-07-17 2023-12-01 长鑫存储技术有限公司 Data processing circuit and memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62226498A (en) * 1986-03-28 1987-10-05 Hitachi Ltd Semiconductor memory device
JPH0740430B2 (en) * 1986-07-04 1995-05-01 日本電気株式会社 Memory device

Also Published As

Publication number Publication date
DE4023002A1 (en) 1991-04-25

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E902 Notification of reason for refusal
E601 Decision to refuse application