SU1610598A1 - Counting device - Google Patents

Abstract

The invention relates to computing and technology for the transmission of discrete messages. The purpose of the invention is to expand the functionality of the device by determining the current value of the ratio of the number of pulses in two pulse streams. To do this, a second summing counter, a second logic block accumulating a totalizer-subtractor, and a block of I. units are introduced into the device containing the first summing counter, the first logic block and the subtracting counter. posts. 4 ill., 1 tab.

Description

The invention relates to a pulse and computer technology and can be used, for example, in the construction of statistical analyzers, digital measuring devices, etc.

The aim of the invention is to enhance the functionality of the devices by determining the value of the ratio of the number of pulses in two pulse streams.

FIG. 1 and 2 shows a functional diagram of the proposed device; in fig. 3 is a diagram explaining the principle of operation of the device; FIG. 4 is a diagram of an accumulator of a subtractor-subtractor.

. The device contains the first summing counter 1, the first logical

.block 2, subtracting counter 3, block of elements AND 4, accumulating adder – subtractor 5, second logical block 6 and second summing counter 7. In addition, the device has the first input 8 (input of the denominator) and the second input 9 (input of the numerator). The first summing counter 1, the first logic block 2 and the subtracting counter 3 are connected in series.

FIG. 1 and 2 indicate the weights of the bits of the accumulating counters 1 and 7, the counter 3 and the adder-subtractor 5; As you know, the younger (zero) discharge has weight 2, the next one is weight 2, etc. up to bit 2 at counter 1 and up to bit 2 at counter 7. Thus, counter 1 has (N + 1) bits, and counter 7 has (M + 1) times

sd

with

OS

Row For subtractive counter 3, which, as will be seen from further, is intended for fixing numbers not exceeding one unit (binary fractions), the most significant bit has a weight of 2 (units), the next, younger phasor D has a weight of 2 and t .d down to weight. Accumulating

adder-subtractor 5 has bits with weights of both large units (2, 2, ...) and equal to or less than one (2 °, 2 ...).

The first logical block 2 is made on the elements And 10-1 - 10-N, P-1 - H-N and the keys (elements And) 12-1 - 12-N. Elements 10-N- - 10-1 are connected in series. The second input of each of these elements AND is connected to the inverse output of that bit of summing counter 1, whose number is shifted by 1 relative to the index of the element And 10 so that the element AND 10-n is associated with the n-1-th digit of the counter ( i.e. having weight 2, p 0.1N-1). The output element And 10-1 through the key (element And)

12-1 is connected to a nup input of a left-hand bit with a weight Z,

subtractive counter 3. The output of each of the remaining elements And 10-n (n 1, ..., N-1) through the elements And 11 - n And the keys 12-n are connected to the counting input of that bit of the subtracting counter 3, which. has weight. For example, element 10-2 through element 11-1 n and key 12-2 are connected to the discharge. The inverse output of the last (N-ro) discharge of counter 1 (having a weight of 2) is connected to the input of the element AND 10-N and through the element And 11-N and the key 12-N to the input of the least significant bit of the counter 3 having a weight 2 (2M-0.

The output of each of the bits of the subtracting counter 3 through the element AND of the block 4 is connected to the summation input of that bit of the adder-5, which has the same second input of each of the AND elements (Zloka 4 connected to the second input 9 of the device).

The second logical block 6 has the elements And Fri-P. Each of these elements is connected to the output of that of the bits of the second summing counter 7, whose number coincides with the first index. The second input of each of these elements is associated with

0

five

0

598

the course of that of the keys l-2-n of block 2, whose index coincides with the second index in the designation of the element And 13. Therefore, the element And 13, is connected to the output of the m-th digit of counter 7 and to the output of the element And 12n (t 0,1, ..., M; n 1, ..., M). The output of the element AND, p (via the elements OR 14 or directly) is connected to the subtractive input of the adder-subtractor 5. At the same time, the output of the element AND 1 3 (m 0,1, ..., M) is connected to the bit that has the number , is equal to m (i.e., weight 2), and the output of each of the remaining elements I 1 3 y, (n 1, ..., N; m 0,1, ..., M) - to bits that have weight . If you need to connect several AND 13 elements to the same input of the adder-subtractor 5, this is done through the elements of OR 14.

Sz mmator-subtractor 5 (Fig. 4) has the first group of inputs 15, the second group of inputs 16, the accumulator-subtractor 1 7 itself, with a group of inputs 18 and control inputs 19 and 20, elements OR 21 - 23. Inputs 15 are connected to OR 22. Inputs 16 are connected in the same way to OR 23. The output of OR 22 is connected to control input 19, and the output of OR 23 is connected to control input 20. Inputs of the same name of both groups 15 and 16 are through the corresponding element OR 21 are connected to the input of the same bit of the totalizer-subtractor 17.

Before describing the operation of the device according to FIG. 1 and 2, we will focus on its principle of operation, which is illustrated in FIG. 3

In technical solutions, linear interpolation of the form fg (k) 1 / k, nodes (, 1, ...) is used. FIG. 3 shows the graphs of this dependence for various 1.

The device pulses come

five

0

five

0

five

0

on two inputs, and it forms the values of the function fJ (k) 1 / k, where k is the number of pulses received by the software on one input (Denominator) and 1 is the number of pulses received on 5 other inputs (Numerator).

As an example, let us consider a situation in which a pulse arrived at the input of the denominator, and

51

input numerator - pulse. The device must then generate the value of the function f (4) 3/4, and its state is indicated by a dot on the curve corresponding to the argument. If now the next pulse arrives at the input of the numerator (the value of 1. increases from 1 3 to 1 4), then the image point must move to a higher curve with the same value of the argument. This new state is indicated by the point b.

If in the case when the device was in the state (l (4) 3/4), a pulse arrived at the input of the denominator, i.e. The argument k changed its value from to the image point of the drill to move along the same curve one step to the right (to point c).

The device works as follows.

First we will stop on the functioning of elements 1,2,3.

As noted above, these elements collectively form a device, the operation of which is as follows.

Suppose that in the initial state all the trigger triggers. 1 and 3 are set to zero. This is done by, for example, applying pulses to the R inputs of the flip-flops.

Since all the triggers of the counter 1 are in the zero state, there are single signals at their inverse outputs. These signals arrive at the inputs of the AND 10-N-1 elements - 10-1, therefore, a single signal also takes place at the output of each of these elements. These single signals are sent to the elements And 11-N-1 11-1. However, since all the triggers of the counter 1 are in the zero state, a second signal from the direct output of that trigger, which has a weight of 21, is sent to the second input of each of the I 11n Elements (n 1, ..., N). Therefore, all elements AND lln at the output have a zero signal and all keys (elements I) 12n (n ,, .., N) turn out to be locked. The exception is the key I2-1, which is opened with a single signal from the output of element I1 0-1.

The first pulse arriving at; input 8 through open the key 12-1,

598f enters the zero-bit trigger input (2) of counter 3 and translates this trigger into one state. In counter 3, the number 00 ... (one) is written. Following this, the same impulse writes 1 unit into the counter (the number 1000 .. o). In this case, the zero-discharge trigger of this counter (of weight 2) goes into one state, at its inverse output a zero signal appears that hits the key 12-1. The single signal, which appeared at the direct output of the same trigger, will go to the second input of the element 11-2, and a single signal will also appear at its output, which will go to the key 12-2 and open it.

0

The next (second) pulse from input 8 through the open cell} Pts 1 2-2 goes to the trigger trigger input -1 (weight 2) of the counter. Since counter 3 is subtracting, the impulse to the input of this trigger corresponds to subtract 1/2 value, previously recorded in the counter. As a result, in the counter 3 the number 0,100., (, 1/2 appears. The same impulse from the input 8 through the delay D is recorded in the counter 1 deuce (the number 0100 ...). Since the trigger 2 of the counter 1 went to Zero state, and the trigger 2 is in the single state, then a single signal is removed from the AND 10-2 element, and a single signal is sent to the AND 11-2 element and thus opens the key 12-2, the zero signal from the output of the AND 10 element 2 will maintain zero signals at the outputs of the And 10-1, 11-2 elements and, therefore, the key 12-1 will remain closed and the key 12-2 will close.

)

By a similar consideration, we find that the description of the operation of the circuit elements 1,2,3 can be represented in Table. 1 and 2 (for elements 10 and 11, the values from the ignals, single or zero, are given at the outputs of these elements after the arrival of the next pulse at input 8),

As can be seen from the table, subtractive counter 4 implements a sequential transition through the points of the broken line, which interpolates the curve f / n (k) 1 / k piecewise linearly.

We now turn to the description of the functioning of the proposed device as a whole.

Suppose initially that the input of the 9 numerator, not received a single pulse. Then the pulses arriving at input 8 of the denominator will, as described above, record a binary fraction in counter 3, giving an approximate (by piecewise linear interpolation) value of 1 / k. As the number of pulses at input 8 increases, the pulses will appear at the output of the element And 12-1, then And 12, etc. These pulses arrive at elements AND of the second logical block 6, and from element 12-1 to elements 13 and (55+.

from item

And Г2-2 - for elements И 13о, + 13ji and, in general, from the element И 2-п - for elements И, + 13дд у (п 0, .. ,, N). However, since at this moment the pulses at input 9 did not arrive, the counter 7 recorded a zero number (zeros are written in all bits). Therefore, at the outputs of the elements And of block 6, zero signals will occur, therefore, no numbers will be written to the accumulating adder-calculator 5 from the side of block 6. Therefore, the adder-subtractor 1: 5 retains its original (zero) state, which corresponds to the number fg (k) o / k 0.

The opposite situation (k 0,) is obviously forbidden due to the impossibility of dividing by zero and therefore is not considered.

Now suppose that one impulse () has arrived at the input of the 8 denominator; If by this time no impulses have arrived at the input 9, then, as described above, in the subtractor 5 there will be written down a zero number. In this case, in the subtractive counter 3, the unit was recorded (the number .1.00.,.) Now let the pulses begin to arrive at the input 9 of the numerator. Their total number will be counted by summing counter 7. In addition, each of these pulses, coming from input 9 to the block of the AND 4 element, will each time be fed to the inputs of the adder-calculator

unit recorded in counter 3, Therefore, the number of times a unit is added to the contents of subtractor 5 as many times as the number of times a pulse is entered at input 9. Consequently, in the adder of the subtractor 6, the square meter m is with the recorded number fg (1) 1/1 1, where 1 is the number of pulses received at the input 9 of the numerator.

Suppose now that, for example, a pulse arrived at the input 9 of the numerator, and a pulse at the input 8 of the denominator. Then, as described above, in the summing counter 1 a binary representation of the number will be written, k 0 ... 0100 (the first digit to the right), in the counter 3, the number is 0.110, .., (the least significant bits to the right), the inverse number, recorded in the counter 1, and in the counter 7 - the number 00..011 (younger bits to the right), If the device still operated

correctly, then in the adder-subtraction. Title 5 is written the number fj () - 3/4 0,1100, .., i.e. zeros are written in bits with a weight of 2.2 or more, in

45

discharge dach with a weight of 2, 2 units

and in the younger grades 2, 2, etc. - also zeros.

Suppose now that one more, fourth impulse entered input 9. This impulse will increase by. unit the contents of counter 7, writing in it the number 00 ... 100. The same pulse through the block of elements I4 will add to the contents of the adder-subtractor 5 the contents of counter 3, i.e. to number

0,1100 .., the number will be added

0,010 ... Thus, the operation (4) +1/4 3/4 + + 1/4 110 ,,, will be executed. Since before this number was fixed in it

s () 0.1100 ,,. ,, then after performing the operation. subtracting in it will fix the number f3 (5) 0.110000 ... - 0.0001100 0.101010, which with an accuracy due to the piecewise linear 50

 interpolates, approximates the number 3/5.

FIG. 3, the described process is indicated by the transition from the point dj to the point

Thus, we considered

Both cases of device operation on the f (4) –f (4) transition examples and

fjC)

3 (5).

916

In order to prove the achievement of a goal in any initial state, let us consider the same two situations (receipt of pulses at input 9 and at input 8) in the general case.

Suppose that at this time, the device received 1 pulses of the numerator (1,.,.) At input 9, and denominator pulses (k 1,2, ...) at counters 7 and 1 recorded a binary image of numbers k and 1, respectively, and counter 3, a binary image of the approximate value of 1 / k, and in subtractor 5, the approximate value of fg (k) 1 / k.

Suppose now that the next pulse of the numerator arrived at the input 9. As follows from the principle of operation of the device, it increases the content of the counter 7 by one unit and adds the content of the counter 3 to the content of the accumulator totalizer 5, i.e. fj (k)

 fg (k) f 1 / k i (l + l) / k.

Ha FIG. 3, this is indicated by a transition (vertically) from line 1 to the next higher line 1 + 1.

Consider the case of pulses at input 8. If initially a certain number fg (k) was recorded in adder-subtractor 5, this means that the number 1 is recorded in summing counter 7. The arrival of the next denominator-impulse leads to the numbers ffl (k) recorded in subtractor 5 will subtract the number 1 recorded in counter 7 with a weight determined by the bounds in which the number k recorded in counter 1 is found. If 2 k with, then can be seen from FIG. 1 and 2, this number will be subtracted with weight i. transition on the line corresponding to the number 1 to the adjacent right

the point.

Thus, with the accuracy stipulated by the linear interpolation, the operation of calculating the current value of the ratio 1 / k will be implemented.

The adder operates as follows.

When a number arrives at a group of inputs 15, the signals from the bits through the elements OR 21 arrive at the naps

59810

the adder-subtractor 17. At the same time, these signals fall on; - elements OR 22. Since at least one of the bit signals at the inputs 5 15 is not zero, the output of the element 22 is a single signal, which is fed to the input 19. Signaling input 19 causes the number applied to adder 17 to be added to the content; 17. Analogically, the number appearing at the input 16 also goes to the adder-subtractor 17 and simultaneously through the OR element 23 fixes a single signal at the control input 20, which leads to the subtraction of the number from the inputs 16 from the content of the adder-viate0 l 17.

Claims (1)

Invention Formula A counting device containing the first totalizer, the first logic block and the subtracting counter, 5 which are connected in series, characterized in that, in order to extend the functionality by determining the value of the ratio of the number of pulses to 30 two pulse streams, the second sum- is additionally introduced into it. A counter that accumulates the adder-subtractor, the block of elements And the second logic block; with the second group of inputs of the second logic block, the outputs of the second logic block are connected to the subtraction outputs of the accumulating adder-subtractor, the second input of the device is connected to the input of v the second logical block contains (M + 1) (N + 1) elements And, where M + 1 is the number of bits of the second summing counter, N + 1 is the number of bits of the first summing counter, and the elements OR, with the first and second inputs (t, n) of the element And, where m 55 0,1, ..., M, n 0,1, ..., N, are connected respectively with the m input of the first group and the nth input of the second group of inputs of the second logical 35 45 50 161059812 block output (M, 0) -th element AND logical unit, and outputs (t, tO-x, which directly, and where m 0.1M, n i, ..., N, ele (t, 0) -x elements And, where m O, ..., cops And through the corresponding element M-1, through the corresponding element OR are connected to t- (2n-1)} - m OR connected to the th output of the second output of the second logic unit. Table 1 No. of input pulse 8 Counter triggers ABOUT . 1 o 1 o about about 1 1 about oh oh oh one k A Elements and 10-1 10-2 G10-3 | ll-2 G11-: eleven Ltd 1 1 1 1 about about 1 oh oh one oh i one table 2 Ush.zh t t t t t t t t t .g PI g ABOUT /five ". 22 vL 2 / 27 /eight G8 7S 20 Fg / g / b about 2J 27 /at