JP2010020815A - Fifo access circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately read effective data in FIFO without depending on a data processing unit when only fragmentary quantity in which effective data storage quantity is less than an output bus width is present in the FIFO by a data processing unit, in the FIFO of input bus width narrower than output bus width. <P>SOLUTION: Data can be read by providing a dummy data write means for the FIFO and by filling data of the portion not filling the output bus width with dummy data. Also it can be recognized that what bit the actually effective data is out of output data from the number of times of writing of dummy data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a FIFO access circuit that controls access according to the amount of valid data stored in a FIFO.

  The FIFO is used as a buffer in various data processing circuits.

  FIG. 1 is a circuit block diagram including a general FIFO, and the operation of the FIFO circuit will be briefly described.

  A FIFO is used when data is transmitted between the 102 write control circuit and the 103 read control circuit. 101 is an MPU for controlling the entire data transmission, 104 is a FIFO access control circuit for controlling writing and reading operations to the memory array 105 in the FIFO, 151 is input data, and 152 is output data.

  FIG. 2 shows an operation flow of the write control circuit 102.

  When the write control circuit 102 receives a write request by asserting the write request signal 111 from the MPU 101 (S201), it starts control for writing the input data 151 to the FIFO. The write control circuit 102 that has received the write request checks whether or not there is an empty FIFO by the full signal 115 from the FIFO access control circuit 104 (S202). If there is no available space in the FIFO, the confirmation of the full signal 115 is repeated, and it is waited for the FIFO to be freed by the read operation (S203). If there is an empty FIFO, the input data 151 is output as the FIFO write data 113, and the FIFO write trigger 114 is output at the same time (S204). At the same time, the write completion trigger 122 is output to the MPU 101 (S205). The MPU 101 receives the write completion trigger 122 and negates the write request signal 111 to complete the write process (S206).

  FIG. 3 shows an operation flow of the read control circuit 103.

  When the read control circuit 103 receives a read request from the MPU 101 by asserting the read request signal 112 (S301), the read control circuit 103 starts control for extracting data from the FIFO and outputting it as output data 152. In response to the read request, the read control circuit 103 checks whether valid data is stored in the FIFO by the empty signal 118 from the FIFO access control circuit 104 (S302). If valid data is not stored in the FIFO, the empty signal 118 is repeatedly checked to wait for valid data to be stored by a write operation (S303). If valid data is stored in the FIFO, the FIFO read trigger 117 is output (S304). In response to the FIFO read trigger, the FIFO access control circuit 104 outputs valid data as FIFO read data 116, and the read control circuit 103 latches this data as output data 152 (S305). At the same time, a read completion trigger 123 is output to the MPU 101 (S306). The MPU 101 receives the read completion trigger 123 and negates the read request signal 112 to complete the read process (S307).

  The FIFO access control circuit 104 manages memory addresses to be written / read, and outputs the result of decoding the address data as a write memory selection signal 120 and a read memory selection signal 121. Further, the effective data amount in the FIFO is detected by comparing the write address and the read address, and the full signal 115 is asserted when there is no empty memory in the FIFO, and the empty signal 118 is asserted when there is no valid data.

  However, in the above configuration, there is a problem that the effective data storage amount in the FIFO cannot be confirmed from the MPU 101, and efficient data transmission cannot be performed. Thus, a method for detecting the effective data storage amount in the FIFO has been proposed.

  For example, Patent Document 1 proposes detecting the effective data amount by outputting the difference between the write address and the read address to the MPU.

  Patent Document 2 proposes to increase access efficiency by adding a circuit that performs access arbitration based on the difference between a write address and a read address.

  Patent Document 3 proposes adding a register indicating whether or not valid data is stored in each memory in the memory array.

Patent Document 4 proposes to add write time data to the memory in the memory array.
JP 5-189955 A Japanese Patent Laid-Open No. 2003-263883 JP-A-5-51931 JP-A-2-183487

  It is possible to detect the effective data storage amount in the FIFO by the method proposed in Patent Document 1. However, this is effective when the bus widths of the input data and the output data are the same, but this control cannot be performed as it is in the FIFOs having different input / output bus widths.

  If the input / output bus width is smaller than the output bus width in FIFOs with different input / output bus widths, data cannot be read out if there is only a fractional amount of valid data storage that is less than the output bus width. .

  For example, when the input data bus width is 8 bits and the output data bus width is 64 bits, it is necessary to write the input data eight times for one read of the output data. Depending on the data processing unit, the number of times of writing input data is not always performed in units of 8. In such a case, the final data in the first data processing and the start in the second data processing in the 64 bits of output data Data will be mixed.

  Therefore, the FIFO control method of the present invention adds a circuit that writes dummy data directly from the MPU until the full signal is asserted, thereby accurately detecting the storage amount of valid data, and at the same time, FIFO that matches the data processing unit. An access control method is proposed.

  When the amount of valid data stored can be determined from the number of dummy data writes, and when the input bus width is smaller than the output bus width, and the effective data storage amount is less than the output bus width, Can also read data.

  Next, details of the present invention will be described in accordance with the description of the embodiments.

  Hereinafter, an embodiment of a FIFO control method according to the present invention will be described in detail with reference to the drawings.

  FIG. 4 shows an example of a circuit block diagram including the FIFO of the present invention.

  4 differs from FIG. 1 in that it has an input data selection circuit 106 for selecting arbitrary MPU write data 172 and input data 151 from the MPU and outputting them as write data 173, and input data selection. The MPU 101 outputs a data selection signal 171 that determines which data is to be selected in the circuit 105, and the full signal 115 is monitored by the MPU.

  FIG. 5 shows the operation flow when writing to the FIFO of the MPU101.

  First, normal data writing will be described. In writing (S501), the MPU 101 clears the counter provided therein and outputs MPU write data 172 (S502). Thereafter, the write request signal 111 is asserted (S503), and the write operation is started. After the start, it waits for the write completion trigger 122 to be output from the write control circuit 102 (S504). When the write completion trigger 122 is received, the current write mode is confirmed (S505). In the normal write mode, the post-write request signal 111 is negated (S506) to complete the write operation.

  Next, dummy data writing will be described. Up to S505, the flow is the same as that for normal data writing. However, when dummy data is written, the counter value provided therein is incremented by 1 (S507). Thereafter, the write request signal 111 is negated (S508) and the write process is once completed. Here, the value of the full signal 115 is confirmed to determine whether or not there is an empty FIFO (S509). If there is an empty FIFO, the operations from S503 to S508 are repeated. When the FIFO is full, the full signal 115 is asserted and the write operation is completed.

  A dummy data write operation in the case of performing data transfer of 112 bits when the input bus width is 8 bits and the output data bus width is 64 bits in the above configuration will be described.

  First, when data transfer is started, data is written in the normal data write mode. For 64 bits out of 112 bits, the output data bus width has reached 64 bits, so it can be read normally. When the writing to the FIFO for the remaining 48 bits is completed, the MPU 101 detects that all the data to be transferred has been written to the FIFO, and switches to the dummy data writing mode to start data writing. When the dummy data is written twice, the FIFO stored data amount is 64 bits, and the full signal 115 is asserted, so the dummy data writing is completed and the FIFO stored data 64 bits are read. Here, since the built-in counter value is 2, the MPU 101 performs subsequent processing assuming that 16 bits of the read data are dummy data.

  The amount of data transfer that cannot be divided by the output data bus width as described above is, for example, data generation in which the number of dots in an image is calculated in an image size unit different from the image size unit for performing image processing when performing image processing Occurs when doing. In either case, when writing to an external RAM via the system bus, the system bus width is determined by the image size unit for image processing, and the FIFO output bus width needs to be adjusted accordingly. However, since the calculation data of the number of dots is calculated in a different image size unit, the FIFO input bus width is different from the output bus width. In addition, since the amount of data is determined by the image to be processed, an amount of data transfer that cannot be divided by the output data bus width occurs.

Circuit block diagram including general FIFO. The operation flow of the write control circuit 102. The operation flow of the read control circuit 103. An example of the circuit block diagram containing the FIFO of this invention. The operation | movement flow at the time of FIFO writing of MPU101 of this invention.

Explanation of symbols

101 MPU
102 write control circuit 103 read control circuit 104 FIFO access control circuit 105 memory array 106 input data selection circuit 111 write request signal 112 read request signal 113 FIFO write data 114 FIFO write trigger 115 full signal 116 FIFO read data 117 FIFO read trigger 118 empty Signal 120 Write memory selection signal 121 Read memory selection signal 122 Write completion trigger 123 Read completion trigger 151 Input data 152 Output data 171 Data selection signal 172 MPU write data 173 Write data

Claims (4)

Data switching means for switching and outputting arbitrary write data to FIFO and input data from outside,
An FIFO access circuit comprising: arbitrary data writing means for writing the arbitrary write data an arbitrary number of times.   2. The FIFO access circuit according to claim 1, wherein the arbitrary number of write data is written until the FIFO becomes empty.   3. The FIFO access circuit according to claim 2, wherein the amount of externally input data stored in the FIFO is detected from the arbitrary write data write count.   4. The FIFO access circuit according to claim 1, wherein a data bus width of the input and output of the FIFO is different.

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