JP2015014934A - Memory controller and memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller capable of executing sequence control at high speed.SOLUTION: A bit operation table storage unit 10 holds the result of bitwise logical operation as a table in advance. A lookup table unit 19 holds one table of the bit operation table storage unit 10. A data latch unit 17 latches bit data extracted by a bit extraction/insertion unit 16, and a bit selector unit 18 selects one bit from the table held in the lookup table unit 19 in accordance with output of the bit data latched by the data latch unit 17. A read/write control unit 20 exerts control for writing back, to a device memory 6, word data in which one bit among word data read out from the device memory 6 after a write to the device memory 6 is replaced with the one bit outputted by the bit selector unit 18.

Description

  The present invention relates to a memory control device and a memory control method for controlling a value of a device memory in a programmable controller that performs a bit operation of sequence processing.

  An apparatus for performing logical operation processing in a conventional programmable controller includes a register, an instruction decoder execution unit, an instruction processing execution unit, and a memory read / write execution unit, and executes sequence processing (see, for example, Patent Document 1).

JP-A-2-75003

  When executing a sequence control according to a ladder diagram with a programmable controller using a CPU, a 1-bit operation and 1-bit data are processed when processing a circuit block consisting of a logical operation of a contact and a coil output during the sequence control. Extraction and insertion from word data is required. When acquiring 1-bit contact data from the device memory, an operation of extracting a specific 1 bit is required, and a bit operation is required in a logical operation between the contacts. In addition, in order to output the calculated 1-bit result as a coil, writing to the device memory is performed. At this time, a read-modify-write process of inserting 1 bit into the word data is required.

  When thinking about performing sequence control at high speed using a CPU that does not have an instruction for performing such bit processing, an instruction circuit for bit operation processing is added to the CPU, or the existing CPU It is necessary to execute bit processing by combining a plurality of instructions. In the case of means for adding a new instruction circuit for bit arithmetic processing to an existing CPU, there has been a problem that a large-scale correction of the circuit is required. In addition, when bit processing is executed by combining multiple existing instructions, an extra instruction cycle is required for bit operation processing, resulting in longer processing time and faster sequence control. There was a problem that it was difficult to carry out.

  The present invention has been made to solve the above problems, and an object thereof is to obtain a memory control device and a memory control method capable of executing sequence control at high speed.

  A memory control device according to the present invention includes a bit operation table that holds a result of a logical operation in units of bits as a table in a memory control device that controls a value of a device memory in a programmable controller that processes a ladder including logical operations of contacts. A storage unit, a lookup table unit that acquires and holds one table from the bit operation table storage unit, and a bit extraction insertion unit that extracts bit data from word data read from the device memory based on a bit selection input A data latch unit that latches the bit data extracted by the bit extraction and insertion unit, and a bit selector that selects one bit from the table held in the lookup table unit according to the output of the bit data latched by the data latch unit And writing to device memory A read / write control unit that reads out word data from the device memory and rewrites the word data in which one bit is replaced with one bit output from the bit selector unit to the device memory. It is a thing.

  The memory control device according to the present invention holds the result of bitwise logical operation as a table in advance, reads the contact data bit by bit, selects the correct operation result from the table using this data as an address, and obtains the obtained 1-bit Since the operation result is written to the device memory, bit operation processing can be performed on the logical operation block at the contact point of sequence control without executing multiple instructions for execution of bit operation. A controller can be realized.

It is a block diagram of the memory control apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the a contact of a ladder diagram, b contact, and a coil. It is explanatory drawing which shows an example of the ladder diagram of sequence control. It is explanatory drawing which shows the example of the block which has three coils. It is explanatory drawing which shows the example of a block with seven contacts. It is explanatory drawing which shows the block at the time of dividing | segmenting the block shown in FIG. It is a block diagram of the memory control apparatus by Embodiment 4 of this invention. It is a block diagram which shows the calculating part of the memory control apparatus by Embodiment 5 of this invention. It is a block diagram of the memory control apparatus by Embodiment 5 of this invention. It is a block diagram of the memory control apparatus by Embodiment 6 of this invention. It is explanatory drawing which shows the example of the command sequence recorded on the command storage part of the memory control apparatus by Embodiment 6 of this invention.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a memory control device according to Embodiment 1 of the present invention.
1 includes a CPU (microprocessor) 1, a CPU address line 2, a CPU data line 3, a write enable line 4, a read enable line 5, a device memory 6, a device memory data line 7, and a device memory read enable. Line 8, device memory write enable line 9, bit operation table storage unit 10, memory address line 11, memory data line 12, memory read enable line 13, bit selection line 14, operation result bit line 15, bit extraction insertion unit 16, A data latch unit 17, a bit selector unit 18, a lookup table unit 19, a read / write control unit 20, and a table address generation unit 21 are provided.

  The CPU 1 is a processor that performs logic processing of a ladder diagram and performs arithmetic processing using other application instructions, arithmetic operation instructions, and the like. The CPU 1 is connected to the device memory 6 through a CPU address line 2 and is connected to the read / write control unit 20. On the other hand, a write enable line 4 and a read enable line 5 are connected. Of the signal lines of the CPU address line 2, the device memory 6 is connected with the number of signals corresponding to the capacity of the device memory 6. Some of the signal lines of the CPU address line 2 are taken out as bit selection lines 14 and connected to the bit extraction / insertion unit 16. When the word size of the device memory 6 is 16 bits, four bit selection lines 14 are necessary, and when the word size is 32 bits, the number is five. The device memory data line 7 of the device memory 6 is connected to the bit extraction / insertion unit 16. The read enable line 5 of the CPU 1 is connected to the read / write control unit 20 and the data latch unit 17.

  The CPU 1 and the table address generator 21 are connected by a CPU data line 3 and a write enable line 4. The device memory 6 is a memory that stores information indicated by 1 and 0 indicating whether the coil is on or off in the ladder diagram. The device memory 6 is connected to the bit extraction / insertion unit 16 by a device memory data line 7 and is also read / write. The controller 20 is connected to the device memory read enable line 8 and the device memory write enable line 9. The bit operation table storage unit 10 is a table storage unit that preliminarily holds a result of logical operation in units of bits in the ladder diagram as a table, and an address is given from the table address generation unit 21 via the memory address line 11, and The read enable / disable is designated from the memory read enable line 13. Further, the read table is configured to be sent to the lookup table unit 19 via the memory data line 12. The operation result bit line 15 is a signal line for sending the operation result from the bit selector unit 18 to the bit extraction / insertion unit 16.

  The bit extraction / insertion unit 16 extracts the bit data from the word data read from the device memory 6 based on the bit selection input of the bit selection line 14, and the word data obtained by replacing the bit data of the operation result bit line 15. This is a circuit for writing back to the device memory 6. The data latch unit 17 is a circuit that latches the bit data output from the bit extraction / insertion unit 16 based on the validity / invalidity of the read enable line 5. The bit selector unit 18 is a circuit that selects one bit of the calculation result from the table of the lookup table unit 19 based on the contact information latched by the data latch unit 17 and outputs it to the calculation result bit line 15. The lookup table unit 19 is a circuit that stores the table of the bit operation table storage unit 10. The read / write control unit 20 reads word data from the device memory 6 in response to writing to the device memory 6, and again replaces the word data in which 1 bit is replaced with 1 bit output from the bit selector unit 18. It is a control unit for performing control to write back to the device memory 6. The table address generation unit 21 provides an address for selecting a table in the bit operation table storage unit 10 based on the address from the CPU data line 3 to the bit operation table storage unit 10 via the memory address line 11, and This is a circuit for enabling the read enable line 13 and reading the table from the bit operation table storage unit 10.

  The present invention is an apparatus for executing the sequence control shown in the ladder diagram. A total of five a-contacts and b-contacts shown in FIG. 2 are connected in parallel or in series, and a combination of the configurations connected to one coil is defined as one block. FIG. 3 shows an example of a ladder diagram of sequence control including blocks composed of such logical operations. This apparatus can achieve the effect of speeding up when executing this block operation.

The bit calculation table storage unit 10 of the present apparatus stores a table showing the calculation result of the sequence control of FIG. 2 before starting the sequence control. For example, since there are five contacts in the block m shown in FIG. 3, there are 2 ⁵ (32) patterns of these logical operation results. If the contact value P _{m [0]} −P _{m [4]} that takes a logical value of 0 or 1 is determined, one of the 32 calculation results can be determined. The table is one in which 32 kinds of calculation results are arranged by 32 1 and 0 values. The bit operation table storage unit 10 holds a table for each block of sequence control.

Next, a procedure for processing the block m shown in FIG. 3 will be described as an example of the operation.
First, in order to read the table corresponding to the operation result of block m from the bit operation table storage unit 10, the CPU 1 enables the write enable line 4, and the CPU data line 3 accesses the memory of the bit operation table storage unit 10. Output address. The write enable line 4 and the CPU data line 3 are connected to a table address generation unit 21, and the table address generation unit 21 outputs a table address from the memory address line 11 to the bit operation table storage unit 10. By enabling the memory read enable line 13, it is possible to read the ladder block table for executing the calculation. The read ladder block table is held in the lookup table unit 19 via the memory data line 12. The process of reading the table from the bit operation table storage unit 10 and storing it in the lookup table unit 19 can be executed in one instruction cycle of the store instruction of the CPU 1.

In order to process the block, the CPU 1 enables the read enable line 5 and outputs an address for reading a word including a contact in the block from the CPU address line 2. The read / write control unit 20 enables the device memory read enable line 8 when the read enable line 5 is valid and the write enable line 4 is invalid. The bit selection line 14 outputs a signal indicating which position of the word contains one bit of the contact. When one word is 16 bits, any one bit can be selected by four signals on the bit selection line 14. The device memory 6 outputs word data including a contact for executing an operation to the bit extraction / insertion unit 16 through the device memory data line 7. The bit extraction / insertion unit 16 extracts only one bit of the contact for performing the operation based on the information of the bit selection line 14. Since the read enable line 5 is enabled, the data latch unit 17 latches the extracted 1-bit information. The CPU 1 executes the load instruction once until the bit data of one contact is read from the device memory 6 and latched in the data latch unit 17. In order to calculate the block m shown in FIG. 3, it is necessary to read 1-bit information of the five contacts of P _{m [0]} -P _{m [4]} , and the CPU 1 executes the load instruction 5 times. Two pieces of contact information can be held in the data latch unit 17.

  The data latch unit 17 and the lookup table unit 19 are connected to the bit selector unit 18, and the bit selector unit 18 calculates the calculation result from the table of the lookup table unit 19 based on the contact information latched by the data latch unit 17. One bit is selected and output to the operation result bit line 15.

The CPU 1 designates an address for designating a word including Q _m indicating on / off information of the coil in the device memory 6 by the CPU address line 2 and enables the write enable line 4. The read / write control unit 20 connected to the write enable line 4 enables the device memory read enable line 8 when the read enable line 5 is invalid and the write enable line 4 is valid, and is designated by the CPU address line 2. The read word is read from the device memory 6 and output to the device memory data line 7. Next, data in which the bit of Q _m designated by the bit selection line 14 in the word input from the device memory data line 7 to the bit extraction / insertion unit 16 is replaced with the signal of the operation result bit line 15 is generated. And Disable the device memory read enable line 8, to enable the device memory write enable lines 9, calculates the output information of the coil Q _m of device memory 6 by outputting the data in the device memory data lines 7 to the device memory 6 Write the value changed by. At this time, address information indicating the memory position of the table is output from the CPU data line 3 in order to read the table for calculating the next sequence control block from the bit operation table storage unit 10. This can be done in that together with a read-modify-write coil information Q _m to load the table of the next block in the look-up table unit 19 at the same time.

  By continuously executing the above processing, an effect is obtained that processing of a block including five contacts and one coil can be processed with five load instructions and one store instruction of the CPU 1 in sequence control.

  As described above, according to the memory control device of the first embodiment, in the memory control device that controls the value of the device memory in the programmable controller that processes the ladder including the logical operation of the contacts, the logical operation of the bit unit is performed. Based on a bit operation table storage unit that stores results in advance as a table, a lookup table unit that acquires and stores one table from the bit operation table storage unit, and a bit selection input from word data read from the device memory The bit extraction / insertion unit for extracting bit data, the data latch unit for latching the bit data extracted by the bit extraction / insertion unit, and the output of the bit data latched by the data latch unit are held in the lookup table unit. Bit select to select one bit from the table And word data read from the device memory in response to writing to the device memory, and the word data in which 1 bit is replaced with 1 bit output from the bit selector unit is written back to the device memory again. The read / write control unit is provided, so for the block consisting of the logical operation of the contacts constituting the sequence control, the table is taken into the lookup table unit, and the bit data is read from the device memory by the number of contacts, and the coil It can be processed simply by writing a word containing a to device memory. Since a table is already obtained as a result of calculation, the result is selected only by the input data of the contact point. Therefore, a separate circuit for logical operation is unnecessary and can be realized with a simple circuit.

  Further, according to the memory control device of the first embodiment, the ladder composed of the logical operation of the contact is processed by the instruction executed by the CPU, and the bit selection input is given from the CPU. Even when a CPU is not used, large-scale correction of the circuit is not necessary, and sequential control can be performed at high speed.

Embodiment 2. FIG.
In the first embodiment, the coil is executed with respect to one block, but there may be a plurality of coils. When executing the block shown in FIG. 4, it is necessary to output to the three coils, but after the operation result is output to the operation result bit line 15 by the data latch of the contact in the first embodiment, the target is three times. The word in the device memory including the coil may be written. That is, for a block having a plurality of coils, the output from the bit extraction / insertion unit 16 is continuously written in the device memory 6 by the number of coils to be output.

  In the second embodiment, an address indicating the table of the block currently being executed is output from the CPU data line 3 in the first two writes so that the lookup table in the lookup table unit 19 does not change. It is preferable to output an address indicating a table of the next block from the CPU data line 3 in the third writing of the coil.

  As described above, according to the memory control method of the second embodiment, for the block having a plurality of coils, the output from the bit extraction / insertion unit is used for the block having a plurality of coils. Since the number of coils to be output is continuously written in the device memory, the processing of the first embodiment can be realized even for a block having a plurality of coil outputs in the sequence control block.

Embodiment 3 FIG.
A table held in the bit operation table storage unit 10 may be shared for a plurality of blocks having the same logic operation circuit but different contact points. For example, the blocks k and t in the sequence control shown in FIG. 3 can share one table because they have the same logical operation although the contacts are different. When loading a table, the table may be read from the bit operation table storage unit 10 and the contact latched in the data latch unit 17 at the time of execution of the operation may be changed. That is, for the processing of the block having the same contact point and coil but the same logic circuit configuration, the same table is loaded into the look-up table unit 19, and the data latch unit 17 latches different contacts. Write to the corresponding coil respectively.
Thus, by sharing a table for blocks using different contacts in the same logical operation circuit, there is an effect of reducing the memory capacity of the bit operation table storage unit 10.

  As described above, according to the memory control method of the third embodiment, the same table is loaded into the look-up table unit for processing of blocks having different contacts and coils but the same logic circuit configuration. Used, latching different contacts in the data latch part and writing to the coil of the corresponding block respectively, so the number of tables can be reduced and the memory capacity of the bit operation table storage part can be saved it can.

Embodiment 4 FIG.
There is no need to limit the number of contacts in one block of the sequence control for performing the calculation, and an arbitrary number X may be used. The number of registers that can hold 1 bit in the data latch unit 17 is X. If the number of contacts included in one block of the sequence control is less Y number than X number, the result of the operation of the table consists of 2 ^Y bits, the 2 ^Y bits of data as 2 ^X-Y number side by side 2 ^x bits It is placed in the bit operation table storage unit 10. As the calculation result, if the bit information of the contact is loaded Y times, the bit selector unit 18 can select from 2 ^× bits loaded from the bit calculation table storage unit 10 to the lookup table unit 19. When processing a block with more than X contacts included in one block of sequence control, an intermediate data holding variable is created and divided into blocks each including X contacts. As a result, there is no need to configure the variable-size data latch unit 17 according to the number of contacts included in the block, and the effect of preventing the table size stored in the bit operation table storage unit 10 from becoming too large can be obtained.

For example, FIG. 6 shows a state in which an intermediate variable is divided into two blocks with respect to FIG. 5 showing a block including seven contacts having a number of contacts larger than five. The ladder block shown in FIG. 5 includes seven contact points, but if M _m is used as an intermediate variable, it can be divided into two blocks, block a and block b, as shown in FIG. Since each contact is 5 or less, the calculation can be performed by the memory control device shown in the first embodiment. At that time, the procedure of writing the value of M _{m in} the device memory 6 when the processing of the block “a” is completed and reading it again when processing the block “b” is necessary in the first embodiment. It will take a cycle.

Therefore, in the fourth embodiment, as shown in FIG. 7, the operation result bit line 15, the CPU address line 2, and the write enable line 4 are connected to the data latch unit 17. Then, for the address defined by the CPU address line 2, the data latch unit 17 holds the value output to the operation result bit line 15 when the write enable line 4 is valid. In this way, after the value of M _m is determined, the CPU 1 outputs an address indicating the table of the next block to the CPU data line 3 and loads the table into the lookup table unit 19 by enabling the write enable line 4. In addition, M _m can be taken into the data latch unit 17. Thus reading the M _m from the device memory 6, the effect of reducing the instruction cycle becomes unnecessary load instruction cycle from two to one is obtained. 7 is the same as that of the first embodiment shown in FIG.

  As described above, according to the memory control method of the fourth embodiment, the memory control device of the first embodiment is used, and the number of contacts included in the ladder block is larger than a predetermined set value. On the other hand, since the processing is performed by dividing the block using the intermediate variable, the table size can be made constant, and the table size increases exponentially according to the number of contacts included in the block. Can be prevented.

  Further, according to the memory control method of the fourth embodiment, the intermediate variable output from the bit selector unit at the timing when the output from the bit selector unit is input to the data latch unit and the next table is loaded into the lookup table unit. Is latched in the data latch unit, so that it is not necessary to write the intermediate variable when the block is divided and processed into the device memory, and read and latch it again.

Also, according to the memory control method of the fourth embodiment, when the number of contacts included in the ladder block is N and the value of 2 ^N is smaller than the number of bits M of the table, the 2 ^N- bit tables are arranged side by side. Since the data expanded to several M is loaded as a table into the lookup table section and the calculation result is obtained by latching the values of the included contacts, even if the number of contacts included in the block is small, the same circuit is used for processing. It can be performed.

Embodiment 5 FIG.
As shown in FIG. 8, a plurality of arithmetic units 22 combining the bit selector unit 18 and the lookup table unit 19 may be provided. In that case, an operation result selector unit 24 and a table selector unit 23 are provided as shown in FIG. All the values of the contacts latched by the data latch unit 17 are inputted to the respective arithmetic units 22. Based on the signal of the CPU data line 3 output from the CPU 1, the table selector unit 23 determines which calculation unit 22 is loaded with the table obtained from the bit calculation table storage unit 10. Further, the calculation result selector unit 24 decodes the signal of the CPU data line 3 output from the CPU 1 and selects a necessary calculation result from the results of the calculation unit 22 having a plurality of signals. Since other configurations are the same as those of the first embodiment shown in FIG. 1, the same reference numerals are given to corresponding portions, and descriptions thereof are omitted.

  As described above, in the fifth embodiment, the same number of operation units 22 as the sequence control logic operation blocks are provided, so that the table is loaded from the bit operation table storage unit 10 only once. become. Further, even if it is impossible to have the same number of operation units 22 as the logical operation blocks included in the sequence control due to the scale of the circuit, etc., by having as many operation units 22 as possible, You will be able to load the table.

  In the first embodiment, each time a block is processed, the table is loaded once. However, when the table can be loaded continuously, the memory of the bit operation table storage unit 10 is a flash memory, a DRAM, Alternatively, when using a recording apparatus connected by a network, it is possible to access at a higher speed by continuously reading than by one reading, so that an effect of improving the processing performance of this apparatus can be obtained.

  As described above, according to the memory control device of the fifth embodiment, the operation result selector unit includes a plurality of operation units each including a bit selector unit and a lookup table unit, and selects outputs from the plurality of operation units. And a table selector unit for selecting a calculation unit to load a table from among a plurality of calculation units, so that it is possible to continuously load a table from the bit calculation table storage unit, thereby enabling continuous access. Fast flash memory and DRAM can achieve the speed-up effect. In addition, when all the logical operation blocks included in the sequence can be loaded into the operation unit, the processing can be performed by loading the table only once.

  Further, according to the memory control method of the fifth embodiment, the memory control device of the fifth embodiment is used, the table is loaded in succession on a plurality of arithmetic units, and the ladder block is processed. Since the table loading from the bit operation table storage unit can be executed continuously, the flash memory and DRAM with fast continuous access can achieve the effect of speeding up. In addition, when all the logical operation blocks included in the sequence can be loaded into the operation unit, the processing can be performed by loading the table only once.

  Further, according to the memory control method of the fifth embodiment, the memory control device of the fifth embodiment is used to load the ladder block by loading the tables for all the blocks included in the sequence into a plurality of arithmetic units. Since the processing is performed, when all the logical operation blocks included in the sequence can be loaded into the arithmetic unit, the processing can be performed by loading the table only once.

Embodiment 6 FIG.
In the first embodiment, the load information and the store instruction executed by the CPU 1 are used to load the contact information and the coil is written. In the sixth embodiment shown in FIG. The instruction code is read out from the instruction storage unit 32, and the block of logical operations for sequence control is processed. The instruction storage unit 32 is a memory in which an instruction sequence including an opcode and an operand shown in FIG. 11 is stored. It has a load as an opcode, an instruction consisting of a set of addresses as an operand, a store as an opcode, and an instruction consisting of a set of addresses and data as an operand. The CPU 1 and the bus arbitration unit 38 are connected by a CPU read enable line 36, a CPU write enable line 37, a CPU bus request line 26, a CPU bus acknowledge line 39, a CPU address line 2, and a CPU data line 3.

  The instruction processing unit 35 and the bus arbitration unit 38 are connected by a bus request line 29, a bus acknowledge line 40, and a bus address line 30. Similar to the CPU address line 2 of the first embodiment, some of the signal lines are extracted from the bus address line 30 as the bit selection line 14 and connected to the bit extraction / insertion unit 16. The bus arbitration unit 38 and the device memory 6 are connected by a device memory address line 25, a device memory read enable line 8, a bit selection line 14, and a device memory data line 7. The bus arbitration unit 38 and the bit extraction / insertion unit 16 are connected by a bus data line 41.

  The bus arbitration unit 38 grants access permission to one of the CPU bus request line 26 and the bus request line 29 when both the CPU 1 and the instruction processing unit 35 request access to the device memory 6. The mediation department. If there is only one request, grant permission to the requesting person. Access permission is given to the CPU 1 by enabling the CPU bus acknowledge line 39. The instruction processing unit 35 is granted permission by enabling the bus acknowledge line 40. Both the CPU 1 and the instruction processing unit 35 can access the device memory 6 by the function of the bus arbitration unit 38.

  The instruction processing unit 35 holds a start address register 42 that holds an address that specifies which address of the instructions stored in the instruction storage unit 32 is to be executed, and an address that indicates which instruction is to be executed. And an end address register 43. These registers can be set by writing access from the CPU 1. Further, from the instruction processing unit 35, the write enable line 4 and the read enable line 5 are connected to the read / write control unit 20, and the table data line 31 is connected to the table address generation unit 21, respectively. Further, the bus read enable line 27 and the bus write enable line 28 are connected from the read / write control unit 20 to the bus arbitration unit 38.

  When the start event line 34 connected to the CPU 1 becomes valid, the instruction processing unit 35 takes out the instruction at the address held in the start address register 42 from the instruction storage unit 32. The instruction is decoded and executed. After the instruction is executed, the address is incremented, the next instruction is taken out from the instruction storage unit 32, and the instruction is decoded and executed. A series of processing for executing these instructions is the same execution processing as that performed by the CPU 1 in the first embodiment. Execution is stopped when the address matches the end address register 43. Then, the end event line 33 is validated to notify the CPU 1 that the processing is completed. Other configurations and operations are the same as those in the first embodiment.

  With the above form, while the instruction processing unit 35 is executing a logical operation block, the CPU 1 processes a block including a basic instruction and an application instruction, thereby executing parallel execution and improving the speed of sequence control. can get.

  As described above, according to the memory control device of the sixth embodiment, in the memory control device that controls the value of the device memory in the programmable controller that processes the ladder composed of the logical operations of the contacts, the start event notification from the CPU A command processing unit for starting a ladder process consisting of a logical operation of a contact and notifying the CPU of an end event when the processing is completed; and a bit operation table storage unit for holding a result of the logical operation in units of bits as a table in advance And a lookup table unit that acquires and holds one table from the bit operation table storage unit, and bit data based on a bit selection input sent from the instruction processing unit from word data read from the device memory The bit extraction / insertion unit to be extracted and the bit data extracted by the bit extraction / insertion unit A data latch unit that latches the data, a bit selector unit that selects one bit from the table held in the lookup table unit according to the output of the bit data latched by the data latch unit, and writing to the device memory On the other hand, a read / write control unit that reads out word data from the device memory and rewrites the word data in which one bit of the word data is replaced with one bit output from the bit selector unit to the device memory, and a CPU and a command Since the bus arbitration unit that arbitrates access to the device memory with the processing unit is provided, the CPU does not need to perform ladder processing including logical operation of the contacts.

  In addition, according to the memory control method of the sixth embodiment, using the memory control device of the sixth embodiment, the logical operation of the contact by the instruction processing unit and the processing other than the logical operation by the CPU are executed in parallel. Therefore, for example, parallel processing is possible in which the CPU performs complex processing other than logical operation while the instruction processing unit executes logical operation of the contacts.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  1 CPU (microprocessor), 2 CPU address line, 3 CPU data line, 4 write enable line, 5 read enable line, 6 device memory, 7 device memory data line, 8 device memory read enable line, 9 device memory write enable line 10-bit operation table storage unit, 11 memory address line, 12 memory data line, 13 memory read enable line, 14-bit selection line, 15 operation result bit line, 16-bit extraction / insertion unit, 17 data latch unit, 18-bit selector unit , 19 Look-up table section, 20 Read / write control section, 21 Table address generation section, 22 operation section, 23 table selector section, 24 operation result selector section, 25 device memory address line, 26 CPU bus request line 27 Bus read enable line, 28 Bus write enable line, 29 Bus request line, 30 Bus address line, 31 Table data line, 32 Instruction storage unit, 33 End event line, 34 Start event line, 35 Instruction processing unit, 36 CPU Read enable line, 37 CPU write enable line, 38 bus arbitration unit, 39 CPU bus acknowledge line, 40 bus acknowledge line, 41 bus data line, 42 start address register, 43 end address register.

Claims (12)

In a memory control device that controls the value of a device memory in a programmable controller that processes a ladder consisting of logical operations of contacts,
A bit operation table storage unit that holds the result of the logical operation in units of bits as a table in advance;
A lookup table unit that acquires and holds one table from the bit operation table storage unit;
A bit extraction / insertion unit for extracting bit data from the word data read from the device memory based on a bit selection input;
A data latch unit that latches the bit data extracted by the bit extraction and insertion unit;
A bit selector for selecting one bit from the table held in the lookup table in accordance with the output of the bit data latched by the data latch;
Control for reading word data from the device memory in response to writing to the device memory, and writing back the word data in which one bit is replaced with one bit output from the bit selector unit to the device memory. A memory control device comprising a read / write control unit for performing   2. The memory control device according to claim 1, wherein a ladder including logical operations of the contacts is processed by an instruction executed by a CPU, and the bit selection input is given by the CPU.   The memory control device according to claim 1, wherein for a block having a plurality of coils, the output from the bit extraction / insertion unit is continuously written in the device memory by the number of coils to be output. Memory control method.   2. The memory control device according to claim 1, wherein the same table is loaded into the look-up table unit for processing of blocks having different contacts and coils but the same logic circuit configuration, and the data latch A memory control method characterized in that different contacts are latched in each section and written in the coils of the corresponding blocks.   Using the memory control device according to claim 1, for a block in which the number of contacts included in the ladder block is larger than a predetermined set value, processing is performed by dividing the block using an intermediate variable. A memory control method.   The output from the bit selector unit is input to the data latch unit, and the intermediate variable output from the bit selector unit is latched in the data latch unit at the timing of loading the next table into the lookup table unit. 6. The memory control method according to claim 5, wherein: When the number of contacts included in the ladder block is N and the value of 2 ^N is smaller than the number of bits M of the table, the lookup table unit uses the data obtained by arranging 2 ^N- bit tables and extending the number of bits as M as a table. 6. The memory control method according to claim 5, wherein a calculation result is obtained by loading the data into the memory and latching the value of the included contact.   A plurality of operation units each including the bit selector unit and the lookup table unit are provided, and an operation result selector unit that selects an output from the plurality of operation units, and the table is loaded from the plurality of operation units. The memory control device according to claim 1, further comprising a table selector unit for selecting an arithmetic unit to perform.   9. A memory control method using the memory control device according to claim 8, wherein the table is loaded in succession on the plurality of arithmetic units, and a ladder block is processed.   9. A memory control method using the memory control device according to claim 8, wherein a table for all blocks included in a sequence is loaded into the plurality of arithmetic units to process ladder blocks. In a memory control device that controls the value of a device memory in a programmable controller that processes a ladder consisting of logical operations of contacts,
A command processing unit for starting a ladder process consisting of a logical operation of the contact by a start event notification from the CPU and notifying the CPU of an end event when the process is completed,
A bit operation table storage unit that holds the result of the logical operation in units of bits as a table in advance;
A lookup table unit that acquires and holds one table from the bit operation table storage unit;
A bit extraction / insertion unit for extracting bit data from the word data read from the device memory based on a bit selection input sent from the instruction processing unit;
A data latch unit that latches the bit data extracted by the bit extraction and insertion unit;
A bit selector for selecting one bit from the table held in the lookup table in accordance with the output of the bit data latched by the data latch;
Control for reading word data from the device memory in response to writing to the device memory, and writing back the word data in which one bit is replaced with one bit output from the bit selector unit to the device memory. A read / write control unit,
A memory control device comprising: a bus arbitration unit that arbitrates access between the CPU and the instruction processing unit to the device memory.   12. A memory control method using the memory control device according to claim 11, wherein a logical operation of the contact by the instruction processing unit and a process other than the logical operation by the CPU are executed in parallel.

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