JP2007219874A - Data transfer controller and data transfer control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer controller which enables data to be efficiently transferred between a data storage means and a buffer memory when transferring data between an input/output device and the data storage means through the buffer memory, and a data transfer control method. <P>SOLUTION: The DMA controller 6 of a data transfer controller 10 includes a bit number detection part 6b for detecting the number of bits of data stored in a FIFO memory 7a (or a FIFO memory 7b) and a data transfer part 6c for transferring data between the FIFO memory 7a (or the FIFO memory 7b) and an SDRAM 5 by one cycle steal on the basis of the number of bits detected by the bit number detection part 6b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer control device and a data transfer control method, and more specifically, data including a DMA (Direct Memory Access) controller for transferring data between an input / output device and a data storage means via a buffer memory. The present invention relates to a transfer control device and a data transfer control method.

When performing DMA transfer between an input / output (I / O) device and a data storage means (here, DRAM: Dynamic Random Access Memory), in order to improve transfer efficiency, between the input / output device and the DRAM. There has been devised a DMA transfer control device that includes a first-in first-out (FIFO) memory and performs DMA transfer of data between an input / output device and a DRAM via the FIFO memory (for example, see Patent Document 1). ).
JP-A-2-227762 (FIG. 2)

  By the way, in the conventional DMA transfer control device as disclosed in Patent Document 1, the data write / read to / from the FIFO memory by the I / O device is always the capacity of the FIFO memory (for example, 4 bytes). Instead, it may be less than the capacity of the FIFO memory (for example, 2 bytes or 3 bytes). As illustrated in FIG. 7A, when 2 bytes of data to be transferred from the I / O device to the DRAM are stored in the FIFO memory (an example of a buffer memory), 1 byte is transferred by one DMA transfer. When data is DMA-transferred from the FIFO memory to the DRAM, there is a problem that the FIFO memory is inefficient because only 1 byte is transferred in spite of storing 2 bytes of data to be transferred to the DRAM.

  Further, as illustrated in FIG. 7B, when 1 byte of data to be read from the DRAM and transferred to the I / O device is stored in the FIFO memory, 1 byte is transferred by one DMA transfer. When data is transferred from the DRAM to the FIFO memory by DMA, only 1 byte is transferred to the FIFO memory even though 3 bytes of data can be stored. .

  The present invention has been made in view of such a problem, and when transferring data between the input / output device and the data storage means via the buffer memory, the data storage means and the buffer memory are efficiently used. An object of the present invention is to provide a data transfer control device and a data transfer control method capable of transferring data.

  In order to achieve the above object, the data transfer control device according to claim 1 includes an input / output device for inputting / outputting data of a predetermined number of bits at a time, and a data storage means for storing data in a readable / writable manner. A buffer memory interposed between the input / output device and data storage means for temporarily storing data of a bufferable bit number which is data of a predetermined number of times more than twice the predetermined number of bits; A data transfer control device comprising a DMA controller for controlling data transfer between the input / output device and the data storage means via a buffer memory, wherein the DMA controller is stored in the buffer memory Detecting means for detecting the number of bits of the data, and based on the number of bits detected by the detecting means, the buffer memory and the The transfer of data to and from the chromatography data storage means, characterized by comprising a data transfer means for performing one cycle steal.

  According to the above configuration, the number of bits of data stored in the buffer memory is detected by the detection means of the DMA controller, and the buffer memory and the data storage are detected by the data transfer means based on the number of bits detected by the detection means. Data transfer to and from the means is performed with one cycle steal.

  Therefore, when data is transferred from the data storage means to the buffer memory, data of the bit number that is the difference between the bufferable bit number and the bit number detected by the detection means is transferred in one cycle steal, When data is transferred from the buffer memory to the data storage means, the data of the number of bits detected by the detection means is transferred in one cycle steal so that the data is efficiently transferred between the data storage means and the buffer memory. It becomes possible to transfer.

  The data transfer control device according to claim 2 is the data transfer control device according to claim 1, wherein the data transfer means transfers the bufferable bit when transferring data from the data storage means to the buffer memory. The transfer of the data of the bit number which is the difference between the number and the bit number detected by the detecting means is performed in one cycle steal.

  According to the above configuration, when data is transferred from the data storage means to the buffer memory, the data transfer means transfers the data having the bit number that is the difference between the bufferable bit number and the bit number detected by the detection means. Since the process is performed by cycle stealing, data can be efficiently transferred from the data storage means to the buffer memory.

  The data transfer control device according to claim 3 is the data transfer control device according to claim 1 or 2, wherein the data transfer means detects the data when the data is transferred from the buffer memory to the data storage means. The data of the number of bits detected by the means is transferred in one cycle steal.

  According to the above configuration, when data is transferred from the buffer memory to the data storage means, the data of the number of bits detected by the detection means is transferred in one cycle steal by the data transfer means. Data can be efficiently transferred to the storage means.

  A data transfer control device according to a fourth aspect of the present invention is the data transfer control device according to any one of the first to third aspects, wherein the data storage means is an SDRAM, and the data transfer means includes the buffer memory and the Data transfer with the data storage means is performed by burst transfer.

  According to the above configuration, the data storage means is configured by SDRAM. Since the data transfer means transfers data between the buffer memory and the data storage means by burst transfer with one cycle steal, data can be efficiently and quickly transferred between the data storage means and the buffer memory. Can be transferred.

  A data transfer control device according to a fifth aspect is the data transfer control device according to any one of the first to fourth aspects, wherein the buffer memory is a FIFO memory.

  According to the above configuration, the number of bits of data stored in the FIFO memory is detected by the detection means of the DMA controller, and the FIFO memory and the data storage are detected by the data transfer means based on the number of bits detected by the detection means. Data transfer to and from the means is performed with one cycle steal.

  Here, since the buffer memory is a FIFO memory, data can be efficiently transferred between the data storage means and the buffer memory without performing complicated memory management for the buffer memory.

  7. The data transfer control method according to claim 6, wherein an input / output device that inputs / outputs data for a predetermined number of bits at a time, data storage means that stores data in a readable / writable manner, and the input / output device and data storage A buffer memory for temporarily storing data of a bufferable bit number which is data of a predetermined number of times more than twice the predetermined number of bits, and the input / output via the buffer memory A data transfer control method of a data transfer control device comprising a DMA controller for controlling data transfer between a device and the data storage means, wherein the DMA controller stores the data stored in the buffer memory The number of bits is detected, and data transfer between the buffer memory and the data storage means is performed based on the detected number of bits. It is characterized in that carried out in one cycle steal.

  According to the above configuration, the number of bits of data stored in the buffer memory is detected by the DMA controller. Then, based on the detected number of bits, the DMA controller transfers data between the buffer memory and the data storage means in one cycle steal.

  Therefore, when data is transferred from the data storage means to the buffer memory, data of the bit number that is the difference between the bufferable bit number and the bit number detected by the detection means is transferred in one cycle steal, When data is transferred from the buffer memory to the data storage means, the data of the number of bits detected by the detection means is transferred in one cycle steal so that the data is efficiently transferred between the data storage means and the buffer memory. It becomes possible to transfer.

  According to the data transfer control device of claim 1, when data is transferred from the data storage means to the buffer memory, the data of the bit number of the difference between the bufferable bit number and the bit number detected by the detection means When the data is transferred from the buffer memory to the data storage means, the data of the number of bits detected by the detection means is transferred by the one-cycle steal. Can be efficiently transferred between the buffer memory and the buffer memory.

  According to the data transfer control device of the second aspect, when data is transferred from the data storage means to the buffer memory, the data of the bit number of the difference between the bufferable bit number and the bit number detected by the detection means is stored. Since the transfer is performed in one cycle steal by the data transfer means, data can be efficiently transferred from the data storage means to the buffer memory.

  According to the data transfer control device of the third aspect, when data is transferred from the buffer memory to the data storage means, the data transfer of the number of bits detected by the detection means is performed by one cycle steal by the data transfer means. As a result, data can be efficiently transferred from the buffer memory to the data storage means.

  According to the data transfer control device of the fourth aspect, the data transfer means transfers the data between the buffer memory and the data storage means by burst transfer with one cycle steal. Data can be transferred to and from the buffer memory efficiently and at high speed.

  According to the data transfer control device of the fifth aspect, since the buffer memory is a FIFO memory, data can be efficiently transferred between the data storage means and the buffer memory without performing complicated memory management for the buffer memory. can do.

  According to the data transfer control method of claim 6, when data is transferred from the data storage means to the buffer memory, the data of the bit number of the difference between the bufferable bit number and the bit number detected by the detection means When data is transferred from the buffer memory to the data storage means, on the contrary, when the data of the number of bits detected by the detection means is transferred by one cycle steal, the data storage is performed. Data can be efficiently transferred between the means and the buffer memory.

  Hereinafter, a facsimile apparatus (an example of an embodiment of a data transfer control apparatus) and a data transfer control method of a facsimile apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing an example of a facsimile machine 10 according to an embodiment of the present invention. As illustrated, the facsimile machine 10 includes a control unit (CPU: Central Processing Unit) 3, a ROM (Read Only Memory) 4, an SDRAM (Synchronous Dynamic Random Access Memory) 5, a DMA (Direct Memory Access) controller 6, a FIFO ( A first-in first-out memory 7 and an I / O device 8 are provided, and the units 3 to 7 are communicably connected by a system bus 9.

  In this embodiment, the system bus 9 also functions as an address bus and a data bus, and a mode in which data DMA transfer is performed between the FIFO memory 7 and the SDRAM 5 via the system bus 9 will be described. However, the data may be transferred between the FIFO memory 7 and the SDRAM 5 via another bus.

  The control unit 3 controls each unit constituting the facsimile apparatus 10. The ROM 4 stores a control program for controlling each unit of the facsimile apparatus 10 by the control unit 3. The SDRAM 5 (an example of a data storage unit) stores various data such as image data and setting information acquired along with execution of the operation of the facsimile apparatus 10 in a readable / writable manner, in other words, capable of being written and read. , Data to be transferred to the I / O device 8 (corresponding to an input / output device: here, the I / O device 8a) and data transferred from the I / O device 8 (here, the I / O device 8b) Etc. are stored.

  The I / O device 8a (8) and the I / O device 8b (8) are input / output devices that input and output data for a predetermined number of bits (for example, 8 bits: 1 byte) at a time. For example, a CODEC (Coder and Decoder) that encodes and decodes image data by the MH, MR, and MMR methods for copying and facsimile transmission / reception, and a MODEM that modulates and demodulates facsimile transmission / reception data.

  In this embodiment, an I / O device 8a (8) that reads data read from the SDRAM 5 and written in the FIFO memory 7a (7), and data to be transferred to the SDRAM 5 are FIFO memory 7b (7). In the following description, the I / O device 8b (8) that writes data to the two I / O devices 8 is described. However, the number of the I / O devices 8 included in the facsimile apparatus 10 is not limited to two. One or three or more I / O devices 8 may be provided.

  The FIFO memory 7 temporarily stores data of a bufferable bit number (32 bits: 4 bytes here) which is data of a predetermined number of times more than twice a predetermined number of bits (here, 8 bits: 1 byte). Buffer memory to store. The facsimile machine 10 includes a FIFO memory 7 a and a FIFO memory 7 b as the FIFO memory 7. The FIFO memory 7a is interposed between the I / O device 8a and the SDRAM 5, and data that is DMA-transferred from the SDRAM 5 to the I / O device 8a is temporarily stored in the FIFO memory 7a. The FIFO memory 7b is interposed between the I / O device 8b and the SDRAM 5, and data to be DMA-transferred from the I / O device 8b to the SDRAM 5 is temporarily stored in the FIFO memory 7b. Note that the data stored in the FIFO memory 7 (7a or 7b) is processed by a first-in first-out method (FIFO method).

  The DMA controller 6 controls data transfer between the I / O device 8 and the SDRAM 5 via the FIFO memory 7. Specifically, the DMA controller 6 performs DMA transfer of data stored in the SDRAM 5 to the I / O device 8a via the FIFO memory 7a, and data of the I / O device 8b via the FIFO memory 7b. Then, transfer processing for DMA transfer to the SDRAM 5 is performed.

  The DMA controller 6 includes a plurality of channels used by each I / O device 8 (here, the I / O device 8a and the I / O device 8b) to request the DMA transfer to the DMA controller 6. A FIFO memory 7 (in this case, the FIFO memory 7a and the FIFO memory 7b) is provided for each of the channels included in the DMA controller 6.

  In addition to the above-described units 3 to 8, the facsimile apparatus 10 includes a document reading unit that reads image data of a document for copying and facsimile transmission, and an operation unit that performs various input operations by a user, although not shown. A display unit for displaying various screen information, for example, a liquid crystal display (LCD), a recording unit for recording an image of image data on paper, and a facsimile machine 10 and a G3 facsimile machine (not shown) for facsimile communication. An NCU (Network Control Unit) or the like is connected to be communicable.

  FIG. 2 is a functional configuration diagram showing an example of a main part of the present invention. The DMA controller 6 of the facsimile apparatus 10 functionally includes a transfer request reception unit 6a, a bit number detection unit 6b, and a data transfer unit 6c.

  The transfer request reception unit 6a of the DMA controller 6 receives a DMA transfer request signal DREQ (data request: DREQ1 in FIG. 1) from the I / O device 8a or a DMA transfer request from the I / O device 8b. A signal DREQ (DREQ2 in FIG. 1) is received.

  When DREQ1 from the I / O device 8a is received by the transfer request receiving unit 6a, the DMA controller 6 DMA-transfers data from the SDRAM 5 to the I / O device 8a via the FIFO memory 7a. . When the transfer request receiving unit 6a receives DREQ2 from the I / O device 8b, the DMA controller 6 DMA-transfers data from the I / O device 8b to the SDRAM 5 via the FIFO memory 7b.

  The bit number detection unit 6 b (corresponding to detection means) detects the number of bits of data stored in the FIFO memory 7. Here, the FIFO memory 7 (7a and 7b) receives a stored data amount notification signal (first detection signal and second detection signal shown in FIG. 1) indicating the number of bits of data stored in the FIFO memory 7. It is configured to be output. Then, for example, after the transfer request receiving unit 6a receives DREQ1 from the I / O device 8a, the bit number detecting unit 6b transmits a signal instructing the FIFO memory 7a to transmit a storage data amount notification signal. Then, the first detection signal is received from the FIFO memory 7a, and the number of bits of data stored in the FIFO memory 7a is detected based on the signal. Further, the bit number detection unit 6b transmits a signal instructing the FIFO memory 7b to transmit a storage data amount notification signal after the transfer request reception unit 6a receives DREQ2 from the I / O device 8b. The second detection signal is received from the FIFO memory 7b, and the number of bits of data stored in the FIFO memory 7b is detected based on the signal.

  The method for detecting the number of bits of data stored in the FIFO memory 7a or the FIFO memory 7b is not limited to this. For example, the number of bits of data stored in the FIFO memory 7a is detected. From the time when DREQ1 is input from the I / O device 8a until the time when DREQ1 is negated (invalidated), the data stored in the FIFO memory 7a is read, and the amount of data read is counted. The number of bits of data stored in the FIFO memory 7a may be detected.

  The data transfer unit 6c (corresponding to the data transfer means) transfers data between the FIFO memory 7 and the SDRAM 5 in one cycle steal based on the number of bits detected by the bit number detection unit 6b. It is. The data transfer unit 6c transfers the data from the SDRAM 5 to the FIFO memory 7, that is, here, when transferring data from the SDRAM 5 to the FIFO memory 7a, the bufferable bit number and the bit number detection unit 6b of the FIFO memory 7a. The data of the number of bits that is the difference from the number of bits detected by (1) is transferred in one cycle steal. For example, when the bufferable bit number is 32 bits (4 bytes) and the bit number detected by the bit number detection unit 6b based on the first detection signal is 8 bits (1 byte), the data transfer unit 6c The DMA transfers data of 24 bits (3 bytes) corresponding to these differences from the SDRAM 5 to the FIFO memory 7a in one cycle steal. In the cycle steal mode in which data is DMA-transferred by one cycle steal, when the control unit 3 does not use the system bus 9, DMA transfer is performed by the data transfer unit 6c of the DMA controller 6, and one DMA transfer is performed. The bus right is returned to the control unit 3 every time it is finished.

  On the other hand, the data transfer unit 6c is detected by the bit number detection unit 6b when transferring data from the FIFO memory 7 to the SDRAM 5, that is, in this embodiment, when transferring data from the FIFO memory 7b to the SDRAM 5. Transfer of data of the number of bits is performed with one cycle steal. For example, when the number of bits detected by the bit number detection unit 6b based on the second detection signal is 16 bits (2 bytes), the 16 bits (2 bytes) of data is transferred from the FIFO memory 7b to the SDRAM 5 in one cycle. DMA transfer with steel.

  Note that the data transfer unit 6c performs data transfer between the FIFO memory 7 and the SDRAM 5 by burst transfer. That is, one-cycle steal DMA transfer from the SDRAM 5 to the FIFO memory 7a and one-cycle steal DMA transfer from the FIFO memory 7b to the SDRAM 5 are performed by burst transfer. Here, burst transfer is DMA transfer in which a plurality of word data (for example, 2-byte or 3-byte data) are transferred together in one bus cycle.

  Next, the generation timing of each signal when data is DMA-transferred from the FIFO memory 7b to the SDRAM 5 in the facsimile apparatus 10 according to the present invention will be described with reference to FIG. Each signal shown in FIGS. 3 to 6 is as follows.

  “CK” (clock) is a clock signal serving as a reference for the operation of the entire facsimile apparatus 10. “DREQ” (data request) is a DMA transfer request signal for requesting DMA transfer from the I / O device 8 to the DMA controller 6. “/ BREQ” (bus request) is a signal used by the DMA controller 6 to request a bus right (here, the right of the system bus 9) from the control unit 3. “/ BACK” (bus acknowledgment) is a confirmation signal for confirming that the control unit 3 gives the bus right to the DMA controller 6. “/ DACK” (data acknowledgment) is a DMA transfer start confirmation signal output from the DMA controller 6 to the I / O device 8. “ADDRESS” is a signal indicating a row address or a column address given to the SDRAM 5. “DATA” indicates data that is DMA-transferred between the FIFO memory 7 and the SDRAM 5. “/ RD” (read) is a signal instructing reading of data from the FIFO memory 7. “/ CS” (chip select) is a signal for selecting the SDRAM 5 as a device to be processed. “/ RAS” (row address strobe) is a signal indicating that data (address) on an address bus (not shown) is ROW (row). “/ CAS” (column address strobe) is a signal indicating that the data (address) on the address bus is COLUMN (column). “/ WE” (write enable) is a signal instructing writing of data to the SDRAM 5. “/ WR” (write) shown in FIGS. 5 and 6 is a signal instructing writing of data into the FIFO memory 7. A signal to which “/” is not assigned indicates that the signal is high active, and a signal to which “/” is assigned indicates that the signal is low active.

  As shown in FIG. 3, the transfer request reception unit 6a of the DMA controller 6 receives the DREQ (here, DREQ2) from the I / O device 8b (when it becomes high active), the control unit 3 In order to request the bus right, / BREQ is output (set to low active). On the other hand, the control unit 3 outputs / BACK to the DMA controller 6 (sets it to low active) to give the DMA right to the DMA controller 6. The DMA controller 6 can use the system bus 9 to perform DMA transfer while / BACK is input from the control unit 3.

  As described above, when / BACK from the control unit 3 is input and the transfer request receiving unit 6a of the DMA controller 6 receives a DMA transfer request from the I / O device 8b, the bit number detecting unit 6b stores in the FIFO memory 7b. The second detection signal is received from the FIFO memory 7b, and the number of bits of data stored in the FIFO memory 7b is detected based on the signal. Here, for example, when the bit number detection unit 6b detects that the number of bits of data stored in the FIFO memory 7b is 24 bits (3 bytes), each of the FIFO memory 7b includes 8 bits (1 byte). ) Data D1, D2, and D3 of 3 bytes of data are stored, the data transfer unit 6c receives a DMA transfer start confirmation signal / DACK (here, / DACK) to the I / O device 8b. DACK2) and / RD, which is a signal for instructing the FIFO memory 7b to read data, and continuously read out three bytes of data D1 to D3 from the FIFO memory 7b (in FIG. 3) FIFO read cycle).

  Subsequently, / CS is input to the SDRAM 5 in order to select a device to which the data D1 to D3 read from the FIFO memory 7b are to be written. At the same time, the row address R is input to the SDRAM 5 together with / RAS indicating that the data on the address bus is a row address, and then the column address C1 together with / CAS indicating that the data on the address bus is a column address. , C2, C3 are input to the SDRAM 5. As a result, the address of 3 bytes of data to be written to the SDRAM 5 is designated, so that the column addresses C1, C2, and C3 are designated for the data D1, D2, and D3 of 3 bytes read from the FIFO memory 7b. At the same time, it is written to the designated address of the SDRAM 5 (SDRAM write cycle in FIG. 3).

  As described above, when data is transferred from the FIFO memory 7b to the SDRAM 5, the number of bits of data stored in the FIFO memory 7b is detected by the bit number detection unit 6b of the DMA controller 6, and the data transfer unit 6c Data transfer of the number of bits (here, 24 bits: 3 bytes) detected by the bit number detection unit 6b is performed by burst transfer with one cycle steal.

  Next, the generation timing of each signal when data is DMA-transferred from the FIFO memory to the SDRAM in the conventional data transfer control device will be described with reference to FIG. Although not shown, this conventional data transfer control device is assumed to include a general control unit, I / O device, SDRAM, FIFO memory, and DMA controller. In addition, it is assumed that 3 bytes of data are stored in the FIFO memory having a bufferable bit number of 32 bits (4 bytes).

  As shown in the figure, when the DREQ from the I / O device is input, the DMA controller of the conventional data transfer control device outputs / BREQ to request the bus right from the control unit. On the other hand, the control unit outputs / BACK to give the bus right to the DMA controller. The DMA controller that has received / BACK does not know how many bytes of data are stored in the FIFO memory having the bufferable number of bits (32 bits: 4 bytes), so the DMA transfer start confirmation signal to the I / O device / DACK is output, and / RD is output to the FIFO memory to read one byte of data D1 from the FIFO memory (FIFO read cycle in FIG. 4).

  Subsequently, / CS is input to the SDRAM to select a device to which the data D1 read from the FIFO memory is to be written. At the same time, the row address R is input to the SDRAM together with / RAS indicating that the data on the address bus is a row address, and then the column address is combined with / CAS indicating that the data on the address bus is a column address. C1 is input to the SDRAM. As a result, the address of 1-byte data to be written to the SDRAM is designated, so that the 1-byte data D1 read from the FIFO memory is written to the SDRAM at the same time as the column address C1 is designated (see FIG. 4 SDRAM write cycle in 4).

  In this way, when one byte of data D1 is DMA-transferred from the FIFO memory to the SDRAM, the DMA controller returns the bus right to the control unit. The DMA controller receives the DREQ from the I / O device again, and DMA transfers the data D2 of the FIFO memory to be transferred next to the SDRAM. As described above, in the conventional data transfer control device, when 3 bytes of data D1 to D3 are stored in the FIFO memory, the transfer process of DMA transferring 1 byte of data by one DMA transfer is performed three times. Repeatedly, 3 bytes of data D1 to D3 stored in the FIFO memory are transferred to the SDRAM.

  As is clear from the description based on FIGS. 3 and 4 above, in the conventional data transfer control device, although data to be transferred to the SDRAM is stored in 3 bytes in the FIFO memory, only 1 byte is transferred by DMA. However, in the facsimile apparatus 10 according to the present invention, when data is transferred from the FIFO memory 7b to the SDRAM 5, the bit number detection unit 6b detects the number of bits of the data stored in the FIFO memory 7b and transfers the data. The data of the number of bits detected by the bit number detection unit 6b is burst transferred by the unit 6c with one cycle steal.

  Therefore, according to the facsimile apparatus 10 according to the present invention, the DMA transfer of data from the FIFO memory 7b to the SDRAM 5 can be performed efficiently and at a higher speed than the conventional data transfer control apparatus.

  Next, the generation timing of each signal when data is DMA-transferred from the SDRAM 5 to the FIFO memory 7a in the facsimile apparatus 10 according to the present invention will be described with reference to FIG. As shown in the figure, the transfer request reception unit 6a of the DMA controller 6 requests / BREQ to request the bus right from the control unit 3 when DREQ (DREQ1 in this case) is input from the I / O device 8a. Is output. On the other hand, the control unit 3 outputs / BACK to the DMA controller 6 to give the DMA right to the DMA controller 6. The DMA controller 6 can use the system bus 9 to perform DMA transfer while / BACK is input from the control unit 3.

  As described above, when / BACK from the control unit 3 is input and the transfer request receiving unit 6a of the DMA controller 6 receives a DMA transfer request from the I / O device 8a, the bit number detecting unit 6b stores in the FIFO memory 7a. The first detection signal is received from the FIFO memory 7a, and the number of bits of data stored in the FIFO memory 7a is detected based on the signal. Here, for example, when the bit number detection unit 6b detects that the number of bits of data stored in the FIFO memory 7a is 8 bits (1 byte), the data transfer unit 6c uses the bufferable bit number (32 24 bits (3 bytes), which is the difference between the number of bits (4 bytes) and the number of bits detected by the bit number detector 6b (here, 8 bits), is read from the SDRAM 5.

  Specifically, / CS is input to the SDRAM 5 in order to select a device that reads data of 3 bytes of 8-bit (1-byte) data D1, D2, and D3 to be DMA-transferred to the FIFO memory 7a. At the same time, the row address R is input to the SDRAM 5 together with / RAS indicating that the data on the address bus is a row address, and then the column address is combined with / CAS indicating that the data on the address bus is a column address. C1, C2, and C3 are input to the SDRAM 5. As a result, the address of 3 bytes of data to be read from the SDRAM 5 is designated, so that the data D1, D2, and D3 of 3 bytes from the SDRAM 5 are successively transmitted with one clock delay from the column addresses C1, C2, and C3. Read (SDRAM read cycle in FIG. 5).

  Subsequently, the data transfer unit 6c outputs / DACK (here, / DACK1), which is a DMA transfer start confirmation signal, to the I / O device 8a, and at the same time, sends data to the FIFO memory 7a to the FIFO memory 7a. Data write instruction / WR is output, and 3 bytes of data D1 to D3 are continuously written in the FIFO memory 7a (FIFO write cycle in FIG. 5).

  As described above, when data is transferred from the SDRAM 5 to the FIFO memory 7a, the bit number detection unit 6b of the DMA controller 6 detects the number of bits of data stored in the FIFO memory 7a, and the data transfer unit 6c The bit number (here, 24 bits: 3) of the difference between the bufferable bit number (here, 32 bits: 4 bytes) and the number of bits detected by the bit number detector 6b (here, 8 bits: 1 byte) Byte) data is transferred by burst transfer at one cycle steal.

  Next, the generation timing of each signal when data is DMA-transferred from the SDRAM to the FIFO memory in the conventional data transfer control device similar to that described with reference to FIG. 4 will be described with reference to FIG. It is assumed that the bufferable bit number of the FIFO memory is 32 bits (4 bytes), and 1-byte data is stored in the FIFO memory.

  As shown in the figure, when the DREQ from the I / O device is input, the DMA controller outputs / BREQ to request a bus right from the control unit. On the other hand, the control unit outputs / BACK to give the bus right to the DMA controller. The DMA controller that has received / BACK does not know how many bytes of data are stored in the FIFO memory having the number of bufferable bits (32 bits: 4 bytes), and therefore selects a device from which data D1 to be written to the FIFO memory is to be read. Therefore, / CS is input to the SDRAM. Then, the row address R is input to the SDRAM together with / RAS indicating that the data on the address bus is a row address. Subsequently, the column address C1 is displayed together with / CAS indicating that the data on the address bus is a column address. Input to SDRAM. As a result, the address of 1-byte data to be read from the SDRAM is designated, so that 1-byte data D1 is read from the SDRAM with a delay of 1 clock after the column address C1 is designated (in FIG. 6). SDRAM read cycle).

  Subsequently, the DMA controller outputs / DACK that is a DMA transfer start confirmation signal to the I / O device, and simultaneously outputs / WR to the FIFO memory and reads from the SDRAM to the FIFO memory. 1 byte of data D1 is written (FIFO write cycle in FIG. 6).

  In this way, when one byte of data D1 is DMA-transferred from the SDRAM to the FIFO memory, the DMA controller returns the bus right to the control unit. The DMA controller receives the DREQ from the I / O device again, and DMA-transfers the SDRAM data D2 to be transferred next to the FIFO memory. As described above, in the conventional data transfer control device, even when 3 bytes of data can be stored in the FIFO memory, the transfer process of DMA transferring 1 byte of data in one DMA transfer is repeated three times in the SDRAM. The stored 3-byte data D1 to D3 are transferred to the FIFO memory.

  As is apparent from the description based on FIGS. 5 and 6 above, in the conventional data transfer control device, although there is a free area in the FIFO memory that can store 3 bytes of data, only one byte at a time is DMA. Although not transferred, in the facsimile apparatus 10 according to the present invention, when data is transferred from the SDRAM 5 to the FIFO memory 7a, the number of bits of the data stored in the FIFO memory 7a is detected by the bit number detection unit 6b. The transfer unit 6c burst-transfers data of the bit number that is the difference between the bufferable bit number and the bit number detected by the bit number detection unit 6b in one cycle steal.

  Therefore, according to the facsimile apparatus 10 according to the present invention, the DMA transfer of data from the SDRAM 5 to the FIFO memory 7a can be performed efficiently and at a higher speed than the conventional data transfer control apparatus.

In addition, this invention is not limited to the said embodiment, The following forms may be sufficient.
That is, in the present embodiment, the mode in which the data transfer control apparatus is the facsimile apparatus 10 has been described. However, the configuration of the facsimile apparatus 10 is only one aspect of the data transfer control apparatus according to the present invention, and the gist of the present invention. The data transfer control device according to the present invention can of course be applied to, for example, a copying machine, an Internet facsimile machine, a scanner, a printer, and a complex machine thereof.

  Further, in the present embodiment, the mode in which the data storage means is the SDRAM 5 has been described. However, the data storage means is not limited to the SDRAM 5, and for example, a DRAM (Dynamic RAM) or a DDR SDRAM (Double Data Rate SDRAM). ).

  In the present embodiment, the data storage means is composed of the SDRAM 5, and the data transfer unit 6c has been described as performing data transfer between the FIFO memory 7 and the SDRAM 5 by burst transfer. You may make it perform. Single transfer is DMA transfer in which one word data is transferred in one bus cycle. In the present embodiment, the transfer request receiving unit 6a is configured to receive DREQ from the I / O device and output / DACK to the I / O device. However, the DREQ is input from the FIFO to the FIFO. / DACK may be output.

  The present invention is applicable to, for example, a data transfer control device and a data transfer control method including a DMA controller that performs data transfer between an input / output device and a data storage unit via a buffer memory.

1 is a configuration diagram showing an example of a facsimile apparatus according to the present invention. FIG. 2 is a functional configuration diagram illustrating an example of a main part of a facsimile apparatus according to the present invention. 6 is a timing chart illustrating the generation timing of each signal when data is DMA-transferred from the FIFO memory to the SDRAM in the facsimile apparatus according to the present invention. 10 is a timing chart showing generation timing of each signal when data is DMA-transferred from a FIFO memory to an SDRAM in a conventional data transfer control device. 5 is a timing chart illustrating the generation timing of each signal when data is DMA-transferred from the SDRAM to the FIFO memory in the facsimile apparatus according to the present invention. 6 is a timing chart showing the generation timing of each signal when data is DMA-transferred from SDRAM to FIFO memory in a conventional data transfer control device. (A) is a diagram illustrating DMA transfer of data from an I / O device to a DRAM via a FIFO memory, and (b) is a DMA of data from the DRAM to the I / O device via a FIFO memory. It is the figure which illustrated transfer.

Explanation of symbols

3 Control section 5 SDRAM (data storage means)
6 DMA controller (detection means, data transfer means)
7a (7), 7b (7) FIFO memory (buffer memory)
8a (8), 8b (8) I / O device (input / output device)
10 Facsimile device (data transfer control device)

Claims (6)

An input / output device that inputs and outputs a predetermined number of bits of data at a time;
Data storage means for storing data in a readable and writable manner;
A buffer memory interposed between the input / output device and data storage means for temporarily storing data of a bufferable bit number which is data of a predetermined number of times greater than or equal to twice the predetermined number of bits;
A data transfer control device comprising a DMA controller for controlling data transfer between the input / output device and the data storage means via the buffer memory,
The DMA controller comprises detection means for detecting the number of bits of the data stored in the buffer memory;
Data transfer control comprising data transfer means for transferring data between the buffer memory and the data storage means in one cycle steal based on the number of bits detected by the detection means apparatus.   When the data transfer means transfers data from the data storage means to the buffer memory, the data transfer means transfers data having a bit number that is the difference between the bufferable bit number and the bit number detected by the detection means. The data transfer control device according to claim 1, wherein the data transfer control device is cycle steal.   2. The data transfer means, when transferring data from the buffer memory to the data storage means, transfers data of the number of bits detected by the detection means in one cycle steal. Or the data transfer control device according to 2; The data storage means is an SDRAM,
The data transfer control device according to any one of claims 1 to 3, wherein the data transfer means performs data transfer between the buffer memory and the data storage means by burst transfer.   The data transfer control device according to claim 1, wherein the buffer memory is a FIFO memory. An input / output device that inputs and outputs a predetermined number of bits of data at a time;
Data storage means for storing data in a readable and writable manner;
A buffer memory interposed between the input / output device and data storage means for temporarily storing data of a bufferable bit number which is data of a predetermined number of times greater than or equal to twice the predetermined number of bits;
A data transfer control method of a data transfer control device comprising a DMA controller for controlling data transfer between the input / output device and the data storage means via the buffer memory,
The DMA controller detects the number of bits of the data stored in the buffer memory;
A data transfer control method, wherein data transfer between the buffer memory and the data storage means is performed in one cycle steal based on the detected number of bits.

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