JP2015170293A - Data processing device and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a high-speed data transfer between a plurality of functional modules connected to a bus.SOLUTION: A data processing device comprises: a bus 101 that relates to a data transfer; a plurality of functional modules 50 and 60 that is connected to the bus 101 ; and a plurality of temporary storage devices 10 and 20 that is connected to the bus 101 and has an order of writing and reading data defined. Each of the plurality of functional modules 50 and 60, and the plurality of temporary storage devices 10 and 20 includes bus connection interfaces 11, 12, 21, 22, 52, 53, 62 and 63 for connecting to the bus 101, and these bus connection interfaces have a bus address capable of uniquely identifying the bus connection interface allocated. Then, the processing device is configured to simultaneously execute the data transfer between one of the plurality of functional modules and one of the plurality of temporary storage devices and the data transfer between the other of the plurality of functional modules and the other of the plurality of temporary storage devices.

Description

  The present invention relates to a data processing apparatus and a data transfer method, and more particularly to a technique for improving a data transfer speed between a plurality of functional modules connected to the same bus.

  Peripheral IO devices, such as HDD (Hard disk drive), SSD (Solid State Drive), USB (Universal Serial Bus), SD card, PCI Express (registered trademark), etc., data processing (image processing, compression / decompression, As the speed of encryption and decryption increases, a master type DMAC (Direct Memory Access Controller) is often provided for each functional module. Each functional module and memory are connected to a bus. When data is transferred between master type DMACs, it is necessary to execute data transfer via a shared memory.

  If the data processing order is fixed (reversal is not allowed), it is necessary to read from the memory after waiting for completion of writing to the memory. Alternatively, it is necessary to provide a sideband signal between the write DMAC and the read DMAC so that the progress of each data transfer can be monitored and the transfer is awaited according to the progress of the data transfer.

  As a method of executing data transfer between master type DMACs without going through a memory, Patent Document 1 discloses a first-in first-out (FIFO) circuit having a capacity necessary for transfer between master type DMACs. A configuration for connecting to a bus is disclosed. As is clear from the fact that the FIFO of Patent Document 1 can input and output data, it has two slave interfaces, and each slave interface is connected to a bus. One slave interface is used for data input to the FIFO, and the other slave interface is used for data output. Then, the master type DMAC on the data transmitting side outputs data to the slave data input interface of the FIFO, and the master type DMAC on the data receiving side passes the data through the slave interface for FIFO data output. Receive. Since the FIFO is used, the data transfer order (write and read) can be protected naturally.

  However, as described in Patent Document 1, in the method of executing data transfer between master DMACs via a single FIFO connected to the bus, the FIFO is used for data transfer between a pair of master DMACs. In this case, the FIFO cannot be used for data transfer between other master type DMACs. In this case, since the transfer is executed via the shared memory instead of the FIFO, the read operation is executed after completion of the write operation to the shared memory, and the transfer speed is lowered. Also, the transfer rate decreases when access to the shared memory is congested. Therefore, in Patent Document 1, when there are a plurality of master type DMACs, the problem that the data transfer rate between other master type DMACs decreases while using a FIFO for data transfer between a pair of master type DMACs is solved. Not done.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a data processing apparatus and a data transfer method capable of transferring data between a plurality of functional modules connected to a bus at high speed.

  In order to solve the above-described problems, a data processing device according to the present invention includes a bus for data transfer, a plurality of functional modules connected to the bus, and the data written in advance from the data connected to the bus. A plurality of temporary storage devices for reading data, and each of the plurality of functional modules and the plurality of temporary storage devices includes a bus connection interface for connecting to the bus, and each of the plurality of temporary storage devices Included in the bus connection interface includes an input interface for receiving data input from the bus to the temporary storage device and an output interface for outputting data from the temporary storage device to the bus, the bus connection interface, The input interface and the output interface are respectively A uniquely identifiable bus address is assigned, data transfer between one of the plurality of functional modules and one of the plurality of temporary storage devices, and the other of the plurality of functional modules and the plurality of temporary storage devices The data transfer between the other is formed so as to be executed simultaneously.

  Further, the data transfer method according to the present invention includes a bus for data transfer, a plurality of functional modules connected to the bus, and a plurality of temporary data connected to the bus and reading the data in order from the previously written data. Each of the plurality of functional modules and the plurality of temporary storage devices includes a bus connection interface for connecting to the bus, and each of the plurality of temporary storage devices. The included bus connection interface includes an input interface that receives input of data from the bus to the temporary storage device and an output interface that outputs data from the temporary storage device to the bus. The bus connection interface, the input Interface, and the output interface A bus address uniquely identifiable is assigned, data transfer between one of the plurality of functional modules and one of the plurality of temporary storage devices, and the other of the plurality of functional modules and the plurality of temporary storages Data transfer between the other devices is performed simultaneously.

  According to the present invention, it is possible to provide a data processing apparatus and a data transfer method capable of transferring data between a plurality of functional modules connected to a bus at high speed.

The figure which shows the structure of the data processing apparatus to which this invention is applied 2 is a diagram showing the configuration of the functional module shown in FIG. 1 in more detail, (a) shows the configuration of the compression / decompression processing unit, (b) shows the configuration of the encryption / decryption processing unit, and (c) shows SATA. The structure of a control part is shown. Explanatory diagram showing an example of bus address assignment The figure which shows the data flow in the data transfer operation | movement at the time of compression, encryption, and writing in HDD The figure which shows the processing operation along the time series at the time of compression, encryption, and writing to HDD The figure which shows the processing operation in time series at the time of decoding, decompression, and writing to memory

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the configuration of the data processing apparatus according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing a configuration of a data processing apparatus to which the present invention is applied. 2 is a diagram showing the configuration of the functional module shown in FIG. 1 in more detail. (A) shows the configuration of the compression / decompression processing unit, (b) shows the configuration of the encryption / decryption processing unit, c) shows the configuration of the SATA control unit.

  As shown in FIG. 1, the data processing apparatus 1 has two buses with different data transfer rates. Among these buses, a bus with a high data transfer rate is called a high-speed bus 101, and a low bus is called a low-speed bus 102.

  The data processing device 1 includes two FIFO circuits (hereinafter abbreviated as “FIFO”) as temporary storage devices. These FIFOs are referred to as FIFO_A (reference numeral 10) and FIFO_B (reference numeral 20). Further, the data processing apparatus 1 includes a memory 30, a SATA (Serial ATA) control unit 40, an encryption / decryption unit 50, a compression / decompression unit 60, a general-purpose DMAC 70, a CPU (Central Processing Unit) 80, and a flash ROM (Read Only Memory) 90. And HDD 103. Hereinafter, the memory 30, the SATA control unit 40, the encryption / decryption device 50, the compression / decompression device 60, the general-purpose DMAC 70, the CPU 80, and the flash ROM 90 are generalized and referred to as functional modules.

  Each functional module has a bus connection interface (hereinafter abbreviated as “interface”) for connection to the high-speed bus 101 or the low-speed bus 102. Each interface is classified into a master interface or a slave interface from the classification of the master / slave function. Each interface is classified into an input interface that receives data input and an output interface that receives data output. Each interface is assigned a bus address that can uniquely identify the interface. Details of these will be described later.

  FIFO_A 10, FIFO_B 20, memory 30, CPU 80, and flash ROM 90 are connected to the high-speed bus 101.

  The SATA control unit 40, the encryption / decryption device 50, the compression / decompression device 60, and the general-purpose DMAC 70 are connected to the high-speed bus 101 and the low-speed bus 102, respectively.

  The FIFO_A 10 is a temporary storage device that can sequentially retrieve data from previously stored data. The FIFO_A 10 has an input slave interface 11 and an output slave interface 12, and is connected to the high-speed bus 101 via each slave interface. Then, it can be accessed from any functional module having a master interface connected to the high-speed bus 101.

  The input slave interface 11 receives data transmitted from an arbitrary master interface having a transmission function. The received data is stored in FIFO_A10. A functional module having a master interface having a transmission function can perform data input to the FIFO_A 10 by executing a write operation on an address assigned to the input slave interface 11.

  The output slave interface 12 transmits the data stored in the FIFO_A 10 to an arbitrary master interface having a reception function. A functional module having a master interface having a reception function can acquire data stored in the FIFO_A 10 by executing a read operation on the address assigned to the output slave interface 12.

  In the present embodiment, the input slave interface 11 and the output slave interface 12 are connected to the high-speed bus 101 with a data bus width of 128 bits. The storage capacity of FIFO_A10 is 8 burst operations × 2 times = 8 × 128 bits × 2 = 2048 bits = 256 bytes. Here, 8 bursts is the number of bursts of the SATA control unit 40 that uses the FIFO_A 10 most frequently.

  By making the storage capacity of the FIFO_A10 twice as large as the burst transfer size of one time of the SATA control unit 40, which is the functional module having the highest data transfer frequency, the balance between the transfer speed and the circuit scale using the FIFO_A10 is balanced. Can take.

  The FIFO_B 20 is a temporary storage device that can extract data in order from the previously stored data, like the FIFO_A 10. The FIFO_B 20 has an input slave interface 21 and an output slave interface 22, and is connected to the high-speed bus 101 via each slave interface. Then, it can be accessed from any functional module having a master interface connected to the high-speed bus 101.

  The input slave interface 21 receives data transmitted from an arbitrary master interface having a transmission function, and the received data is stored in the FIFO_B 20. A functional module having a master interface having a transmission function can perform data input to the FIFO_B 20 by executing a write operation on an address assigned to the input slave interface 21.

  The output slave interface 22 transmits the data stored in the FIFO_B 20 to an arbitrary master interface having a reception function. A module having a master interface having a reception function can acquire data stored in the FIFO_B 20 by executing a read operation on the address assigned to the output slave interface 22.

  In the present embodiment, the input slave interface 21 and the output slave interface 22 are connected to the high-speed bus 101 with a data bus width of 128 bits. The storage capacity of the FIFO_B 20 is 16 burst operations × 2 times = 16 × 128 bits × 2 = 4096 bits = 512 bytes. Here, 16 bursts are the number of operations in the functional module having the maximum burst operation performed by one burst transfer among the functional modules connected to the high-speed bus 101. Therefore, a functional module that performs 16 bursts in one burst transfer can be said to be a functional module that has a maximum data size to be transferred in one burst transfer.

  By making the storage capacity of FIFO_B20 twice the size of one burst transfer of the function module with the maximum data size transferred in one burst transfer, the burst transfer performance of any functional module connected to the bus can be increased. There is an effect that can be maximized.

  The storage capacities of FIFO_A10 and FIFO_B20 may be twice the data bus width of each interface of FIFO_A10 and FIFO_B20 in addition to the above-described determination method. Thereby, when the speed at which data is input to FIFO_A10 and FIFO_B20 is equal to the speed at which data is output from FIFO_A10 and FIFO_B20, the data transfer speed can be maintained with a minimum storage capacity.

  Further, the storage capacity of the FIFO_A 10 is set to a storage capacity twice as large as the burst transfer size of one time of the function module (SATA control unit 40) having the highest data transfer frequency using the FIFO_A 10, and the storage capacity of the FIFO_B 20 is set to the data transfer frequency. The storage capacity of the second highest module, for example, twice the burst transfer size of the memory 30 may be used. Thereby, it is possible to balance the data transfer speed and the circuit scale of the FIFO_A 10 and the FIFO_B 20.

  The high-speed bus 101 mediates data transfer between a function module having an arbitrary master interface and a function module having an arbitrary slave interface, and executes data transfer between a plurality of sets of master / slave modules in parallel. be able to. In the present embodiment, a band of several GB / s is assumed.

  The low-speed bus 102 is used for transmission / reception of data that does not require high-speed transfer (setting information of each functional module), and data between a functional module having an arbitrary master interface and a functional module having an arbitrary slave interface When data transfer is being performed between a pair of master / slave modules via transfer, data transfer between other master / modules cannot be executed. In this embodiment, a bandwidth of several tens of MByte / s is assumed.

  The high-speed bus 101 and the low-speed bus 102 are connected via a master interface included in the high-speed bus 101 and a slave interface included in the low-speed bus 102.

  The CPU 80 sets the operation of each functional module and executes main control of the data processing device 1. The CPU 80 has an input / output master interface 81 for data transmission / reception, and can access a module having an arbitrary slave interface connected to the bus through the input / output master interface 81. Each slave interface is assigned an address range or a specific address value according to the specification of the slave module. By specifying this address, it is possible to access a desired slave module. The address of the slave interface provided in each module will be described later with reference to FIG.

  The flash ROM 90 stores a boot program and is accessed from the CPU 80 when the system is started.

  An address range corresponding to the capacity of the flash ROM 90 is assigned to the input / output slave interface 91, and a functional module having an arbitrary master interface connected to the bus accesses the flash ROM 90 by specifying this address. can do.

  The general-purpose DMAC 70 has an input master interface 72 and an output master interface 73, and is connected to the high-speed bus 101 via these, and accesses any functional module having a slave interface connected to the bus. can do.

  The general-purpose DMAC 70 can read data from a functional module having an arbitrary output slave interface through the input master interface 72, and can write data to a functional module having an arbitrary input slave interface through the output master interface 73.

  The general-purpose DMAC 70 further has an input / output slave interface 71, and is connected to the low-speed bus 102 via this. The setting of the general-purpose DMAC 70 (read target slave module, write target slave module, transfer data size, etc.) is executed by the CPU 80 through the input / output slave interface 71 connected to the low-speed bus 102.

  The memory 30 is used as a work area for each functional module, such as storing an operation program of the CPU 80 read from the HDD 103 or storing data processed by the CPU 80.

  The memory 30 has an input / output slave interface 31. An address range corresponding to the capacity of the memory 30 is assigned to the input / output slave interface 31, and a functional module having an arbitrary master interface connected to the bus accesses the memory 30 by designating this address. can do.

  As shown in FIG. 2A, the compressor / decompressor 60 includes an input / output slave interface 61 connected to the low speed bus 102, an input master interface 62 connected to the high speed bus 101, and an output master interface 63. Further, the compressor / decompressor 60 includes a master type reception DMAC 64, a master type transmission DMAC 65, and a compression / decompression processing unit 66.

  The receiving DMAC 64 is connected to the high-speed bus 101 through the input master interface 62. The transmission DMAC 65 is connected to the high-speed bus 101 through the output master interface 63. The reception DMAC 64 can access any functional module having an output slave interface having a transmission function, and the transmission DMAC 65 can access any functional module having an input slave interface having a reception function. it can.

  The compression / decompression processing unit 66 performs data processing by switching between a compression operation mode for compressing data input via the input master interface 62 and the receiving DMAC 64 or a decompression operation mode for performing expansion processing.

  In the compression operation mode, data to be compressed is acquired through the input master interface 62, and compressed data is output through the output master interface 63.

  The operation mode of the compression / decompression processing unit 66 is set by the CPU 80 through the input / output slave interface 61 connected to the low-speed bus 102. The settings of the reception DMAC 64 and the transmission DMAC 65 (read target slave module, write target slave module, transfer data size, etc.) are also set by the CPU 80 through the input / output slave interface 61.

  The encryption / decryption device 50 includes an input / output slave interface 51 connected to the low-speed bus 102, an input master interface 52 and an output master interface 53 connected to the high-speed bus 101, as shown in FIG. Further, the encryption / decryption device 50 includes a master type reception DMAC 54, a master type transmission DMAC 55, and an encryption / decryption processing unit 56.

  The receiving DMAC 54 is connected to the high-speed bus 101 through the input master interface 52. The transmission DMAC 55 is connected to the high-speed bus 101 through the output master interface 53. The reception DMAC 54 can access any functional module having an output slave interface having a transmission function, and the transmission DMAC 55 can access any functional module having an input slave interface.

  The encryption / decryption device 50 includes an encryption operation mode for encrypting data input via the input master interface 52 and the reception DMAC 54, and a decryption mode for decryption. Data processing is performed by switching to one of the operation modes. I do.

  The encryption / decryption device 50 acquires data to be encrypted in the encryption operation mode through the input master interface 52 and outputs the encrypted data through the output master interface 53.

  In the decryption operation mode, the encrypted data is acquired through the input master interface 52, and the decrypted data is output through the output master interface 53.

  The operation mode of the encryption / decryption device 50 is set by the CPU 80 through the input / output slave interface 51 connected to the low-speed bus 102. The CPU 80 also sets the settings of the reception DMAC 54 and the transmission DMAC 55 (read target slave module, write target slave module, transfer data size, etc.) through the input / output slave interface 51.

  The SATA control unit 40 includes an input / output slave interface 41 connected to the low speed bus 102 and an input / output master interface 42 connected to the high speed bus 101 as shown in FIG. Further, the SATA control unit 40 includes a master type DMAC for transmission / reception (hereinafter referred to as “transmission / reception DMAC”) 44 and a SATA host controller 46 for controlling a device compliant with the SATA standard.

  The transmission / reception DMAC 44 is connected to the high-speed bus 101 through the input / output master interface 42. The transmission / reception DMAC 44 can access any functional module having an input slave interface having a reception function.

  The SATA host controller 46 executes data write / data read to the HDD 103. The SATA command setting and the acquisition of the status information of the HDD 103 are executed by the CPU 80 through the input / output slave interface 41 connected to the low-speed bus 102. Further, the CPU 80 also executes the setting of the transmission / reception DMAC 44 (read target slave module, write target slave module, transfer data size, etc.) through the input / output slave interface 41.

  The HDD 103 is a storage device that conforms to the SATA standard, and is used for storing an OS, application programs, etc., and a temporary save area for processing data.

  Next, an example of bus address allocation in the data processing apparatus according to the present embodiment will be described with reference to FIG. FIG. 3 is an explanatory diagram showing an example of bus address assignment.

  The flash ROM area 910 shown in FIG. 3 is an area that can be accessed through the input / output slave interface 91, and addresses 0x0008 — 0000 to 0x000F_FFFF are assigned.

  The system control register area 810 is an area for setting an operation mode of the CPU 80, and addresses 0x0010 — 0000 to 0x0010 — 0FFF are allocated.

  The SATA control register area 410 is an area that can be accessed through the input / output slave interface 41, and is assigned addresses 0x0010_1000 to 0x0010_1FFF.

  The encryption / decryptor control register area 510 is an area that can be accessed through the input / output slave interface 51, and is assigned addresses 0x0010_2000 to 0x0010_2FFF.

  The compressor / decompressor control register area 610 is an area that can be accessed through the input / output slave interface 61, and is assigned addresses 0x0010_3000 to 0x0010_3FFF.

  The general-purpose DMAC control register area 710 is an area that can be accessed through the input / output slave interface 71, and is assigned addresses 0x0010_4000 to 0x0010_4FFF.

  The FIFO_A (input) area 110 is an area that can be accessed through the input slave interface 11 and is assigned an address 0x0020_0000.

  The FIFO_A (output) area 120 is an area that can be accessed through the output slave interface 12, and is assigned an address 0x0020_1000.

  The FIFO_B (input) area 210 is an area that can be accessed through the input slave interface 21 and is assigned an address 0x0020_2000.

  The FIFO_B (output) area 220 is an area that can be accessed through the output slave interface 22, and is assigned an address 0x0020_3000.

  The memory area 310 is an area that can be accessed through the input / output slave interface 31 and is assigned addresses 0x8000 — 0000 to 0xFFFF_FFFF.

  Hereinafter, an example of data transfer operation in the case where data stored in the memory 30 is compressed and encrypted and then written to the HDD 103 will be described with reference to FIGS. FIG. 4 is a diagram showing a data flow in a data transfer operation when compression, encryption, and writing to the HDD. FIG. 5 is a diagram showing processing operations in time series when compression, encryption, and writing to HDD. A solid line indicates a state in which processing is simultaneously performed at a certain timing, and a dotted line indicates the timing. The processing performed before is shown.

  In the read operation from the memory, the compression, the encryption, and the write operation to the HDD 103, data transfer is performed by the function of the DMAC included in each functional module without using the CPU as shown in FIG. Hereinafter, a series of processing operations will be described in the order of steps in FIG.

  The compressor / decompressor 60 uses the input master interface 62 to access the input / output slave interface 31 of the memory 30 and read the data stored in the memory 30 (S501).

  After the read data is compressed by the compression / decompression processor 66 (S502), the compressed data is transmitted to the input slave interface 21 of the FIFO_B 20 using the output master interface 63 (S503).

  The FIFO_B 20 receives the compressed data at the input slave interface 21 and stores it in the FIFO_B 20 (S504).

  The input slave interface 21 includes a signal indicating that data reception is possible, and asserts a data reception enable signal when there is a free space in the storage area of the FIFO_B 20. The output master interface 63 of the compressor / decompressor 60 maintains the currently transmitted data, i.e., does not perform transmission of the next data until the receivable signal of the input slave interface 21 is asserted.

  The output slave interface 22 includes a signal indicating that data transmission is possible, and asserts a data transmission enable signal when data is stored in the FIFO_B 20. The input master interface 52 of the encryption / decryption device 50 waits for data acquisition until the transmission enable signal of the output slave interface 22 is asserted. The encryption / decryption device 50 accesses the output slave interface 22 of the FIFO_B 20 by using the input master interface 52, and reads the compressed data stored in the FIFO_B 20 (S505).

  After the read data is encrypted in the encryption / decryption processing unit 56 (S506), the encrypted data is transmitted to the input slave interface 11 of the FIFO_A 10 using the output master interface 53 (S507).

  The FIFO_A 10 receives the encrypted data at the input slave interface 11 and stores it in the FIFO_A 10 (S508).

  The input slave interface 11 includes a signal indicating that data reception is possible, and asserts a data reception ready signal when there is a free space in the storage area of the FIFO_A 10. The output master interface 53 of the encryption / decryption device 50 maintains the currently transmitted data, that is, does not perform transmission of the next data until the receivable signal of the input slave interface 11 is asserted.

  The output slave interface 12 includes a signal indicating that data transmission is possible, and asserts a data transmission enable signal when data is stored in the FIFO_A 10. The input / output master interface 42 of the SATA control unit 40 waits for data acquisition until the transmission enable signal of the output slave interface 12 is asserted.

  The SATA control unit 40 uses the input / output master interface 42 to access the output slave interface 12 of the FIFO_A 10, reads the encrypted data stored in the FIFO_A 10 (S 509), and transmits it to the HDD 103 (S 510). .

  In the above, read processing, compression processing, encryption processing, and write processing to the HDD 103 of the data from the memory 30 are performed in parallel at the same time. FIG. 5 shows the simultaneous parallel processing. At a certain timing, the data transfer from the compressor / decompressor 60 to the FIFO_B 20, the data transfer from the encryption / decryptor 50 to the FIFO_A 10, and the write operation to the HDD 103 are executed simultaneously. Is shown by a solid line

  As described above, by using the FIFO_A10 and the FIFO_B20, data transfer from the compression / decompression device 60 to the encryption / decryption device 50 (S502 to S506) and data transfer from the encryption / decryption device 50 to the SATA control unit 40 ( Since S507 to S509) can be executed in parallel, data transfer can be executed at a higher speed than when the memory 30 is shared.

  Next, with reference to FIG. 6, an example of data transfer operation in the case where data stored in the HDD 103 is decrypted and expanded and then written to the memory 30 will be described. FIG. 6 is a diagram illustrating processing operations in time series when decoding, decompressing, and writing to a memory. A solid line indicates a state in which processing is simultaneously performed at a certain timing, and a dotted line indicates the timing. The processing performed before is shown.

  The SATA control unit 40 transmits the data read from the HDD 103 (S601) to the input slave interface 11 of the FIFO_A 10 using the input / output master interface 42 (S602).

  The FIFO_A 10 receives the data read from the HDD at the input slave interface 11 and stores it in the FIFO_A 10 (S603).

  The input slave interface 11 includes a signal indicating that data reception is possible, and asserts a data reception ready signal when there is a free space in the storage area of the FIFO_A 10. The input / output master interface 42 of the SATA control unit 40 maintains the currently transmitted data until the receivable signal of the input slave interface 11 is asserted. (Do not send the next data)

  The output slave interface 12 includes a signal indicating that data transmission is possible, and asserts a data transmission enable signal when data is stored in the FIFO_A 10. The input master interface 52 of the encryption / decryption device 50 waits for data acquisition until the transmission enable signal of the output slave interface 12 is asserted.

  The encryption / decryption device 50 uses the input master interface 52 to access the output slave interface 12 of the FIFO_A 10 and reads the HDD data stored in the FIFO_A 10 (S604).

  After the read / decryption processing unit 56 decrypts the read data (S605), the decrypted data is transmitted to the input slave interface 21 of the FIFO_B 20 using the output master interface 53 (S606).

  The FIFO_B 20 receives the decrypted data by the input slave interface 21 and stores it in the FIFO_B 20 (S607).

  The input slave interface 21 includes a signal indicating that data reception is possible, and asserts a data reception enable signal when there is a free space in the storage area of the FIFO_B 20. The output master interface 53 of the encryption / decryption device 50 maintains the currently transmitted data until the receivable signal of the input slave interface 21 is asserted.

  The output slave interface 22 includes a signal indicating that data transmission is possible, and asserts a data transmission enable signal when data is stored in the FIFO_B 20. The input master interface 62 of the compressor / decompressor 60 waits for data acquisition until the transmission enable signal of the output slave interface 22 is asserted.

  The compressor / decompressor 60 accesses the output slave interface 22 of the FIFO_B 20 using the input master interface 62, and reads the decoded data stored in the FIFO_B 20 (S608).

  The compression / decompression processing unit 66 decompresses the read data (S609), and then uses the output master interface 63 to transmit the decompressed data to the input / output slave interface 31 of the memory 30 and writes to the memory 30. Execute (S610).

  In the above, read processing from the HDD 103, decompression processing, decryption processing, and write processing to the memory 30 are performed simultaneously in parallel. FIG. 6 shows reading from the HDD 103 to the SATA control unit 40 at a certain timing, data transfer from the FIFO_A 10 to the encryption / decryption device 50, and data transfer from the FIFO_B 20 to the compression / decompression device 60 in order to represent the simultaneous parallel processing. Are indicated by a solid line.

  As described above, by using FIFO_A10 and FIFO_B20, data transfer from the SATA control unit 40 to the encryption / decryption device 50 (S602 to S605) and data transfer from the encryption / decryption device 50 to the compression / decompression device 60 ( S606 to S609) can be executed in parallel, so that data transfer can be executed at a higher speed than when the memory 30 is shared.

1 Data processing device 10 FIFO_A
11, 21 Input slave interface 12, 22 Output slave interface 20 FIFO_B
30 Memory 31, 41, 51, 61, 71, 81 Input / output slave interface 40 SATA control unit 42, 81 Input / output master interface 44 Transmission / reception DMAC
46 SATA host controller 50 Encryption / decryption device 52, 62, 72 Input master interface 53, 63, 73 Output master interface 54, 64 Reception DMAC
55, 65 DMAC for transmission
56 Encryption / Decryption Processing Unit 60 Compression / Expansion Unit 66 Compression / Expansion Processing Unit 70 General Purpose DMAC
80 CPU
90 flash ROM
103 HDD
101 High-speed bus 102 Low-speed bus

JP 2003-337805 A

Claims (5)

A bus for data transfer;
A plurality of functional modules connected to the bus;
A plurality of temporary storage devices connected to the bus and reading the data in order from the previously written data,
Each of the plurality of functional modules and the plurality of temporary storage devices includes a bus connection interface for connection to the bus, and the bus connection interface included in each of the plurality of temporary storage devices includes the bus connection interface. An input interface for receiving input of data to the temporary storage device and an output interface for outputting data from the temporary storage device to the bus are included,
The bus connection interface, the input interface, and the output interface are each assigned a bus address that can be uniquely identified,
Data transfer between one of the plurality of functional modules and one of the plurality of temporary storage devices, and data transfer between the other of the plurality of functional modules and the other of the plurality of temporary storage devices can be executed simultaneously. Formed into,
A data processing apparatus. The storage capacity of at least one of the plurality of temporary storage devices is 2 of the burst transfer size of one time of the functional module having the maximum data size to be transferred in one burst transfer of the plurality of functional modules. Double,
The data processing apparatus according to claim 1. The storage capacity of at least one of the plurality of temporary storage devices is twice the burst transfer size of one time of the function module having the highest data transfer frequency using the temporary storage device among the plurality of function modules. Is,
The data processing apparatus according to claim 1. The storage capacity of at least one of the plurality of temporary storage devices is twice the data bus width of the input interface and the output interface.
The data processing apparatus according to claim 1, wherein the data processing apparatus is a data processing apparatus. A bus for data transfer;
A plurality of functional modules connected to the bus;
In a data processing device comprising a plurality of temporary storage devices connected to the bus and reading the data in order from the previously written data,
Each of the plurality of functional modules and the plurality of temporary storage devices includes a bus connection interface for connection to the bus, and the bus connection interface included in each of the plurality of temporary storage devices includes the bus connection interface. An input interface for receiving input of data to the temporary storage device and an output interface for outputting data from the temporary storage device to the bus are included,
The bus connection interface, the input interface, and the output interface are each assigned a bus address that can be uniquely identified,
Simultaneously transferring data between one of the plurality of functional modules and one of the plurality of temporary storage devices, and transferring data between the other of the plurality of functional modules and the other of the plurality of temporary storage devices. ,
A data transfer method characterized by the above.