JP2010152604A - Information processor, and image data recording system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor capable of quickening DMA transfer to an I/O buffer, and an image data recording system. <P>SOLUTION: This information processor 1 includes an internal bus 40, a DMA controller 20 for transferring a data from a transferring side resource to a transferred side resource, and an I/O controller 30 including an FIFO 320 (I/O buffer), and for transferring a data between the FIFO 320 and an external device 100. The DMA controller selects either of continuous reading-out of a plurality of data from the FIFO 320, or reading-out of one piece of data therefrom, in one data transfer request from the I/O controller, when the transferring side resource is the I/O controller, and selects either of continuous writing-in of a plurality of data into the FIFO 320, or writing-in of one piece of data thereinto, in the one data transfer request from the I/O controller, when the transferred side resource is the I/O controller. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, an image data recording system, and the like.

  When image data during driving of a car is recorded in a primary storage device such as SDRAM at regular time intervals, and an event such as an accident occurs, image data for a predetermined time before and after the event is stored in a primary storage device such as SDRAM. Drive recorders that transfer data to a secondary storage device such as a CF memory card or an SD memory card. If a drive recorder is used, it is possible to grasp the situation when an event such as an accident occurs by analyzing the image data recorded in the secondary storage device.

Since the drive recorder is required to reliably record image data when an event such as an accident occurs in the secondary storage device, the information processing device used for the drive recorder is changed from the primary storage device to the secondary storage device. The image data is transferred at a high speed by DMA transfer without using a CPU.
JP 2008-2405070 A

  When a CF memory card or an SD memory card is used as a secondary storage device, an I / O buffer is used because burst writing cannot be performed on these memory cards. That is, in the information processing apparatus, image data is DMA-transferred from the primary storage device to the I / O buffer by the DMA controller, and image data stored in the I / O buffer is transferred to the secondary storage device by the I / O controller. The Here, because the transfer timing from the primary storage device to the I / O buffer and the transfer timing to the secondary storage device are different, conventionally, DMA transfer is performed by handshake for each data between the DMA controller and the I / O controller. Had gone. Therefore, there is an overhead due to handshaking for each data, and there is a case where speeding up by DMA transfer cannot be sufficiently achieved.

  The present invention has been made in view of the above problems, and according to some aspects of the present invention, an information processing apparatus and image data capable of speeding up DMA transfer to an I / O buffer. A recording system can be provided.

  (1) The present invention reads the data from the transfer source resource via the internal bus and the internal bus, and writes the read data to the transfer destination resource via the internal bus. A DMA transfer control unit that performs data transfer to a transfer destination resource, an I / O buffer that includes data transfer between the I / O buffer and an external device, the transfer source resource, and the transfer A transfer information setting unit that sets information for specifying a destination resource and information for specifying a size of data to be transferred from the transfer source resource to the transfer destination resource, and the DMA transfer control unit includes: When the transfer source resource is the I / O control unit, a single data transfer request from the I / O control unit is duplicated from the I / O buffer. If the data of the transfer destination is the I / O control unit, a response to a single data transfer request from the I / O control unit is selected. Thus, the information processing apparatus selects whether to write a plurality of data continuously or to write one data in the I / O buffer.

  The external device is, for example, an SD (Secure Digital) memory card, a CF (Compact Flash) memory card, a USB (Universal Serial Bus) device, or a PC (Personal Computer).

  The transfer information setting unit is, for example, a CPU (Central Processing Unit).

  According to the information processing apparatus of the present invention, in response to a single data transfer request from the I / O control unit, the DMA transfer control unit continuously transfers a plurality of data to the I / O buffer via the internal bus. By performing the above, it is possible to speed up the DMA transfer to the I / O buffer.

  Further, according to the information processing apparatus of the present invention, even when continuous transfer is difficult for one data transfer request from the I / O control unit, one data transfer request is performed by DMA transfer without using the CPU. Since one data can be transferred every time, the load on the CPU can be reduced.

  As described above, according to the information processing apparatus of the present invention, it is determined whether a plurality of data is continuously transferred or one data is transferred in response to one data transfer request, the type of external device or the I / O buffer. The DMA transfer rate for the I / O buffer can be optimized by appropriately selecting according to the size and the like.

  (2) In the information processing apparatus of the present invention, the transfer information setting unit sets information for specifying the number of data that the DMA transfer control unit continuously reads or writes to the I / O buffer. It may be.

  According to the information processing apparatus of the present invention, the data size of continuous transfer to the I / O buffer can be variably set, so that the DMA transfer rate for the I / O buffer can be further optimized.

  (3) In the information processing apparatus according to the present invention, when the DMA transfer control unit continuously reads or writes the plurality of data with respect to the I / O buffer, the DMA transfer control unit starts reading or writing. It may be selected whether to occupy the bus right of the internal bus until the end.

  According to the information processing apparatus of the present invention, the internal bus can be occupied when the priority of continuous transfer to the I / O buffer is high, and the internal bus can be prevented from being occupied when the priority is low. The bus can be used efficiently.

  (4) In the information processing apparatus of the present invention, the transfer information setting unit sets a transfer mode of data transfer from the transfer source resource to the transfer destination resource, and the DMA transfer control unit is based on the transfer mode. In response to one data transfer request, it is selected whether to read or write the plurality of pieces of data to the I / O buffer continuously or to read or write one piece of data. May be.

  (5) In the information processing apparatus according to the present invention, when the I / O control unit becomes the transfer destination resource, the size of the free area of the I / O buffer and the I / O buffer written continuously Compare the size of multiple data, and if it becomes the source resource, compare the size of the data stored in the I / O buffer and the size of the multiple data read from the I / O buffer continuously Then, a continuous transfer request signal or a unit transfer request signal is sent to the DMA transfer control unit based on the comparison result, and when the DMA transfer control unit receives the continuous transfer request signal, the I / O buffer When the unit transfer request signal is received, the plurality of data is continuously read or written to the I / O buffer. It may be or be written.

  According to the information processing apparatus of the present invention, the I / O control unit determines whether continuous transfer to the I / O buffer is possible based on the state of the I / O buffer. Transfer can be performed more efficiently.

  (6) In the information processing apparatus according to the present invention, the I / O control unit may determine that the size of data that the DMA transfer control unit continuously reads or writes from the I / O buffer is the data transfer target. If the data size is smaller than the data size, the data transfer request may be made to the DMA transfer control unit in a plurality of times.

  (7) The information processing apparatus according to the present invention includes the first I / O control unit including the first I / O buffer and the second I / O control including the second I / O buffer. The DMA transfer control unit is configured such that the transfer source resource is the first I / O control unit and the transfer destination resource is the second I / O control unit. In response to a single data transfer request from the first I / O control unit, a selection is made as to whether to read a plurality of data from the first I / O buffer or to read one data. In response to a single data transfer request from the second I / O control unit, it is selected whether to write a plurality of data continuously or to write one data in the second I / O buffer. May be.

  According to the information processing apparatus of the present invention, DMA transfer can be performed between two I / O buffers. Further, according to the information processing apparatus of the present invention, in DMA transfer between I / O buffers, it is selected whether to transfer a plurality of data continuously or to transfer one data in response to a single data transfer request. The DMA transfer rate can be optimized.

  (8) The present invention provides any one of the information processing apparatuses described above, at least one camera module, a first storage device that temporarily stores a plurality of image data captured by the camera module at a predetermined interval, A non-volatile second storage device that performs data transfer with the I / O buffer of the I / O control unit of the information processing device, the information processing device based on occurrence of a predetermined event, The DMA transfer control unit transfers the image data stored in the first storage device to the I / O buffer, and the I / O control unit transfers the image data transferred to the I / O buffer. An image data recording system for transferring to the second storage device.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Information processing apparatus 1-1. First Embodiment [Configuration of Information Processing Apparatus]
FIG. 1 is a diagram for explaining the configuration of the information processing apparatus according to the first embodiment.

  The information processing apparatus 1 according to the first embodiment includes a CPU 10, an internal memory 12, an external memory controller 14, a DMA (Direct Memory Access) controller 20, an I / O controller 30, and an internal bus 40 to which these are connected. ing.

  The CPU 10 performs various information processing such as data processing and interrupt processing using both or one of the internal memory 12 and the external memory 110 as a work area.

  The external memory controller 14 is connected to an external memory 110 such as an SRAM (Static Random Access Memory) or an SDRAM (Synchronous Dynamic Random Access Memory), and controls access to the external memory 110.

  The I / O controller 30 is connected to an external device 100 such as an SD memory card, a CF memory card, a USB device, or a PC, and controls access to the external device 100.

  The DMA controller 20 controls data transfer between any two resources of the internal memory 12, the external memory 110, and the I / O controller 30 via the internal bus 40. Specifically, the DMA controller 20 reads the data to be transferred from the transfer source resource via the internal bus 40 and writes the read transfer target data to the transfer destination resource via the internal bus 40 to perform the DMA transfer. To realize. That is, the DMA controller 20 functions as a bus master, and the internal memory 12, the external memory 110, and the I / O controller 30 function as bus slaves. Since the DMA controller 20 can perform data transfer processing between these resources without intervention of the CPU 10, the load on the CPU can be greatly reduced.

  The internal bus 40 has, for example, 32-bit read data (HRDATA [31: 0]) and write data (HWDATA [31: 0]), 32-bit address signal (HADDR [31: 0]), and 1-bit write. The bus arbiter is composed of a signal (HWRITE), a 1-bit bus request signal (HBUSREQ), a 1-bit bus grant signal (HGRANT), and the like. As such an internal bus, for example, AHB (Advanced High-performance Bus) is known.

  The DMA controller 20 and the I / O controller 30 function as a DMA transfer control unit and an I / O control unit in the present invention, respectively.

[DMA controller]
FIG. 2 is a diagram for explaining the configuration of the DMA controller according to the first embodiment.

  The DMA controller 20 includes a register unit 200, a control unit 210, a FIFO (First In First Out) 220, and a bus master interface unit 230.

  The register unit 200 includes various setting registers for controlling DMA transfer, such as a transfer source address register 202, a transfer destination address register 204, a transfer size counter 206, and a control register 208, which are set by the CPU 10. . That is, the CPU 10 functions as a transfer information setting unit in the present invention.

  In the transfer source address register 202 and the transfer destination address register 204, a read start address of a transfer source resource and a write start address of a transfer destination resource that are targets of DMA transfer are set, respectively. The transfer size counter 206 is set with the size of data to be subjected to DMA transfer.

  Depending on the set value of the control register 208, it is possible to select a transfer source resource or transfer destination resource, select a unit size of transfer source data or transfer destination data, select transfer prohibition or transfer permission, and the like. . When transfer permission is selected, the DMA enable signal 212 becomes active.

  When the transfer source resource or transfer destination resource is the I / O controller 30, the transfer mode from the I / O controller 30 to the DMA controller 20 (hereinafter referred to as “I / O read transfer”) is set according to the set value of the control register 208. Mode) and a transfer mode from the DMA controller 20 to the I / O controller 30 (hereinafter referred to as “I / O write transfer mode”). For example, as an I / O read transfer mode or I / O write transfer mode, a unit size data transfer mode (hereinafter referred to as “single transfer mode”) in response to a single transfer request from the I / O controller 30. ) Or a mode in which a plurality of unit-size data are continuously transferred (hereinafter referred to as “continuous transfer mode”) can be selected. Furthermore, in order to change the number of data continuously transferred in the continuous transfer mode, for example, a register for setting a data size for continuous transfer (hereinafter referred to as “continuous transfer size”) may be provided.

  When the DMA enable signal 212 becomes active, the controller 210 starts DMA transfer control based on the set values of the transfer source address register 202, transfer destination address register 204, transfer size counter 206, control register 208, and the like.

  First, the control unit 210 sends a bus request signal 45 to the internal bus 40 via the bus master interface unit 230 in order to read transfer target data from the transfer source resource via the internal bus 40. The bus arbiter of the internal bus 40 sends a bus authorization signal 46 to the DMA controller 20 if the internal bus 40 is unused, and if another bus master such as the CPU 10 is using the internal bus 40. After waiting until the internal bus 40 is released, a bus authorization signal 46 is sent to the DMA controller 20. Then, the control unit 210 acquires the bus right by receiving the bus authorization signal 46 via the bus master interface unit 230, and starts the process of reading the transfer target data from the transfer source resource.

  Next, the control unit 210 sets the address set in the transfer source address register 202 to the address signal 43, sets the write signal 44 in the reading direction, and sends it to the internal bus 40 via the bus master interface unit 230. . Read data 42 is read from the address set in the address signal 43 to the internal bus 40, and the control unit 210 writes the read data 42 into the FIFO 220 via the bus master interface unit 230.

  Each time the controller 210 writes the read data 42 to the FIFO 220, the controller 210 decrements the transfer size counter 206 by the unit size selected by the control register 208, and sets the address signal 43 to the next address. Then, the control unit 210 repeats the process of writing the read data 42 into the FIFO 220 until the value of the transfer size counter 206 becomes zero.

  Here, when the transfer source resource is the internal memory 12 or the external memory 110, since the transfer target data always exists in the internal memory 12 or the external memory 110, the control unit 210 reads the read data immediately after acquiring the bus right. 42 reading can be started.

  On the other hand, when the transfer source resource is the I / O controller 30, the control unit 210 obtains the bus right, and if the transfer target data is not transferred from the external device 100 to the I / O controller 30, the read data 42 reading cannot be started. Therefore, the I / O controller 30 sends the DMA request signal 32 to the DMA controller 20 after receiving the transfer target data from the external device 100, and the control unit 210 performs the read processing until the DMA request signal 32 is received. Do not start. When the control unit 210 receives the DMA request signal 32, the control unit 210 transmits a DMA acknowledge signal 22 to the I / O controller 30 and starts a reading process.

  If the I / O read transfer mode is set to the single transfer mode, the control unit 210 reads one read data 42 and receives the FIFO 220 every time the DMA request signal 32 is received until reading of the transfer target data is completed. And the process of sending the DMA acknowledge signal 22 to the I / O controller 30 is repeated.

  If the I / O read transfer mode is set to the continuous transfer mode, the control unit 210 receives the read data 42 corresponding to the continuous transfer size every time the DMA request signal 32 is received until reading of the transfer target data is completed. The process of continuously reading and writing to the FIFO 220 and sending the DMA acknowledge signal 22 to the I / O controller 30 is repeated.

  Next, the control unit 210 sends a bus request signal 45 to the internal bus 40 via the bus master interface unit 230 in order to write data to be transferred to the transfer destination resource via the internal bus 40. The control unit 210 acquires the bus right by receiving the bus authorization signal 46 via the bus master interface unit 230, and starts the process of writing the transfer target data to the transfer destination resource.

  Next, the control unit 210 reads the data stored in the FIFO 220 and sets it in the write data 41, sets the address set in the transfer destination address register 204 in the address signal 43, and sets the write signal 44 in the writing direction. It is set and sent to the internal bus 40 via the bus master interface unit 230. Then, the transfer destination resource writes the data set in the write data 41 to the address set in the address signal 43.

  The controller 210 reads data from the FIFO 220 and sets it in the write data 41 until the FIFO 220 becomes empty, and repeats the process of setting the address where the write data 41 is to be written in the address signal 43.

  Here, when the transfer destination resource is the internal memory 12 or the external memory 110, since the area for writing the transfer target data is secured in the internal memory 12 or the external memory 110, the control unit 210 acquires the bus right. The writing of the write data 41 can be started immediately.

  On the other hand, when the transfer destination resource is the I / O controller 30, the control unit 210 acquires the bus right, but if the area for writing the transfer target data is not secured in the I / O controller 30, the write data 41 Cannot start writing. Therefore, the I / O controller 30 sends the DMA request signal 32 to the DMA controller 20 only when the area to which the transfer target data is written is empty, and the control unit 210 writes until the DMA request signal 32 is received. Do not start processing. When the control unit 210 receives the DMA request signal 32, it sends a DMA acknowledge signal 22 to the I / O controller 30 and starts a writing process.

  If the I / O write transfer mode is set to the single transfer mode, the controller 210 reads one data from the FIFO 220 and writes it every time it receives the DMA request signal 32 until writing of the transfer target data is completed. The process of setting the data 41 and sending the DMA acknowledge signal 22 to the I / O controller 30 is repeated.

  If the I / O write transfer mode is set to the continuous transfer mode, the control unit 210 receives data for the continuous transfer size from the FIFO 220 every time it receives the DMA request signal 32 until the writing of the transfer target data is completed. The process of continuously reading and setting the write data 41 and sending the DMA acknowledge signal 22 to the I / O controller 30 is repeated.

  Note that the control unit 210 may continuously send out the bus request signal 45 from the start of the read process (or write process) of the transfer target data until it is completed, and occupy the bus right of the internal bus 40. The bus request signal 45 is transmitted at the start of reading (or writing) of each write data 41, and the transmission of the bus request signal 45 is stopped at the end of reading (or writing), thereby reading (or writing) each write data 41. You may make it acquire a bus right every time.

  For example, the control unit 210 determines whether to occupy the bus right according to the setting (single transfer mode or continuous transfer mode) of the I / O read transfer mode (or I / O write transfer mode). Alternatively, in the read process (or write process), a selection bit for determining whether to occupy the bus right is provided in the control register 208, and it is determined whether to occupy the bus right according to the set value of the selection bit. You may do it.

[I / O controller]
FIG. 3 is a diagram for explaining the configuration of the I / O controller according to the first embodiment.

  The I / O controller 30 includes a register unit 300, a DMA control unit 310, a FIFO 320, a bus slave interface unit 330, and an I / O interface unit 340.

  The register unit 300 includes a DMA control register 302 for controlling DMA transfer, an I / O control register 304 for controlling data transfer to the external device 100, and the like, which are set by the CPU 10.

  The I / O interface unit 340 performs data transfer with the external device 100 in a data transfer format corresponding to the type of the I / O 100 according to the set value of the I / O control register 304. That is, the I / O interface unit 340 stores the data received from the external device 100 in the FIFO 320 or performs processing for sending the data stored in the FIFO 320 to the external device 100. The FIFO 320 can be configured using a predetermined area of RAM (Random Access Memory) or a shift register, for example, and functions as an I / O buffer in the present invention.

  The I / O interface unit 340 can be realized by a known interface circuit according to the type of the external device 100 (SD memory card, CF memory card, USB device, PC, etc.).

  The DMA transfer mode can be selected (single transfer mode or continuous transfer mode) according to the set value of the DMA control register 302, and the control unit 310 can recognize the DMA transfer mode by the transfer mode signal 312. it can.

  The setting value of the DMA control register 302 can specify the size of the empty area of the FIFO 320 that is a condition for starting DMA transfer and the threshold value of the data size stored in the FIFO 320. The CPU 10 sets this threshold value corresponding to the data size to be transferred.

  Further, the DMA control register 302 is provided with a bit for instructing the start of DMA transfer. When the CPU 10 instructs to start DMA transfer, the DMA control unit 310 sends an address signal via the bus slave interface unit 330. 43 and confirms whether the address signal 43 is the address of the FIFO 320 (if there are a plurality of FIFOs 320, which FIFO address is specified). The DMA control unit 310 receives the write signal 44 via the bus slave interface unit 330 and determines whether the I / O controller 30 is a transfer source resource or a transfer destination resource.

  When the I / O controller 30 becomes a transfer source resource, the DMA control unit 310 determines whether or not the data size stored in the FIFO 320 is equal to or larger than the threshold value. If it is smaller, the DMA request signal 32 is sent to the DMA controller 20 after waiting until the threshold is exceeded.

  As described above, when the DMA controller 20 receives the DMA request signal 32, it sends the DMA acknowledge signal 22. Therefore, when the DMA controller 310 receives the DMA acknowledge signal 22, the DMA controller 310 reads and reads the data stored in the FIFO 320. Data 42 is set and sent to the internal bus 40 via the bus slave interface unit 330.

  If the DMA transfer mode is set to the single transfer mode, the control unit 310 first transmits a DMA request signal and then receives one data (unit size data) from the FIFO 320 every time the DMA acknowledge signal 22 is received. The process of reading and setting to the read data 42 and sending the next DMA request signal 32 to the DMA controller 20 is repeated.

  If the DMA transfer mode is set to the continuous transfer mode, the control unit 310 first transmits the DMA request signal 32, and then continuously reads data for the continuous transfer size (unit size data) from the FIFO 320. Processing to set the read data 42 is performed.

  On the other hand, when the I / O controller 30 becomes a transfer destination resource, the DMA control unit 310 determines whether the size of the free area of the FIFO 320 is equal to or larger than the threshold value. If it is smaller, the DMA request signal 32 is sent to the DMA controller 20 after waiting until the threshold is exceeded.

  As described above, when the DMA controller 20 receives the DMA request signal 32, it sends the DMA acknowledge signal 22 together with the write data 41. Therefore, when the DMA controller 310 receives the DMA acknowledge signal 22, the DMA controller 310 passes through the bus slave interface unit 330. Write data 41 to the FIFO 320.

  If the DMA transfer mode is set to the single transfer mode, the control unit 310 writes one write data 41 (unit size data) to the FIFO 320 and receives data from the DMA controller 20 every time the DMA acknowledge signal 22 is received. The process of sending the next DMA request signal 32 is repeated.

  If the DMA transfer mode is set to the continuous transfer mode, the control unit 310 continuously receives the write data 41 (unit size data) corresponding to the continuous transfer size together with the DMA acknowledge signal 22 and writes the write data 41 into the FIFO 320. .

[Timing chart]
4 to 9 show examples of timing charts for data transfer in the information processing apparatus according to the first embodiment.

4 to 6 are timing charts when the transfer source resource and the transfer destination resource are the external memory 110 and the I / O controller 30, respectively, and 32 bytes (32 bits (4 bytes) × 8) of data are transferred. Yes (the transfer source resource may be the internal memory 12). 4 to 6, before the time T ₀ , the address RA 0 of the external memory 110 in which the first data to be transferred is stored is set in the transfer source address register 202. The transfer destination address register 204 is set with the address WA0 of the FIFO 320 of the I / O controller 30. The transfer size counter 206 is set with 32 bytes, which is the data size to be transferred. The unit size is 32 bits (4 bytes).

  FIG. 4 is a diagram illustrating an example of a timing chart when the DMA controller 20 transfers unit size data in response to a single transfer request from the I / O controller 30. That is, the I / O write transfer mode is set to the single transfer mode in the control register 208 of the DMA controller 20. Also, the DMA transfer mode is set to the single transfer mode in the DMA control register 302 of the I / O controller 30. Hereinafter, the timing chart of FIG. 4 will be described.

When the DMA enable signal 212 (DE) becomes active when the CPU 10 changes the setting of the control register 208 from the transfer prohibition to the transfer permission at the time T ₀ , the DMA controller 20 follows the setting values of the registers of the register unit 200. Data transfer processing from the external memory 110 to the FIFO 320 of the I / O controller 30 is started.

At time _{T 1,} DMA controller 20 sends a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter), the internal bus 40 from the internal bus 40 if unused state (bus arbiter) The bus authorization signal 46 (HGRANT) is received to acquire the bus right, and reading of the transfer target data from the external memory 110 is started.

At times T _{1 to} T ₃ , the DMA controller 20 occupies the bus right by continuously sending the bus request signal 45 (HBUSREQ) to burst-read the transfer target data from the external memory.

Since the transfer source address register 202 addresses RA0 external memory 110 the first data to be transferred is stored is set, DMA controller 20 at time _T 1 through T _4, is incremented from address RA0 sequentially The addresses RA0 to RA7 are sent to the internal bus 40 as the address signal 43 (HADDR [31: 0]).

Outside the memory 110 of the address RA0~RA7 are stored is 32 bytes (32 bits (4 bytes) × 8) of data D0~D7 to be transferred, at time _T 2 through T _4, data D0~D7 is The read data 42 (HRDATA [31: 0]) is read to the internal bus 40 via the external memory controller 14, and the DMA controller 20 stores the data D0 to D7 in the FIFO 220 in order.

At time T ₄ , the I / O controller 30 sends the DMA request signal 32 (DREQ) to the DMA controller 20 because the size of the empty area of the FIFO 320 becomes equal to or larger than the threshold (for example, 32 bytes) set in the DMA control register 302. ).

DMA controller 20 receives a DMA request signal 32 (DREQ), to transfer the first data D0 stored in FIFO320 in FIFO320 the I / O controller 30, at time _T 5 through T _6, an internal bus 40 ( A bus request signal 45 (HBUSREQ) is sent to the bus arbiter.

  Since the address WA0 of the FIFO 320 is set in the transfer destination address register 204, the DMA controller 20 sends the address WA0 to the internal bus 40 as the address signal 43 (HADDR [31: 0]).

When the DMA controller 20 receives the bus authorization signal 46 (HGRANT) from the internal bus 40 (bus arbiter) at time T _{5 to} T ₆ and acquires the bus right, the write signal 44 (HWRITE) is obtained at time T _{6 to} T ₇ . ) In the writing direction (high level) and sent to the internal bus 40.

The I / O controller 30 recognizes that the write signal 44 (HWRITE) is in the writing direction (high level) at time T _{5 to} T ₆ and prepares for writing to the FIFO 320.

At times T _{7 to} T ₈ , the DMA controller 20 sends a DMA acknowledge signal 22 (DACK) to the I / O controller 30 and reads the data D0 from the FIFO 220 as write data 41 (HWDATA [31: 0]). The data is sent to the internal bus 40, and the I / O controller 30 stores the data D 0 in the FIFO 320.

Since the DMA transfer mode is set to single transfer mode in the DMA control register 302, I / O controller 30, at time _{T 8,} and sends the next DMA request signal 32 (DREQ) to the DMA controller 20.

Upon receiving the DMA request signal 32 (DREQ), the DMA controller 20 sends a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter) at times T _{9 to} T ₁₀ , and the internal bus 40 (bus The bus grant signal 46 (HGRANT) is received from the arbiter), the bus right is acquired, and the process of transferring the next data D1 stored in the FIFO 220 to the FIFO 320 of the I / O controller 30 is started.

From time T _{10 to} T ₁₁ , the DMA controller 20 sends the write signal 44 (HWRITE) to the internal bus 40 in the writing direction (high level).

At times T _{11 to} T ₁₂ , the DMA controller 20 sends a DMA acknowledge signal 22 (DACK) to the I / O controller 30 and reads the data D1 from the FIFO 220 as write data 41 (HWDATA [31: 0]). The data is sent to the internal bus 40, and the I / O controller 30 stores the data D1 in the FIFO 320.

Similarly, at times T _{12 to} T ₁₃ , data D 2 to D 7 are transferred from the FIFO 220 of the DMA controller 20 to the FIFO 320 of the I / O controller 30.

At times T _{13 to} T ₁₄ , the DMA controller 20 generates a DMA end interrupt signal 24 (DMAINT), and the CPU 10 can recognize that the transfer process has ended. Moreover, the transfer processing is completed, setting of the control register 208 is automatically changed to a transfer prohibited from transfer permission, at time _{T 14,} DMA enable signal 212 (DE) is DMA controller 20 deactivates stops.

  As described above, in the case of FIG. 4, since the I / O write transfer mode is set to the single transfer mode in the control register 208, the DMA controller 20 transfers the DMA acknowledge signal every time data of D0 to D7 is transferred. 22 (DACK) is sent to the I / O controller 30, and the I / O controller 30 sends the next DMA request signal 32 (DREQ) to the DMA controller 20 every time the DMA acknowledge signal 22 (DACK) is received. . That is, since the DMA controller 20 and the I / O controller 30 perform handshake processing for every 32 bits (4 bytes) of data transfer, it takes time to transfer data of 32 bytes.

  FIG. 5 shows an example of a timing chart when the DMA controller 20 continuously transfers a plurality of unit size data without occupying the bus right in response to a single transfer request from the I / O controller 30. FIG. That is, the I / O write transfer mode is set to the continuous transfer mode in the control register 208 of the DMA controller 20. Further, the DMA transfer mode is set to the continuous transfer mode in the DMA control register 302 of the I / O controller 30. Hereinafter, the timing chart of FIG. 5 will be described.

The process of reading the transfer target data from the external memory 110 at times T _{0 to} T ₄ is the same as that in FIG.

At time T ₄ , the I / O controller 30 sends a DMA request signal 32 (DREQ) to the DMA controller 20. When the DMA controller 20 receives the DMA request signal 32 (DREQ), the head data stored in the FIFO 320 is transmitted. the D0 for transfer to FIFO320 the I / O controller 30, at time _T 5 through T _6, sends a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter).

Since the addresses are set WA0 of FIFO320 the transfer destination address register 204, DMA controller 20, the address signal 43 to the address WA0 (HADDR [31: 0] ) is sent to the internal bus 40 as at time _{T 5,} A write signal 44 (HWRITE) is sent to the internal bus 40 in the writing direction (high level).

At times T _{5 to} T ₆ , the DMA controller 20 receives the bus grant signal 46 (HGRANT) from the internal bus 40 (bus arbiter) and acquires the bus right, and the I / O controller 30 receives the write signal 44 (HWRITE). Is in the writing direction (high level), and prepares for writing to the FIFO 320.

At times T _{7 to} T ₈ , the DMA controller 20 reads the data D0 from the FIFO 220 and sends it as write data 41 (HWDATA [31: 0]) to the internal bus 40. The I / O controller 30 sends the data D0 to the FIFO 320. To store.

Since the DMA transfer mode is set to the continuous transfer mode in the DMA control register 302, the DMA controller 20 transfers the next data D1 stored in the FIFO 220 to the FIFO 320 of the I / O controller 30 at time T _7. in through T _8, it sends a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter).

At times T _{8 to} T ₉ , the DMA controller 20 receives the bus grant signal 46 (HGRANT) from the internal bus 40 (bus arbiter), acquires the bus right, and writes the next data D1 to the write data 41 (HWDATA [31: 0]. ] To the internal bus 40, and the I / O controller 30 stores the data D1 in the FIFO 320.

Similarly, at times T _{9 to} T ₁₀ , data D 2 to D 7 are transferred from the FIFO 220 of the DMA controller 20 to the FIFO 320 of the I / O controller 30.

The processing at times T _{11 to} T ₁₂ is the same as the processing at times T _{13 to} T ₁₄ in FIG.

In this way, in the case of FIG. 5, since the I / O write transfer mode is set to the continuous transfer mode in the control register 208 and the continuous transfer size is 32 bytes, the DMA controller 20 performs the time T _{4 to} T Upon receiving once DMA request signal 32 (DREQ) at _5, and transferred at time _T 7 _{through T 11} to 32 bytes of data D0~D7 continuously. In addition, since the DMA transfer mode is set to the continuous transfer mode in the DMA control register 302, the I / O controller 30 does not confirm the DMA acknowledge signal 22 (DACK), but the data of 32 bytes of D0 to D7. The FIFO 320 can be written in order. That is, the DMA controller 20 and the I / O controller 30 do not need to perform handshake processing for every 32 bits (4 bytes) of data transfer. Therefore, the time required to transfer 32 bytes of data compared to the case of FIG. Can be shortened.

  FIG. 6 shows an example of a timing chart when the DMA controller 20 occupies the bus right and transfers a plurality of unit size data continuously in response to a single transfer request from the I / O controller 30. FIG. That is, the I / O write transfer mode is set to the continuous transfer mode in the control register 208 of the DMA controller 20, and the DMA transfer mode is set to the continuous transfer mode in the DMA control register 302 of the I / O controller 30. Hereinafter, the timing chart of FIG. 6 will be described.

The process of reading the transfer target data from the external memory 110 at times T _{0 to} T ₄ is the same as that in FIG.

At time _{T 4,} I / O controller 30 sends a DMA request signal 32 (DREQ) to the DMA controller 20, DMA controller 20 receives a DMA request signal 32 (DREQ), at time _{T 5,} the internal bus 40 A bus request signal 45 (HBUSREQ) is sent to (bus arbiter).

DMA controller 20 at time _{T 5,} and get the bus from the internal bus 40 (bus arbiter) receives a bus grant signal 46 (HGRANT), at time _T 2 through T _7, the bus request signal 45 (HBUSREQ) Continue sending and occupy the bus right.

At times T _{6 to} T ₈ , the DMA controller 20 continuously reads the data D 0 to D 7 from the FIFO 220 and sends them to the internal bus 40 as write data 41 (HWDATA [31: 0]). Stores the data D0 to D7 in the FIFO 320.

Processing time _T 8 through T ₉ is omitted because it is same as the processing time _T 13 _{through T 14} in Figure 4.

  As described above, in the case of FIG. 6, the DMA controller 20 occupies the bus right and transfers the transfer target data for 32 bytes to the I / O controller 30 continuously. Can be shortened.

7 to 9 are timing charts in the case where the transfer source resource and the transfer destination resource are the I / O controller 30 and the external memory 110, respectively, and 32 bytes (32 bits (4 bytes) × 8) of data are transferred. (The transfer destination resource may be the internal memory 12). In Figure 7-9, the time _{T 0} previously, addresses RA0 of FIFO320 the I / O controller 30 is set in the transfer source address register 202. The transfer destination address register 204 is set with the address WA0 of the external memory 110 in which the first data to be transferred is stored. The transfer size counter 206 is set with 32 bytes, which is the data size to be transferred. The unit size is 32 bits (4 bytes).

  FIG. 7 is a diagram illustrating an example of a timing chart when the DMA controller 20 transfers unit size data in response to a single transfer request from the I / O controller 30. That is, the I / O read transfer mode is set to the single transfer mode in the control register 208 of the DMA controller 20. Also, the DMA transfer mode is set to the single transfer mode in the DMA control register 302 of the I / O controller 30. Hereinafter, the timing chart of FIG. 7 will be described.

When the DMA enable signal 212 (DE) becomes active when the CPU 10 changes the setting of the control register 208 from transfer prohibition to transfer permission at time T ₀ , the DMA controller 20 receives the DMA request signal 32 from the I / O controller 30. Wait until (DREQ) is received.

Since the data size stored in the FIFO 320 becomes equal to or larger than the threshold (for example, 32 bytes) set in the DMA control register 302 at the time T ₁ , the I / O controller 30 sends a DMA request signal 32 to the DMA controller 20. (DREQ) is sent out.

The DMA controller 20 receives the DMA request signal 32 (DREQ), and transmits a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter) at times T _{2 to} T ₃ .

  Since the address RA0 of the FIFO 320 is set in the transfer source address register 202, the DMA controller 20 sends the address RA0 to the internal bus 40 as the address signal 43 (HADDR [31: 0]).

If the internal bus 40 is in an unused state, the DMA controller 20 receives the bus grant signal 46 (HGRANT) from the internal bus 40 (bus arbiter) and acquires the bus right at times T _{2 to} T ₃ . The reading of the transfer target data from the FIFO 320 of the / O controller 30 is started.

When the DMA controller 20 sends a DMA acknowledge signal 22 (DACK) to the I / O controller 30 at times T _{4 to} T ₅ , the I / O controller 30 receives the DMA acknowledge signal 22 (DACK) and receives a write signal 44 (HWRITE). ) Is in the reading direction (high level), the first data D0 is read from the FIFO 320 and sent to the internal bus 40 as read data 42 (HRDATA [31: 0]), and the DMA controller 20 receives the data D0. Is stored in the FIFO 220.

Since the DMA transfer mode is set to single transfer mode in the DMA control register 302, I / O controller 30 at time _{T 5,} and sends the next DMA request signal 32 (DREQ) to the DMA controller 20.

Upon receiving the DMA request signal 32 (DREQ), the DMA controller 20 sends a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter) at times T _{6 to} T ₇ , and the internal bus 40 (bus The bus grant signal 46 (HGRANT) is received from the arbiter), the bus right is acquired, and the process of reading the next data D1 stored in the FIFO 320 into the FIFO 220 is started.

When the DMA controller 20 sends a DMA acknowledge signal 22 (DACK) to the I / O controller 30 at times T _{8 to} T ₉ , the I / O controller 30 receives the DMA acknowledge signal 22 (DACK) and receives the next data D 0 from the FIFO 320. Is read out as read data 42 (HRDATA [31: 0]) to the internal bus 40.

  The DMA controller 20 stores the data D1 in the FIFO 220.

Similarly, at times T _{9 to} T ₁₀ , data D 2 to D 7 are transferred from the FIFO 320 of the I / O controller 30 to the FIFO 220 of the DMA controller 20.

Since the transfer destination address register 204 are set address WA0 external memory 110, DMA controller 20, the address signal 43 to the address WA0 at time _{T 11 (HADDR [31: 0} ]) is sent to the internal bus 40 as At the same time, the write signal 44 (HWRITE) is sent to the internal bus 40 in the write direction (high level).

At time _{T 12,} DMA controller 20 sends a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter), the internal bus 40 from the internal bus 40 if unused state (bus arbiter) The bus authorization signal 46 (HGRANT) is received, the bus right is acquired, and writing of the transfer target data to the external memory 110 is started.

At times T _{12 to} T ₁₄ , the DMA controller 20 occupies the bus right by continuously sending the bus request signal 45 (HBUSREQ) to burst write the transfer target data to the external memory.

Since the transfer destination address register 204 address WA0 external memory 110 the first data to be transferred is stored is set, DMA controller 20 at time _T 12 _{through T 15,} while incrementing the address WA0 in order Addresses WA0 to WA7 are sent to the internal bus 40 as an address signal 43 (HADDR [31: 0]).

At times T _{13 to} T ₁₅ , the DMA controller 20 reads the data D0 to D7 from the FIFO 220 and sends them as write data 41 (HWDATA [31: 0]) 42 to the internal bus 40, and the data D0 to D7 are external memory controllers. 14 to the addresses WA0 to WA7 of the external memory.

At times T _{16 to} T ₁₇ , the DMA controller 20 generates a DMA end interrupt signal 24 (DMAINT), and the CPU 10 can recognize that the transfer process has ended. Moreover, the transfer processing is completed, setting of the control register 208 is automatically changed to a transfer prohibited from transfer permission, at time _{T 17,} DMA enable signal 212 (DE) is DMA controller 20 deactivates stops.

  In this way, in the case of FIG. 7, the I / O read transfer mode is set to the single transfer mode in the control register 208, so that the DMA controller 20 transfers the DMA acknowledge signal every time each data of D0 to D7 is transferred. 22 (DACK) is sent to the I / O controller 30, and the I / O controller 30 sends the next DMA request signal 32 (DREQ) to the DMA controller 20 every time the DMA acknowledge signal 22 (DACK) is received. . That is, since the DMA controller 20 and the I / O controller 30 perform handshake processing for every 32 bits (4 bytes) of data transfer, it takes time to transfer data of 32 bytes.

  FIG. 8 shows an example of a timing chart when the DMA controller 20 continuously transfers a plurality of unit size data without occupying the bus right in response to one transfer request from the I / O controller 30. FIG. That is, the I / O read transfer mode is set to the continuous transfer mode in the control register 208 of the DMA controller 20. Further, the DMA transfer mode is set to the continuous transfer mode in the DMA control register 302 of the I / O controller 30. Hereinafter, the timing chart of FIG. 8 will be described.

DMA enable signal 212 (DE) is activated at time _{T 0,} I / O controller 30 at time _{T 1} is sent to DMA request signal 32 (DREQ).

The DMA controller 20 receives the DMA request signal 32 (DREQ), sends a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter) at times T _{2 to} T ₃ , and the internal bus 40 (bus arbiter). ) From the FIFO 320 of the I / O controller 30 and starts reading data to be transferred.

At time _{T 4,} recognizes that I / O controller 30 write signal 44 (HWRITE) is a read direction (high level), the read data 42 reads the first data D0 from FIFO320 (HRDATA [31: 0] ) To the internal bus 40, and the DMA controller 20 stores the data D0 in the FIFO 220.

Since the DMA transfer mode is set to the continuous transfer mode in the DMA control register 302, the DMA controller 20 transfers the next data D1 stored in the FIFO 320 of the I / O controller 30 to the FIFO 220 at time T _5. in through T _6, it sends a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter).

At time _T 5 ~T _6, DMA controller 20 acquires the bus right to receive the internal bus 40 bus grant signal 46 from the (bus arbiter) (HGRANT), at time _{T 7,} I / O controller 30 next data D1 is sent to the internal bus 40 as read data 42 (HRDATA [31: 0]), and the DMA controller 20 stores the data D1 in the FIFO 220.

Similarly, at times T _{7 to} T ₈ , data D 2 to D 7 are transferred from the FIFO 320 of the I / O controller 30 to the FIFO 220 of the DMA controller 20.

Processing time _T 8 _{through T 14} is omitted because it is same as the processing time _T 11 _{through T 17} in FIG.

Thus, in the case of FIG. 8, in the control register 208 I / O read transfer mode is set to the continuous transfer mode, and the size continuous transfer is 32 bytes, DMA controller 20, the time _T 1 through T Upon receiving once DMA request signal 32 (DREQ) at _2, it is transferred at time _T 4 through T ₂ and 32 bytes of data D0~D7 continuously. In addition, since the DMA transfer mode is set to the continuous transfer mode in the DMA control register 302, the I / O controller 30 does not confirm the DMA acknowledge signal 22 (DACK), but the data of 32 bytes of D0 to D7. The data can be read from the FIFO 320 in order. That is, the DMA controller 20 and the I / O controller 30 do not need to perform handshake processing for every 32 bits (4 bytes) of data transfer. Therefore, the time required to transfer 32 bytes of data compared to the case of FIG. Can be shortened.

  FIG. 9 shows an example of a timing chart when the DMA controller 20 occupies the bus right and continuously transfers a plurality of unit size data in response to a single transfer request from the I / O controller 30. FIG. That is, the I / O read transfer mode is set to the continuous transfer mode in the control register 208 of the DMA controller 20, and the DMA transfer mode is set to the continuous transfer mode in the DMA control register 302 of the I / O controller 30. Hereinafter, the timing chart of FIG. 9 will be described.

DMA enable signal 212 (DE) is activated at time _{T 0,} I / O controller 30 at time _{T 1} is sent to DMA request signal 32 (DREQ).

DMA controller 20 receives a DMA request signal 32 (DREQ), at time _{T 2,} sends a bus request signal 45 (HBUSREQ) to the internal bus 40 (bus arbiter).

DMA controller 20, at time _{T 2,} when acquires the bus from the internal bus 40 (bus arbiter) receives a bus grant signal 46 (HGRANT), at time _T 2 through T _4, the bus request signal 45 (HBUSREQ) Continue sending and occupy the bus right.

The I / O controller 30 continuously reads the data D0 to D7 from the FIFO 320 and sends them to the internal bus 40 as read data 42 (HRDATA [31: 0]) at times T _{3 to} T _{5. The} DMA controller 20 Data D0 to D7 are stored in the FIFO 220.

The processing at times T _{5 to} T ₁₁ is the same as the processing after times T _{11 to} T ₁₇ in FIG.

  As described above, in the case of FIG. 9, the DMA controller 20 occupies the bus right and transfers the transfer target data for 32 bytes from the I / O controller 30 continuously. Can be shortened.

[Effect of the first embodiment]
According to the information processing apparatus 1 of the first embodiment, in response to a single data transfer request from the I / O controller 30, the DMA controller 20 continuously transfers a plurality of data to the FIFO 320 via the internal bus 40. As a result, the DMA transfer to the FIFO 320 can be speeded up.

  Further, according to the information processing apparatus 1 of the first embodiment, even when continuous transfer is difficult in response to a single data transfer request from the I / O controller 30, it is performed once by DMA transfer without using the CPU 10. Since one data can be transferred for each data transfer request, the load on the CPU 10 can be reduced.

  As described above, according to the information processing apparatus 1 of the first embodiment, the type of the external device 100 or the FIFO 320 determines whether a plurality of data is continuously transferred or one data is transferred in response to one data transfer request. The DMA transfer rate for the FIFO 320 can be optimized by appropriately selecting according to the size of the file.

  Further, according to the information processing apparatus 1 of the first embodiment, the data size of continuous transfer to the FIFO 320 can be variably set, so that the DMA transfer rate for the FIFO 320 can be further optimized.

  Further, according to the information processing apparatus 1 of the first embodiment, the internal bus 40 is occupied when the priority of continuous transfer to the FIFO 320 is high, and the internal bus 40 is not occupied when the priority is low. Therefore, the internal bus 40 can be used efficiently.

1-2. Second Embodiment Since the configuration of the information processing apparatus 1 of the second embodiment is the same as that of the first embodiment except for the DMA controller 20 and the I / O controller 30, the DMA controller 20 and the second embodiment in the second embodiment will be described below. Only the configuration of the I / O controller 30 will be described.

  10 and 11 are diagrams for explaining the configurations of the DMA controller and the I / O controller in the second embodiment, respectively.

  In the first embodiment, every time the DMA controller 20 receives one DMA request signal 32, the unit 320 reads or writes unit size data to the FIFO 320 of the I / O controller 30, or the continuous transfer size. Whether to read or write data continuously is selected according to a mode (single transfer mode or continuous transfer mode) set in the control register 202 and the DMA control register 302.

  On the other hand, in the second embodiment, as shown in FIG. 10 and FIG. 11, the I / O controller 20 sends out a DMA request signal 34 when requesting transfer of unit size data, and the continuous transfer size. A DMA request signal 36 is sent out when requesting continuous transfer of data for a minute.

  When the DMA controller 20 receives the DMA request signal 34, it sends a DMA acknowledge signal 22 to the I / O controller 20 to read or write one data to the FIFO 320, and when it receives the DMA request signal 36, The DMA acknowledge signal 22 is sent to the / O controller 20 to continuously read or write data corresponding to the continuous transfer size to the FIFO 320.

  The I / O controller 20 determines whether or not the data size stored in the FIFO 320 is equal to or larger than the continuous transfer size when it becomes a transfer source resource. It is determined whether or not the size is equal to or larger than the continuous transfer size. If the size is equal to or larger than the continuous transfer size, the DMA request signal 36 is transmitted. If the size is smaller than the continuous transfer size, the DMA request signal 34 is transmitted. However, if the data size stored in the FIFO 320 or the size of the empty area of the FIFO 320 is smaller than the unit size, the I / O controller 20 waits until the unit size is reached before sending the DMA request signal 34.

  That is, in the second embodiment, since the I / O controller 20 determines whether or not continuous transfer is possible based on the state of the FIFO 320, the mode setting required in the first embodiment is not necessary.

  Furthermore, in the first embodiment, in the continuous transfer mode, data transfer is waited until the data size stored in the FIFO 320 or the size of the free area of the FIFO 320 becomes equal to or larger than the threshold value. Therefore, depending on the state of the FIFO 320, the data transfer time In the second embodiment, a more appropriate transfer method is selected according to the state of the FIFO 320, so that the data transfer time can be optimized.

  Since other configurations of the DMA controller 20 and the I / O controller 30 in the second embodiment are the same as those in the first embodiment, the description thereof is omitted.

  12 to 15 show examples of timing charts for data transfer in the information processing apparatus according to the second embodiment.

FIGS. 12 and 13 are timing charts in the case where the transfer source resource and the transfer destination resource are the external memory 110 and the I / O controller 30, respectively, and 32 bytes (32 bits (4 bytes) × 8) of data are transferred. Yes (the transfer source resource may be the internal memory 12). 12 and 13, before the time T ₀ , the address RA 0 of the external memory 110 in which the first data to be transferred is stored is set in the transfer source address register 202. The transfer destination address register 204 is set with the address WA0 of the FIFO 320 of the I / O controller 30. The transfer size counter 206 is set with 32 bytes, which is the data size to be transferred. The unit size is 32 bits (4 bytes).

  FIG. 12 is a diagram illustrating an example of a timing chart when the DMA controller 20 transfers unit size data to the DMA request signal 34 (DREQ1). In FIG. 12, since the data size stored in the FIFO 320 is smaller than the continuous transfer size, the DMA request signal 34 (DREQ1) is generated and the DMA request signal 36 (DREQ2) is not generated. The other signal waveforms are the same as those in FIG.

  FIG. 13 is a diagram illustrating an example of a timing chart when the DMA controller 20 continuously transfers data corresponding to the continuous transfer size with respect to the DMA request signal 36 (DREQ2). In FIG. 13, since the data size stored in the FIFO 320 is equal to or larger than the continuous transfer size, the DMA request signal 36 (DREQ2) is generated and the DMA request signal 34 (DREQ1) is not generated. The other signal waveforms are the same as those in FIG.

FIGS. 14 and 15 are timing charts in the case where the transfer source resource and the transfer destination resource are the I / O controller 30 and the external memory 110, respectively, and 32 bytes (32 bits (4 bytes) × 8) of data are transferred. (The transfer destination resource may be the internal memory 12). 14 and 15, at time _{T 0} previously, addresses RA0 of FIFO320 the I / O controller 30 is set in the transfer source address register 202. The transfer destination address register 204 is set with the address WA0 of the external memory 110 in which the first data to be transferred is stored. The transfer size counter 206 is set with 32 bytes, which is the data size to be transferred. The unit size is 32 bits (4 bytes).

  FIG. 14 is a diagram illustrating an example of a timing chart when the DMA controller 20 transfers unit size data to the DMA request signal 34 (DREQ1). In FIG. 14, since the size of the empty area of the FIFO 320 is smaller than the continuous transfer size, the DMA request signal 34 (DREQ1) is generated and the DMA request signal 36 (DREQ2) is not generated. The other signal waveforms are the same as those in FIG.

  FIG. 15 is a diagram illustrating an example of a timing chart when the DMA controller 20 continuously transfers data corresponding to the continuous transfer size with respect to the DMA request signal 36 (DREQ2). In FIG. 15, since the size of the empty area of the FIFO 320 is equal to or larger than the continuous transfer size, the DMA request signal 36 (DREQ2) is generated and the DMA request signal 34 (DREQ1) is not generated. The other signal waveforms are the same as those in FIG.

[Effects of Second Embodiment]
According to 2nd Embodiment, in addition to the effect similar to 1st Embodiment, there exist the following effects.

  That is, according to the information processing apparatus 1 of the second embodiment, the I / O controller 30 determines whether continuous transfer to the FIFO 320 is possible based on the state of the FIFO 320, so that the DMA transfer to the FIFO 320 is more efficient. Can be done automatically.

1-3. Third Embodiment FIG. 16 is a diagram for explaining a configuration of an information processing apparatus according to a third embodiment.

  In the first embodiment, one I / O controller 30 is connected to the internal bus 40, but in the third embodiment, two I / O controllers 30 a and 30 b are connected to the internal bus 40. The I / O controllers 30a and 30b are connected to external devices 100a and 100b such as an SD memory card, a CF memory card, a USB device, and a PC, respectively, and control access to the external devices 100a and 100b, respectively.

  The DMA controller 20 in the third embodiment controls data transfer between any two resources of the internal memory 12, the external memory 110, and the I / O controllers 30a and 30b via the internal bus 40. That is, in the information processing apparatus 1 of the third embodiment, the DMA controller 20 can perform data transfer between the I / O controllers 30a and 30b via the internal bus 40.

  The configuration of the I / O controllers 30a and 30b is the same as the configuration of the I / O controller 30 shown in FIG. In addition, since the configuration other than the I / O controllers 30a and 30b in the third embodiment is the same as that of the first embodiment, description thereof is omitted.

  17 and 18, an example of a timing chart when transferring 32 bytes (32 bits (4 bytes) × 8) of data between the I / O controllers 30 a and 30 b in the information processing apparatus according to the third embodiment. Show. 17 and 18, in response to a single transfer request from the I / O controller 30a or 30b, the DMA controller 20 occupies the bus right and continuously transfers a plurality of unit size data. That is, both the I / O read transfer mode and the I / O write transfer mode are set to the continuous transfer mode in the control register 208 of the DMA controller 20, and the DMA transfer mode is set to the continuous transfer mode in the I / O controllers 30a and 30b. ing. Further, the bit widths of the external devices 100a and 100b are 32 bits and 16 bits, respectively. Therefore, the unit size of data transfer to the I / O controllers 30a and 30b is 32 bits (4 bytes) and 16 bits (2 bytes), respectively. Suppose that Further, it is assumed that the continuous transfer size of data transfer to the I / O controllers 30a and 30b is 32 bytes and 16 bytes, respectively. That is, the DMA controller 20 continuously transfers 32 bytes of data to the DMA request signal 32a (DREQ) from the I / O controller 30a, and transfers it to the DMA request signal 32b (DREQ) from the I / O controller 30b. On the other hand, 16 bytes of data are continuously transferred.

FIG. 17 is a timing chart when the transfer source resource and the transfer destination resource are the I / O controller 30a and the I / O controller 30b, respectively. 17, at time _{T 0} previously, addresses RA0 of FIFO320 the I / O controller 30a is set in the transfer source address register 202. In addition, the address WA0 of the FIFO 320 of the I / O controller 30b is set in the transfer destination address register 204. The transfer size counter 206 is set with 32 bytes, which is the data size to be transferred. Hereinafter, the timing chart of FIG. 17 will be described.

When the DMA enable signal 212 (DE) becomes active at time T _{0 and the} I / O controller 30 a sends the DMA request signal 32 a (DREQ) at time T ₁ , the DMA controller 20 sends the DMA request signal 32 a (DREQ). At time T _{2 to} T ₄ , the bus request signal 45 (HBUSREQ) is continuously sent to the internal bus 40 (bus arbiter) to occupy the bus right.

At time _T 3 through T _5, when the DMA controller 20 sends out a DMA acknowledge signal 22a (DACK), I / O controller 30a is read data 42 is read out in succession 32-bit data D0~D7 from FIFO 320 (HRDATA [ 31: 0]) to the internal bus 40, and the DMA controller 20 stores the 32-bit data D0 to D7 in the FIFO 220.

When I / O controller 30b sends out a DMA request signal 32 b (DREQ) at time _{T 6,} DMA controller 20 receives a DMA request signal 32 b (DREQ), at time _T 7 _{through T 14,} internal bus 40 (bus arbiter ) Continues to send the bus request signal 45 (HBUSREQ) to occupy the bus right.

DMA controller 20 reads the 32-bit data D0 from the FIFO 220, the time _T 8 through T ₉ and the time _T 9 in _{through T 10,} the upper 16-bit data D0 _H and Write the lower 16-bit data D0 _L of 32-bit data D0 Data 41 (HWDATA [15: 0]) is sent to the internal bus 40.

Similarly, at times T _{10 to} T ₁₁ , 32-bit data D1 to D3 are divided into upper 16-bit data D1 _{H to} D3 _H and lower 16-bit data D1 _{L to} D3 _L , respectively, from the FIFO 220 of the DMA controller 20. The data is transferred to the FIFO 320 of the I / O controller 30b.

Since continuous transfer size for I / O controller 30b is a 16-byte, with respect to one DMA request signal 32 b (DREQ), at time _T 8 _{through T 11,} it is 16-byte data D0~D3 Has been transferred.

Since the data size to be transferred is 32 bytes, I / O controller 30b in order to request the transfer of the remaining 16 bytes of the data D4 to D7, at time _{T 12,} 2 nd DMA request signal 32 b (DREQ ).

Then, at time _T 13 _{through T 15,} 32-bit data D4~D7 is upper 16-bit data, respectively _D4 H -D7 _H and FIFO220 from the I / O of the lower 16-bit data _D4 L -D7 DMA controller 20 is divided into _L The data is transferred to the FIFO 320 of the controller 30b.

At times T _{16 to} T ₁₇ , the DMA controller 20 generates a DMA end interrupt signal 24 (DMAINT), and the CPU 10 can recognize that the transfer process has ended. Moreover, the transfer processing is completed, setting of the control register 208 is automatically changed to a transfer prohibited from transfer permission, at time _{T 17,} DMA enable signal 212 (DE) is DMA controller 20 deactivates stops.

  In this way, in the case of FIG. 17, the continuous transfer size of data transfer to the I / O controller 30a is 32 bytes, which is the same as the transfer target data size (32 bytes). Due to (DREQ), 32 bytes of data are continuously transferred from the FIFO 320 of the I / O controller 30a to the FIFO 220 of the DMA controller. On the other hand, the continuous transfer size of data transfer to the I / O controller 30b is 16 bytes, which is smaller than the data size to be transferred (32 bytes), so that the DMA controller FIFO 220 is generated by two DMA request signals 32b (DREQ). 32 bytes of data are continuously transferred 16 bytes at a time to the FIFO 320 of the I / O controller 30b. Therefore, for example, even when the size of the FIFO 320 of the I / O controller 30b is smaller than the size of the data to be transferred, the DMA controller 20 performs continuous transfer in multiple times, so that all data to be transferred can be transferred as much as possible. It can be transferred reliably in a short time.

FIG. 18 is a timing chart when the transfer source resource and the transfer destination resource are the I / O controller 30b and the I / O controller 30a, respectively. 18, at time _{T 0} previously, addresses RA0 of FIFO320 the I / O controller 30b is set in the transfer source address register 202. The transfer destination address register 204 is set with the address WA0 of the FIFO 320 of the I / O controller 30a. The transfer size counter 206 is set with 32 bytes, which is the data size to be transferred. Hereinafter, the timing chart of FIG. 18 will be described.

When the DMA enable signal 212 (DE) becomes active at time T _{0 and the} I / O controller 30 b sends the DMA request signal 32 b (DREQ) at time T ₁ , the DMA controller 20 sends the DMA request signal 32 b (DREQ). At time T _{2 to} T ₉ , the bus request signal 45 (HBUSREQ) is continuously sent to the internal bus 40 (bus arbiter) to occupy the bus right.

At time _T 3 through T _6, the DMA controller 20 sends out a DMA acknowledge signal 22b (DACK), I / O controller 30b, the time _T 3 in the through T ₄ and time _T 4 through T _5, respectively 16-bit data D0 _H and D0 _H are successively read from the FIFO 320 and sent to the internal bus 40 as read data 42 (HRDATA [15: 0]). The DMA controller 20 sends 16-bit data D0 _H and D0 _H to the upper 16 bits and The 32-bit data D0 having the lower 16 bits is stored in the FIFO 220.

Hereinafter, similarly, at time _T 5 through T _6, 32 each upper 16-bit data _D1 H to D3 _H and the low-order 16-bit data _D1 L to D3 _L bits data D1~D3 from FIFO320 the I / O controller 30b The data is transferred to the DMA controller 20 and the data D1 to D3 are stored in the FIFO 220.

Since continuous transfer size for I / O controller 30b is a 16-byte, with respect to one DMA request signal 32 b (DREQ), at time _T 3 through T _6, 16 bytes of data D0~D3 Has been transferred.

Since the data size to be transferred is 32 bytes, I / O controller 30b in order to request the transfer of the remaining 16 bytes of the data D4 to D7, at time _{T 7,} 2 nd DMA request signal 32 b (DREQ ).

Then, at time _T 8 _{through T 10,} 32-bit data DMA controller 20 from FIFO320 of each upper 16-bit data _D4 H -D7 _H and the low-order 16-bit data _D4 L -D7 _L is I / O controller 30b of D4~D7 The data D4 to D7 are stored in the FIFO 220.

When I / O controller 30a sends out a DMA request signal 32a (DREQ) at time _{T 11,} DMA controller 20 receives a DMA request signal 32a (DREQ), at time _T 12 _{through T 14,} internal bus 40 (bus arbiter ) Continues to send the bus request signal 45 (HBUSREQ) to occupy the bus right.

At times T _{13 to} T ₁₅ , the DMA controller 20 continuously reads the data D0 to D7 from the FIFO 220 and sends the data as write data 41 (HWDATA [31: 0]) to the internal bus 40, and the I / O controller 30a. Stores the data D0 to D7 in the FIFO 320.

Processing time _T 16 _{through T 17} is omitted because it is same as the processing time _T 16 _{through T 17} in Figure 4.

  As described above, in the case of FIG. 18, the continuous transfer size of the data transfer to the I / O controller 30a is 32 bytes, which is the same as the transfer target data size (32 bytes). By (DREQ), 32 bytes of data are continuously transferred from the FIFO 220 of the DMA controller to the FIFO 320 of the I / O controller 30a. On the other hand, since the continuous transfer size of data transfer to the I / O controller 30b is 16 bytes, which is smaller than the data size to be transferred (32 bytes), the I / O controller is determined by two DMA request signals 32b (DREQ). 32 bytes of data are continuously transferred 16 bytes at a time from the FIFO 320 of the 30b to the FIFO 220 of the DMA controller. Therefore, for example, even when the size of the FIFO 320 of the I / O controller 30b is smaller than the size of the data to be transferred, the DMA controller 20 continuously transfers the data in a plurality of times. It can be transferred reliably in a short time.

[Effect of the third embodiment]
According to 3rd Embodiment, in addition to the effect similar to 1st Embodiment, there exist the following effects.

  That is, according to the information processing apparatus 1 of the third embodiment, not only DMA transfer is possible between the external memory 110 (or internal memory) and the I / O controller 30a or 30b, but also the I / O controller 30a and DMA transfer is also possible between 30b.

  Further, according to the information processing apparatus 1 of the third embodiment, even in the DMA transfer between the I / O controllers 30a and 30b, a plurality of data is continuously transferred in response to one data transfer request or one data Can be selected, so that the DMA transfer rate can be optimized.

2. Image Data Recording System FIG. 19 is a diagram for explaining the configuration of the image data recording system of this embodiment.

  The image data recording system 700 includes an information processing device 500, a secondary storage device 600, a primary storage device 610, a camera module 620, and a sensor 630.

  The information processing apparatus 500 includes a CPU 510, a RAM (Random Access Memory) 512, an external memory controller 514, a ROM (Read Only Memory) 516, a DMA controller 520, an I / O controller 530, an I / O controller 532, an internal bus 540, a camera. An interface circuit 550, an image processing circuit 560, and a sensor interface circuit 570 are included.

  The information processing apparatus 500 can be connected to a primary storage device 610 such as an SDRAM, and can transfer data to the primary storage device 610 via an external memory controller 514.

  The information processing apparatus 500 can be connected to a secondary storage device 600 such as an SD memory card or a CF memory card, and can transfer data to the secondary storage device 610 via the I / O controller 530. it can.

  The information processing apparatus 500 can be connected to an external device 602 such as a PC or a USB device, and can transfer data to the external device 602 via the I / O controller 532.

  Image data captured by the camera module 620 is sent to the image processing circuit 560 via the camera interface circuit 550.

  The image processing circuit 560 performs image processing such as resizing (cutting) and JPEG (Joint Photographic Experts Group) compression on the image data received via the camera interface circuit 550 to generate image data in a recording format.

  The recording format image data generated by the image processing circuit 560 is sequentially transferred to the primary storage device 610 by the DMA controller 530 via the external memory controller 514 and stored in the primary storage device 610.

  The CPU 510 reads out a program stored in the ROM 516 and performs information processing such as various data processing and interrupt processing using the RAM 512 as a work area.

  Further, the CPU 510 receives a detection signal of the sensor 630 via the sensor interface circuit 570, and determines whether or not a predetermined event has occurred.

  When the CPU 510 determines that a predetermined event has occurred, the CPU 510 performs processing for transferring the image data stored in the primary storage device 610 to the secondary storage device 600 and recording it. Specifically, the CPU 510 instructs the DMA controller 530 to transfer image data, and the DMA controller 530 DMA-transfers predetermined image data from the primary storage device 610 to the FIFO of the I / O controller 530 via the internal bus 40. Then, the I / O controller 530 sequentially records the image data written in the FIFO in the secondary storage device.

  The DMA controller 530 can DMA transfer image data from the FIFO of the primary storage device 610 or the I / O controller 530 to the FIFO of the I / O controller 532 via the internal bus 40. The I / O controller 532 sequentially transfers the image data written in the FIFO to the external device 602.

  For example, if a display is connected as the external device 602, the image data recorded in the primary storage device 610 or the secondary storage device 600 can be displayed on the display. If a PC is connected as the external device 602, image data recorded in the primary storage device 610 or the secondary storage device 600 can be analyzed in detail on the PC.

  When functioning the image data system 700 as a drive recorder, the camera module 620 is installed in front of the vehicle body and takes images of the front at regular time intervals. Are repeatedly recorded. The sensor 630 detects an impact applied to the vehicle body, and the CPU 510 determines that an accident has occurred if the level of the detection signal of the sensor 630 is equal to or greater than a threshold value. When an accident occurs, image data for a certain period (for example, 15 seconds before the accident and 15 seconds after the accident) recorded in the primary storage device 610 is transferred to the secondary storage device 600. To be recorded.

  By incorporating the information processing apparatus 1 of this embodiment into the image data recording system 700 as the information processing apparatus 500, the transfer time of the image data from the primary storage device 610 to the secondary storage device 600, the primary storage device 610 or 2 The transfer time of image data from the next storage device 600 to the external device 602 can be shortened. Therefore, the image data can be stored more reliably and the analysis time of the image data can be shortened.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, in the information processing apparatus 1 according to the first embodiment, the CPU 10, the internal memory 12, the external memory controller 14, the DMA controller 20, and the I / O controller 30 are connected to the internal bus 40. For example, the CPU 10 and the built-in memory 12 are connected to the first internal bus, the DMA controller 20 is connected to the second internal bus, and the external memory controller 14 and the I / O controller 30 are connected to the first internal bus via the bus selection circuit. You may comprise so that it can connect to either an internal bus and a 2nd internal bus.

  In the data recording system 700 of this embodiment, there is only one DMA controller, but a plurality of DMA controllers may be provided. For example, a DMA controller that exclusively controls the transfer of image data from the image processing circuit 560 to the external memory controller 514 and a DMA controller that controls other data transfers may be provided separately.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

The figure for demonstrating the structure of the information processing apparatus of 1st Embodiment. The figure for demonstrating the structure of the DMA controller in 1st Embodiment. The figure for demonstrating the structure of the I / O controller in 1st Embodiment. The figure which shows an example of the timing chart of the data transfer in 1st Embodiment. The figure which shows an example of the timing chart of the data transfer in 1st Embodiment. The figure which shows an example of the timing chart of the data transfer in 1st Embodiment. The figure which shows an example of the timing chart of the data transfer in 1st Embodiment. The figure which shows an example of the timing chart of the data transfer in 1st Embodiment. The figure which shows an example of the timing chart of the data transfer in 1st Embodiment. The figure for demonstrating the structure of the DMA controller in 2nd Embodiment. The figure for demonstrating the structure of the I / O controller in 2nd Embodiment. The figure which shows an example of the timing chart of the data transfer in 2nd Embodiment. The figure which shows an example of the timing chart of the data transfer in 2nd Embodiment. The figure which shows an example of the timing chart of the data transfer in 2nd Embodiment. The figure which shows an example of the timing chart of the data transfer in 2nd Embodiment. The figure for demonstrating the structure of the information processing apparatus of 3rd Embodiment. The figure which shows an example of the timing chart of the data transfer in 3rd Embodiment. The figure which shows an example of the timing chart of the data transfer in 3rd Embodiment. The figure for demonstrating the structure of the image data recording system of this embodiment.

Explanation of symbols

1 Information processing device, 10 CPU, 12 internal memory, 14 external memory controller, 20 DMA controller, 22 DMA acknowledge signal, 24 DMA end interrupt signal, 30 I / O controller, 30a I / O controller, 30b I / O controller, 32 DMA request signal, 34 DMA request signal, 36 DMA request signal, 40 internal bus, 41 write data, 42 read data, 43 address signal, 44 write signal, 45 bus request signal, 46 bus grant signal,
100 external device, 100a external device, 100b external device, 110 external memory, 200 register unit, 202 transfer source address register, 204 transfer destination address register, 206 transfer size counter, 208 control register, 210 control unit, 212 DMA enable signal, 220 FIFO, 230 bus master interface unit, 300 register unit, 302 DMA control register, 304 I / O control register, 310 DMA control unit, 312 transfer mode signal, 320 FIFO, 330 bus slave interface unit, 340 I / O interface unit , 500 Information processing device, 510 CPU, 512 RAM, 514 External memory controller, 516 ROM, 520 DMA controller, 530 I / O controller 532 I / O controller, 540 internal bus, 550 camera interface circuit, 560 image processing circuit, 570 sensor interface circuit, 600 secondary storage device, 602 external device, 610 primary storage device, 620 camera module, 630 sensor, 700 Image data recording system

Claims (8)

An internal bus,
DMA transfer control for transferring data from the transfer source resource to the transfer destination resource by reading data from the transfer source resource via the internal bus and writing the read data to the transfer destination resource via the internal bus And
An I / O control unit that includes an I / O buffer and performs data transfer between the I / O buffer and an external device;
A transfer information setting unit configured to set information for specifying the transfer source resource and the transfer destination resource and information for specifying a size of data to be transferred from the transfer source resource to the transfer destination resource,
The DMA transfer control unit
When the transfer source resource is the I / O control unit, whether or not a plurality of data is continuously read from the I / O buffer in response to a single data transfer request from the I / O control unit. When the data to be read is selected and the transfer destination resource is the I / O control unit, a plurality of data is requested in the I / O buffer in response to one data transfer request from the I / O control unit. The information processing apparatus is characterized by selecting whether to continuously write the data or to write one data. In claim 1,
The transfer information setting unit
An information processing apparatus, wherein the DMA transfer control unit sets information for specifying the number of data to be continuously read from or written to the I / O buffer. In claim 1 or 2,
The DMA transfer control unit
When continuously reading or writing the plurality of data to or from the I / O buffer, a selection is made as to whether or not to occupy the bus right of the internal bus from the start to the end of the read or write. An information processing apparatus characterized by that. In any one of Claims 1 thru | or 3,
The transfer information setting unit
Set the transfer mode of data transfer from the transfer source resource to the transfer destination resource,
The DMA transfer control unit
Based on the transfer mode, in response to one data transfer request, whether to read or write the plurality of data to the I / O buffer continuously or to read or write one data An information processing apparatus characterized by selecting. In any one of Claims 1 thru | or 3,
The I / O control unit
When the resource becomes the transfer destination resource, the size of the free area of the I / O buffer is compared with the size of the plurality of data continuously written to the I / O buffer. The size of the data stored in the / O buffer is compared with the size of the plurality of data continuously read from the I / O buffer, and a continuous transfer request signal is sent to the DMA transfer control unit based on the comparison result Or send a unit transfer request signal,
The DMA transfer control unit
When the continuous transfer request signal is received, the plurality of data is continuously read or written to the I / O buffer, and when the unit transfer request signal is received, the I / O buffer is read. An information processing apparatus that reads or writes one piece of data. In any one of Claims 1 thru | or 5,
The I / O control unit
If the size of the data that the DMA transfer control unit continuously reads or writes from the I / O buffer is smaller than the size of the data to be transferred, the DMA transfer control unit An information processing apparatus characterized in that a data transfer request is made in a plurality of times. In any one of Claims 1 thru | or 6.
A first I / O controller including the first I / O buffer;
A second I / O control unit including a second I / O buffer;
The DMA transfer control unit
When the transfer source resource is the first I / O control unit and the transfer destination resource is the second I / O control unit, 1 from the first I / O control unit In response to one data transfer request, it is selected whether to read a plurality of data continuously from the first I / O buffer or to read one data, and once from the second I / O control unit. In response to the data transfer request, the information processing apparatus selects whether to write a plurality of data continuously or to write one data in the second I / O buffer. An information processing apparatus according to claim 1;
At least one camera module;
A first storage device that temporarily stores a plurality of image data captured by the camera module at predetermined intervals;
A non-volatile second storage device that performs data transfer with the I / O buffer of the I / O control unit of the information processing device,
The information processing apparatus includes:
Based on the occurrence of a predetermined event, the DMA transfer control unit transfers the image data stored in the first storage device to the I / O buffer, and the I / O control unit transfers the I / O control unit. An image data recording system, wherein the image data transferred to a buffer is transferred to the second storage device.

Images