JP4821628B2 - Packet buffer FIFO memory device - Google Patents

Description

The present invention relates to a packet buffer memory.

  The packet buffer FIFO memory is used for speed conversion and queuing in an apparatus for processing packets. A typical configuration includes a memory for storing packet data, a write address control unit, a read address control unit, and a state control unit.

  The conventional configuration uses a ring-like configuration that allows continuous writing from the last address of the memory to the first address, and allows continuous writing and reading, and a clock with the same frequency that synchronizes the write clock and the read clock. It is.

  In addition, this memory has a dual port RAM configuration capable of reading and writing at the same time, and is a memory in which data of the next packet can be written during data reading.

  As input conditions for the packet buffer FIFO memory, write data with the packet size added to the beginning of the packet data and a clock for generating a write address are included.

  It also includes a write enable that asserts from the start to the end of the data of one packet to be written to allow writing to the memory, a clock for read address generation, and a device on the memory output side. In addition, there is a RESET signal that notifies that the module is ready for input (acceptance) and resets the read enable, write address, and read address values that allow the call.

  As an operation method, in order to first make the memory empty (EMPTY) state, the write address and the read address are reset from the state control unit by an external RESET signal, respectively, and the memory is made empty (EMPTY) state and initialized. To do. At this time, the read address control unit stops the read operation because the EMPTY signal is asserted.

  Next, when the packet is received, the write address control unit recognizes that the FULL signal output from the state control unit is negated when there is no free memory area (FULL state), and is in a writable state. Judge. That is, the memory is empty (EMPTY).

  Subsequently, while the write enable is asserted, the write address generated by incrementing with the write clock and the memory write enable signal to the memory are output to the memory. With this write address and a memory write enable signal, write data with the packet size added to the beginning of the packet data is stored in the memory.

  Next, the state control unit constantly compares the write address and the read address of the memory, detects the difference between the write address and the read address generated by writing the packet, and negates the EMPTY signal.

  The read address control unit determines that data has been written to the memory when the EMPTY signal is negated. Further, it is confirmed that the read enable signal indicating that the memory output side device, module or the like can be input (accepted) is asserted.

  If the read enable signal is asserted, the packet size at the head address is read, and a read address incremented by the packet size by the read clock is generated.

  The read address control unit outputs a memory read enable signal to the memory together with the generated read address to the memory, so that one packet of read data is output from the memory.

  In addition, when the remaining capacity of the memory becomes below a certain level, the status control unit asserts that the area for writing the next packet size data is insufficient (exceeds the FULL state) and asserts the FULL signal to write address control unit. And the write operation is stopped in advance so that the write address does not overtake the read address.

  This operation prevents data loss due to overwriting of unread data by writing over the read address exceeding the read address.

  Here, it is assumed that the packet size on the reading side shows an abnormal value due to some external factor at the time of writing or reading.

  At this time, if a value larger than the normal packet size is indicated, the read control unit performs reading using the value, so that it is expected that the read operation will continue beyond one normal packet. Is done. As a method of avoiding this operation, a comparison is always made between the write address value and the read address value to check that they are the same value.

  If the values are the same, the state control unit determines that the memory is empty (EMPTY) and asserts the EMPTY signal.

  The read address control unit outputs the ERROR signal to the state control unit because the EMPTY signal is asserted even though the reading is not completed.

  The status control unit initializes the address value by outputting a RESET signal to both the write address control unit and the read address control unit, immediately stops the memory read operation, and starts the memory operation from the state where the memory is empty. Restart.

  The packet buffer FIFO memory having the conventional configuration can stop the abnormal operation of the memory when the read address exceeds the write address.

Further, a technique for controlling the writing and reading of packet data stored in the packet buffer FIFO memory is described in, for example, Patent Document 1 shown below.
JP-A-9-247213

  However, when writing and reading are always performed, if the packet size shows an abnormal value due to some external cause, and the read address does not overtake the write address, the conventional circuit can detect such an abnormality. As long as the state control unit does not assert the EMPTY signal (until the memory becomes empty), the read operation is repeated, and thus abnormal data reading continues.

  In the case of the above operation, the write address and the read address are not matched, so there is a possibility of malfunction such as reading an abnormal packet or continuing to read, and if malfunction occurs, the malfunction is detected. Difficult to do.

  Therefore, an object of the present invention is to provide a packet buffer FIFO memory that solves the above problems and that operates normally even when the packet size shows an abnormal value.

A packet buffer FIFO memory device according to the present invention is a packet buffer FIFO memory device that performs writing to a memory and reading from the memory under sequentially controlled packet data for sequentially supplied packet data , and sets a write address for the packet data. Write means for writing to the memory while designating, Read means for sequentially reading data from the memory while designating a read address, State control means for performing FIFO control for the write means and the read means, The writing means includes a monitoring flag indicating by a value whether or not it is the start address of the packet for each write data of the packet data, and a monitoring flag inserting means for inserting the packet size of the packet data, and the reading means Read the write data from the memory Look including an abnormality determination unit that the value of the monitoring flag and the monitoring flag by extracting the packet size is the extracted from the read data to determine whether the expected value indicative of the leading address while out, the The reading unit determines that the value of the monitoring flag extracted by the abnormality determination unit for one read data is the expected value, and then the newly extracted data is extracted by the abnormality determination unit. When it is determined that the value of the monitoring flag is not the expected value, it is determined whether or not reading of the write data corresponding to the packet size extracted by the abnormality determination unit is completed for the one read data. It is characterized by that.

  According to the present invention, it is possible to detect an abnormality in packet data based on the comparison between the bit value of the monitoring flag and the expected value. When an abnormality is detected, the abnormal data is skipped and the address is determined by the write pointer value. By taking the consistency of values, it is possible to operate data writing and reading from the next packet normally.

  FIG. 1 is a block diagram for explaining the operation of the packet buffer FIFO memory of the present invention.

  The memory 1 in this embodiment has a ring-like configuration that allows continuous writing from the last address of the memory 1 to the head address. The memory 1 is capable of continuous writing and reading, and is a clock having the same frequency in which the write clock 2 and the read clock 3 are synchronized.

  The operation of the memory 1 starts with the RESET signal from the state control unit 7 to the write address control unit 5 and the read address control unit 6 by an external RESET input 4 in order to empty the memory 1 first (EMPTY). 8 is sent to initialize memory 1 to empty (EMPTY). At this time, the read address controller 6 stops the read operation because the EMPTY signal 9 is asserted.

  Next, when a packet is received when there is no free space in the memory (FULL state), the write address control unit 5 recognizes that the FULL signal 10 output from the state control unit 7 is negated and the memory 1 Judge that it is in a writable state.

  Next, while the write enable 11 is asserted, the write address 12 generated by incrementing the write clock 2 and the memory write enable signal 13 to the memory 1 are output to the memory 1.

The write address control unit 5 generates write data 15 in which the packet size of the packet data is added to the head of the packet data based on the write address 12, the memory write enable signal 13 , and the head address information 14.

  The head address monitoring / flag insertion unit 16 generates a head address monitoring flag indicating the head address of the packet, and stores the data with the head address monitoring flag and the packet size added thereto in the memory 1. The head address monitoring / flag insertion unit 16 constitutes a monitoring flag insertion unit. The head address monitoring flag is significant at “1” and is insignificant at “0”.

  By this operation, information for determining the head address of one packet can be given.

  The write pointer control unit 17 stores a value obtained by adding 1 to the write address 12 for each packet in the write pointer. With this operation, the address value when one packet is normally written can be held.

  Next, the state control unit 7 constantly compares the write address 12 and the read address 18 of the memory 1 to detect a difference between the write address 12 and the read address 18 generated by writing the packet, and negates the EMPTY signal 9 Let

  The read address control unit 6 determines that data has been written to the memory 1 when the EMPTY signal 9 is negated. Further, it is confirmed that a read enable signal 19 indicating that an output side device, module, etc. (not shown) of the memory 1 can be input (accepted) is asserted.

  In the circuit configuration of the present invention, if the read enable signal 19 is asserted, the head address monitoring flag monitoring / packet size reading unit 20 reads the packet size and head address monitoring flag at the head address.

  If the head address monitoring flag is “1”, that is, if it is an expected value, it is determined that reading can be normally performed from the head of one packet.

  An address is generated by incrementing the read address 18 by the packet size information 21 by the read clock 3.

  Next, a memory read enable signal 22 from the read address control unit 6 to the memory 1 and the generated read address 18 are output to the memory 1 and read data 23 of one packet is output from the memory 1.

  At this time, the head address monitoring flag monitoring / packet size reading unit 20 reads the head address monitoring flag and the packet size at the head address. When the head address monitoring flag reads “0” indicating that the address is in the middle of one packet, it is determined that normal reading is impossible, and a head address error 24 is output to the read address control unit 6.

  Note that the head address monitoring flag monitoring / packet size reading unit 20 constitutes an abnormality determining means when reading packet data.

  The read address control unit 6 stops the memory read operation and matches the read address 18 with the write pointer value 25 held in the write pointer control unit 17.

  By this operation, abnormal data is skipped, and the address value is matched by matching the read address 18 with the write pointer value 25, which is the address value for which normal writing has been completed. With the function to operate.

  FIG. 2 is a flowchart for explaining the write operation of the memory 1 according to the embodiment of the present invention.

  First, the state control unit 7 determines whether or not the received packet data has a size that can be written to an empty area of the memory 1 (step S1).

  If not possible, it is determined that the memory 1 is FULL (not writable) (step S2). The determination is repeated until the memory 1 can be written.

  When writing to the memory 1 is possible, the write address control unit 5 and the start address monitoring / flag insertion unit 16 write the start address monitoring flag indicating the start address at the beginning of the data to be written and the packet size information of one packet ( Step S3), followed by writing packet data (step S4).

  The write address 12 is incremented (step S5), and the packet data is written to the memory 1 by repeatedly incrementing the address until one packet of packet data is written (step S6).

  When the writing is completed, the write pointer control unit 17 holds the value of the address value +1 where the writing is completed as the write pointer value 25 (step S7), and the memory write operation is completed (step S8). The write pointer value 25 is used for error processing during a read operation of the memory 1 described later.

 FIG. 3 is a flowchart for explaining the read operation of the packet buffer FIFO memory according to the embodiment of the present invention.

  When the memory read operation is started, the state control unit 7 determines whether a difference between the address values is detected (whether the write address 12 is ahead of the read address 18) (step S11). If the difference could not be detected (write address 12 and read address 18 have the same value), memory 1 is determined to be empty (EMPTY) (step S12), and until the difference between the address values is detected (the memory is not written) Repeat until it is).

  When a difference between the address values is detected, the head address monitoring flag monitoring / packet size reading unit 20 reads the head address monitoring flag and the packet size (step S13), and determines the address by determining the head address monitoring flag (step S14). It is determined whether or not reading can be started from the top.

  At this time, if the head address monitoring flag is “0”, that is, the determination is “No”, it is determined that reading from the head address is not possible, data reading from the memory 1 is stopped, and the reading address 18 Is subjected to error processing to match the write pointer value 25 held by the write pointer control unit 17 (address value at which writing has been completed + 1) (step S15).

  By this operation, abnormal data can be skipped, and the next packet data can be normally written and read.

  When the start address monitoring flag is “1”, that is, the determination is “Yes”, it is determined that the read from the start address can be normally performed, and the data is read from the memory 1.

  Next, the read address 18 is incremented by 1 (step S16), and data reading at the next address is started.

  At this time, the start address monitoring flag is monitored even at a position other than the start address (step S17). Even though the reading for the packet size has not been completed, the start address monitoring flag is “1”, that is, the determination is “Yes”. If there is, it is determined as abnormal, reading of data from the memory 1 is stopped, and the read address control unit 6 performs error processing for matching the read address 18 with the write pointer value 25 (step S15).

  This operation allows normal writing and reading from the next packet data. When the head address monitoring flag is “0”, that is, the determination is “No”, it is determined as normal and the process proceeds to the next step.

  Next, the read address control unit 6 determines whether the read address 18 is the same value as the write pointer value 25 (step S18).

  At this time, if the determination is “Yes”, reading of packet data for the packet size has not been completed, so it is determined that the read packet size information has an abnormal value due to some external cause, and the memory Data reading from 1 is stopped, and error processing is performed to match the read address 18 with the write pointer value 25 (step S15).

  This operation allows normal writing and reading from the next packet data.

  If the determination is “No”, it is determined as normal and data is read from the memory 1.

  After the data is normally read out, it is determined from the packet size information read in advance whether or not the reading for the packet size is completed (step S19).

  At this time, if the determination is “No”, it is determined that reading for the packet size is not completed, and reading is performed by incrementing the reading address 18 by 1 until it is determined that reading for the packet size is completed. Repeat the operation.

  If the determination is “Yes”, it is determined that data reading for one packet has been completed, and the process proceeds to the next step.

  When the data reading for one packet is completed, the head address monitoring / flag insertion unit 16 deletes the head address monitoring flag indicating the head address of this one packet, that is, writes “0” (step S20).

  Next, the read address control unit 6 increments the read address by 1 so as to match the read address 18 with the head address of the next packet (step S21), and performs a memory read process for the next packet.

  FIG. 4 is a diagram for explaining the internal operation of the packet buffer FIFO memory according to the present invention.

  Here, it is assumed that there is a memory 26 having a capacity from addresses 0x0000 to 0xffff.

  The memory 26 is in an empty state before writing (the write address 12 and the read address 18 have the same value).

  Next, the writing is started, and the head address monitoring / flag insertion unit 16 writes “1” indicating the head address to the head address monitoring flag prepared for each head address of the packet, and stores the packet size information. Write. Further, “0” is written in the head address monitoring flag other than the head address of the packet.

  When the writing for one packet is completed, the write pointer control unit 17 holds the address value next to the write end address as the write pointer value 25.

  Next, the state control unit 7 detects that the write address 12 has advanced from the read address 18, determines that data has been written, and performs a read operation.

  When the start address monitoring flag is “1” indicating that the start address is 1 at the time of the read operation, the read address control unit 6 determines that the read start position (address) is normal, and the data is stored in the data area of the start address. A certain packet size is read and the packet size is read.

  When the reading is completed, the head address monitoring / flag insertion unit 16 erases the head address monitoring flag (writes “0”), and the operation ends.

  FIG. 5 is a diagram for explaining the operation when the packet size becomes abnormal according to the embodiment of the present invention.

  If the packet size information becomes abnormal due to some external cause during reading, and the reading address stops in the middle of one packet, normally the reading operation is repeated until the memory 26 becomes empty (EMPTY). Will continue to be output.

  However, in the present invention, it is possible to read that the start address monitoring flag is “0” and determine that it is abnormal. By aligning the read pointer to the write pointer value 25, the abnormal data is skipped and the memory is read. The address information is returned to a normal state, and normal operation can be performed from the memory operation of the next packet.

  As described above, according to the embodiment of the present invention, by using the head address monitoring flag in the FIFO memory device for the packet buffer, the update of the read address 18 that could not be detected in the past is performed in the middle of one packet. Even if there is an abnormality that stops, the abnormality can be detected by the head address monitoring flag.

  When the abnormality is detected, the abnormal data is skipped, and the address value is matched by the write pointer value 25, whereby the data writing and reading from the next packet can be normally operated.

  In the above embodiment, when the packet data has been written to the memory 1, the value of the address value + 1 that has been written is held as the write pointer value 25, but the value that is held as the write pointer value 25. The address value + N (N = 1, 2, 3,...) For which writing has been completed may be used.

  In the above embodiment, the head address monitoring flag is significant at “1” and unintentional at “0”, but may be significant at “0” and insignificant at “1” depending on circumstances.

It is a block diagram explaining operation | movement of the FIFO memory for packet buffers of this invention. 4 is a flowchart illustrating a write operation of the memory 1 according to the embodiment of the present invention. It is a flowchart explaining the read-out operation | movement of the memory of the Example of this invention. It is a figure explaining operation | movement inside the memory of the FIFO memory for packet buffers by this invention. It is a figure explaining operation | movement when the packet size of the FIFO memory for packet buffers becomes abnormal by this invention.

Explanation of symbols

1 memory
2 Write clock
3 Read clock
4 RESET input
5 Write address controller
6 Read address controller
7 State controller
8 RESET signal
9 EMPTY signal
10 FULL signal
11 Write enable
12 Write address
13 Memory write enable
14 Start address information
15 Write data
16 Start address monitoring / flag insertion part
17 Write pointer controller
18 Read address
19 Read enable
20 Start address monitoring flag monitoring / packet size reading part
21 Packet size information
22 Memory read enable
23 Read data
24 Start address error
25 Write pointer value
26 memory

Claims (3)

A packet buffer FIFO memory device that performs writing to a memory and reading from the memory for sequentially supplied packet data under FIFO control,
A writing means for writing to the memory while designating a write address for the packet data;
Read means for sequentially reading data from the memory while designating a read address;
State control means for performing FIFO control for the writing means and the reading means,
The writing means inserts a monitoring flag indicating an expected value for the write data at the head address of the packet data and a packet size of the packet data, and sets the monitoring flag for the write data other than the head address. Including monitoring flag insertion means for inserting as a value different from the expected value ;
It said reading means determines whether or not the value of the monitoring flag and the monitoring flag by extracting the packet size is the extracted from data read while reading the write data from the memory is the expected value look including an abnormality determination means,
The reading means determines that the value of the monitoring flag extracted by the abnormality determination means for one read data is the expected value, and then the newly read data is extracted by the abnormality determination means. When it is determined that the value of the monitoring flag is not the expected value, it is determined whether reading of the write data corresponding to the packet size extracted by the abnormality determination unit is completed for the one read data A packet buffer FIFO memory device. It said write means includes a write pointer which holds the write end position address indicating a write end position of each of the write data,
When the abnormality determining unit determines that the value of the monitoring flag is not the expected value for the one read data, and the value of the monitoring flag is set by the abnormality determining unit for the newly read data. 2. The packet buffer FIFO memory device according to claim 1 , wherein the read address is matched with the write end position address when it is determined that the value is the expected value . 2. The packet buffer FIFO memory device according to claim 1, wherein the reading unit deletes the monitoring flag when it is determined that reading of the write data for the packet size is completed .

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