JP2002073411A - Method and device to judge memory capacity of eeprom - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device to judge an EEPROM memory capacity, which can decide an access sequence by using a result of the judgment based upon the procured EEPROM memory capacity that can be automatically determined when the capacity of the EEPROM is unknown in advance. SOLUTION: The device enters an address data into an EEPROM 2 and counts the number of address bits entered until an EEPROM 2 output reaches a pre-determined value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM (electrical
EEPROM storage capacity determination device and EE for determining storage capacity of ly erasable and programmable read only memory
The present invention relates to a method for determining the storage capacity of a PROM.

[0002]

2. Description of the Related Art Conventionally, EEPROMs widely used include those having a storage capacity of 1 k bits and those having a storage capacity of 2 k bits. In order to access such an EEPROM, it is usual to access by inputting address data serially. In an EEPROM having a storage capacity of 1 kbit, 1 is required.
Address data is composed of 6 bits, and in an EEPROM having a storage capacity of 2 k bits, one address data is composed of 8 bits. Since the number of bits of the address data is different, a case where an EEPROM having a storage capacity of 1 kbit is used and a case where an EEPROM having a storage capacity of 2 kbit are used are as follows.
A different EEPROM drive program must be used.

For this reason, conventionally, the storage capacity of the EEPROM has been determined in advance to be 1 kbit or 2 kbit, and an access sequence suitable for each has been programmed and used.

[0004]

SUMMARY OF THE INVENTION However, recent ICs
Due to the shortage, EEPROM of 1 kbit storage capacity
In many cases, it is not known whether an OM can be obtained or an EEPROM having a storage capacity of 2 k bits can be obtained. For this reason, software for driving the EEPROM cannot be created until the EEPROM is actually obtained, causing a delay in the product planning schedule.

[0005] An object of the present invention is to make it possible to automatically determine the storage capacity of an obtained EEPROM even when the storage capacity of the EEPROM is not known in advance, and to use the result of the determination.
An object of the present invention is to provide an EEPROM storage capacity determination device and an EEPROM storage capacity determination method capable of determining an access sequence.

[0006]

According to a first aspect of the present invention, there is provided an EEPROM storage capacity determining apparatus for inputting a chip select signal for making an EEPROM accessible to the EEPROM. Chip select signal inputting means, serial data inputting means for inputting serial data including a read command for setting the EEPROM to a data reading mode and address data of a predetermined number of bits to the EEPROM, and the serial data inputting means comprising: Address data input bit number counting means for counting the number of input bits of the address data input to the
An EEPROM for monitoring the output level of the OM and inputting a stop signal to the address data input bit number counting means to stop the counting operation of the address data input bit number counting means when the output level takes a predetermined value. Output level determining means.

According to the present invention, by inputting serial data including a read command to an EEPROM which can be accessed by inputting a chip select signal,
The PROM is in the data read mode. In the data read mode, the EEPROM changes the level of the output terminal from the high impedance state to the low level according to the specification when determining that address data of a required number of bits has been input. Therefore, while counting the number of bits of the address data by the address data input bit number counting means, the serial data input means sets the EEPRO bit by bit.
When input to M, the EEPROM that receives this address data changes the level of its output terminal from a high impedance state to a low level when it determines that the required number of bits of address data has been input. Is detected by the output level determining means of the EEPROM, and the counting operation of the address data input bit number counting means is stopped.

As a result, an EEPROM having a storage capacity of 1 kbits
Since the output level of the OM becomes low when the address data input from the serial data input means becomes 6 bits, the counting of the address data input bit number counting means is stopped at this time, and the count value becomes 6 bits.
Therefore, it can be automatically determined that the EEPROM has a storage capacity of 1 kbit. When the memory capacity is 2 k bits, the output level is set to a low level when the input address data becomes 8 bits. Therefore, the count value of the address data input bit number counting means indicates 8, and similarly, It can be automatically determined that the EEPROM has a storage capacity of 2 kbits.

Therefore, according to the first aspect of the present invention, the storage capacity of the obtained EEPROM can be automatically determined, and the access sequence can be determined by using the result of the determination.

According to a second aspect of the present invention, in the EEPROM storage capacity judging device according to the first aspect, the address data input bit number holding the count value counted by the address data input bit number counting means is provided. It is characterized by further comprising storage means. According to the present invention, since the determination result of the storage capacity of the EEPROM is held in the address data input bit number storage means, the determination result of the storage capacity of the EEPROM can be used as needed, and the access sequence is determined. It is convenient at times.

According to a third aspect of the present invention, in the EEPROM storage capacity determining apparatus according to the first or second aspect, a serial clock is generated and the generated serial clock is input to the EEPROM. A serial clock input means is further provided. According to the present invention, a serial clock serving as a basis for a sequential operation can be generated by an EEPROM storage capacity determination device itself without receiving external supply, so that the EEPROM storage capacity determination device can be used as a device such as a printer. This increases the degree of freedom of embedding in the memory, and provides an easy-to-use EEPROM storage capacity determination device.

The EE according to the invention described in claim 4 of the present application.
A method of determining the storage capacity of a PROM includes a chip select signal inputting step of inputting a chip select signal to the EEPROM to enable access to the EEPROM, a read command to set the EEPROM in a data read mode, and address data of a predetermined number of bits. A serial data input step of inputting serial data to the EEPROM, an address data input bit number counting step of counting the number of input bits of address data input to the EEPROM in the serial data input step, and an output of the EEPROM. An EEPROM output level determining step of monitoring a level and stopping the operation of counting the number of input bits of the address data when the output level takes a predetermined value. According to the present invention, the same effect as that of the first aspect can be obtained.

According to a fifth aspect of the present invention, there is provided the EEPROM storage capacity determining method according to the fourth aspect, wherein:
An address data input bit number storing step of holding a count value counted in the address data input bit number counting step is further provided. According to the present invention, the same effect as that of the second aspect of the present invention can be obtained by utilizing the determination result of the storage capacity of the EEPROM stored in the address data input bit number storage step as needed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing functional blocks of an embodiment of an EEPROM storage capacity determination device according to the present invention. Each functional block of the present embodiment includes:
It may be realized by hardware or by software on a computer. FIG. 2 is a timing chart showing signal waveforms of signals transmitted and received between these functional blocks and the EEPROM.

Referring to FIGS. 1 and 2, EE of this embodiment is shown.
The PROM storage capacity determination device 1 has the following functional blocks for determining the storage capacity of the EEPROM 2.

That is, it includes a chip select signal input means 11 for inputting a chip select signal CS for making the EEPROM 2 accessible to the EEPROM 2, a read command for setting the EEPROM 2 in a data read mode, and address data of a predetermined number of bits. Serial data input means 12 for inputting serial data DI to EEPROM 2, address data input bit number counting means 13 for counting the number of input bits of address data input to EEPROM 2 by serial data input means 12, and monitoring the output level of EEPROM 2. Then, a stop signal for stopping the counting operation of the address data input bit number counting means 13 is input to the address data input bit number counting means 13 when the output level takes a predetermined value.
4, an address data input bit number storage means 15 for holding the count value counted by the address data input bit number counting means 13, and a serial clock input for generating a serial clock SK and inputting the generated serial clock SK to the EEPROM 2. Means 16.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. First, in order to access the EEPROM 2, the chip select signal CS is raised to a high level and the chip select signal input means 11
The data is input to the EEPROM 2 (step S1).

On the other hand, the serial clock input means 16
The serial clock SK is generated and sequentially input to the EEPROM 2. The instruction is executed in the EEPROM 2 by fetching the serial data DI in synchronization with the rising edge of the serial clock SK.

When the chip select signal CS rises to a high level, the EEPROM 2 starts operating and becomes accessible, and the serial data input means 12 raises the serial data DI to a high level and sets it to logic 1 (step S2). ). The first rise of the serial data DI is referred to as a start bit. At the first rise of the serial clock SK (step S3) (clock No. 1) after the rise of the start bit, the logic 1 of the start bit is taken into the EEPROM 2. Then, the EEPROM 2 releases the standby state up to that point and starts operation.

Next, the serial data input means 12 supplies the next two clocks of the serial clock SK (clock No.
Data reading (1, 0) and writing (0,
1) A command for each operation of the EEPROM 2, such as data erasing (1, 1), is input to the EEPROM 2 (step S4). The logical value of these two bits is called an operation code. In the present embodiment, in order to make the EEPROM 2 perform a data reading operation, the operation code (0, 1) can be read by the clock Nos. 2, 3 of the serial clock SK (step S5).
The level of the serial data DI is changed.

Next, the serial data input means 12 changes the signal level of the serial data DI for at least the time read at the rise of at least eight clocks of the serial clock SK and outputs it as address data (steps S6 to S9). . That is, address data of at least 8 bits is output bit-serial.

In the timing chart of FIG. 2, X, A6, A5,..., A0 are shown as each bit of the address data to be read in synchronization with the rising of the clocks No. 4 to No. 11 of the serial clock SK. .

The reading operation will be described in more detail. The serial data input means 12 outputs the serial data DI
Is set as one bit (X) of the address signal and input to the EEPROM 2 (step S6). The address data input operation by the serial data input means 12 is counted by the address data input bit number counting means 13 as 1 bit number (step S7). Next, the serial clock input means 16 inputs the serial clock SK of the clock No. 4 to the EEPROM 2 (step S8),
The EEPROM 2 takes in the signal level of the serial data DI as the first bit (X) of the address data in synchronization with the rise of the serial clock SK of No. 4. Subsequently, the output level determination means 14 of the EEPROM 2
The signal level of the serial output data DO of OM2 is determined (step S9), and the signal level of logic 0 (low level)
Then, the process returns to step S6, and the operation of reading the signal level of the next bit (A6) of the address data is performed. Note that the serial output data DO of the EEPROM 2
The output terminal is in a high-impedance state until a predetermined number of bits (6 bits in the case of 1 k-bit storage capacity, 8 bits in the case of 2 k-bit storage capacity) are inputted, and a logic 0 signal is input. It does not become a level. The address data input here is not used for the actual reading operation,
Since the data is for determining the storage capacity of the PROM 2, any data may be used. That is, at least 8-bit data may be configured as the dummy data.

As described above, when the value of each bit of the address data of the serial data DI is input to the EEPROM 2, if the EEPROM 2 is an EEPROM having a storage capacity of 1 k bits, the address data of the sixth bit (A2) is When the signal is input, the signal level of the serial output data DO is set to the low level, assuming that the address data for the EEPROM 2 to perform the reading operation has been input. Therefore, EEPROM2
The output level determination means 14 detects a change in the signal level of the serial output data DO (step S9), and stops the counting operation of the address data input bit number counting means 13. At this time, the count value of the address data input bit number counting means 13 is 6,
2 indicates that the storage capacity is 1 k bits. The count value of the address data input bit number counting means 13 is stored by the address data input bit number storage means 15 (step S10). After this, normal data reading and data writing operations may be continued,
If the purpose is only to determine the storage capacity of No. 2, the chip select signal CS falls and the determination operation ends (step S11).

If the storage capacity of the EEPROM 2 is 2 k bits, the number of bits of the serial data DI is 8
The output terminal continues to be in a high impedance state until it becomes a bit (bit A0), and when the address data of the eighth bit (A0) is taken in, the serial output data DO is set to logic 0.

The EEPROM 2 stores a chip select signal C
Unless S goes low, the serial output data D
From the first rise of the serial clock SK after O is set to logic 0 (the rise of the clock of No. 12 in the example of FIG. 2), the data recorded at the input address is output (the example of FIG. 2). D15 is the first bit of this data).

The serial clock input means 16 of the functional blocks shown in FIG.
The system clock of a system such as a printer in which the storage capacity determination device is incorporated may be used instead of being provided as one component of the storage capacity determination device, and the address data input bit number storage means 15 must always be provided. There is no. Further, the function blocks of the chip select signal input unit 11, the serial data input unit 12, the address data input bit number counting unit 13, and the output level determination unit 14 of the EEPROM are used in a system such as a printer in which the storage capacity determination device is incorporated. It may be realized as a part of the function of the CPU.

[0028]

As described above, in the EEPROM storage capacity determining apparatus and the EEPROM storage capacity determining method of the present invention, when the address data is input to the EEPROM and the output level of the EEPROM reaches a predetermined value. By the time the number of bits of address data input to the EEPROM is counted, the storage capacity of the EEPROM can be automatically determined,
The access sequence can be determined by using the result of the determination.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing functional blocks of an embodiment of an EEPROM storage capacity determination device according to the present invention.

FIG. 2 is a timing chart showing signal waveforms of signals transmitted and received between each functional block shown in FIG. 1 and an EEPROM.

FIG. 3 is a flowchart showing an operation of the embodiment shown in FIG. 1;

[Explanation of symbols]

 1 EEPROM storage capacity determination device 2 EEPROM 11 Chip select signal input means 12 Serial data input means 13 Address data input bit number counting means 14 EEPROM output level determination means 15 Address data input bit number storage means 16 Serial clock input means CS chip Select signal DI Serial data SK Serial clock

Claims (5)

[Claims] 1. A chip select signal input means for inputting a chip select signal for making an EEPROM accessible to the EEPROM, a read command for setting the EEPROM in a data read mode, and address data of a predetermined number of bits. Serial data input means for inputting serial data to the EEPROM; address data input bit number counting means for counting the number of input bits of address data input to the EEPROM by the serial data input means; and monitoring the output level of the EEPROM And a stop signal for stopping the counting operation of the address data input bit number counting means when the output level takes a predetermined value.
EE comprising OM output level determination means
PROM storage capacity determination device. 2. An EEPROM storage capacity determining device according to claim 1, further comprising address data input bit number storage means for holding a count value counted by said address data input bit number counting means. 3. The method according to claim 1, wherein a serial clock is generated, and the generated serial clock is transmitted to the EE.
An EEPROM storage capacity judging device further comprising a serial clock input means for inputting data to a PROM. 4. A chip select signal inputting step of inputting a chip select signal for making the EEPROM accessible to the EEPROM, a read command for setting the EEPROM in a data read mode, and address data of a predetermined number of bits. A serial data input step of inputting serial data to the EEPROM, an address data input bit number counting step of counting the number of input bits of address data input to the EEPROM in the serial data input step, and monitoring an output level of the EEPROM An EEPROM output level determining step of stopping the operation of counting the number of address data input bits when the output level takes a predetermined value. 5. The method according to claim 4, further comprising the step of storing an address data input bit number storing a count value counted in the address data input bit number counting step.