JP2001337914A - Low-speed device access control method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate high-precision access timing for a relatively low-speed access speed device with a relatively simple hardware configuration at a low cost. SOLUTION: A predetermined wait time is set in a specific address region by the setting of the internal weight generator of CPU 101 prior to the access to the low-speed device 104. During the access to the low-speed device, the control signals of the device 104 are written in sequence to a data latch 105 latching the data forming the control signals of the device arranged at the front stage of the low-speed device. The time for writing to the data latch 105 is secured at high precision by the dummy access to the specific address region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an access control method and apparatus which can be widely used for electronic equipment utilizing a computer system.

[0002]

2. Description of the Related Art Conventionally, in order to improve the processing performance of the entire system, a CPU (Central Processing Unit) having a high processing capability
A system centered on is constructed. Accompanying this, the access speed of memories and I / O devices has also become faster.

However, even in such a system having a high processing performance, when considering the cost of the entire hardware, a memory and an I / O device having a low access speed are used for parts that do not require high speed. Low-speed devices). On the other hand, CPU with high processing capacity
From the viewpoint, the access cycle of the low-speed device is CP
It is several times slower than the U access cycle. For this reason, a method of increasing the hardware such as a counter to generate an access timing for controlling a low-speed device, using a general-purpose timer LSI, or combining a CPU instruction and generating timing by software is known. Generally done.

[0004]

However, in the prior art for adding hardware as described above, the prior art
Since the access timing of the low-speed device is generated from the access timing of the PU, a multi-stage counter or the like is required, and the circuit configuration becomes complicated and expensive from the viewpoints of cost, installation area, power consumption, heat generation and the like.

Further, even when the access timing of a low-speed device is generated using a general-purpose timer LSI, the circuit configuration is expensive.

Further, when the access timing is generated by software by combining CPU instructions, the timing is determined by the required execution time of the instruction, so that the accuracy is not good. This is because the execution time of an instruction varies depending on various factors. In particular, in a system having a cache memory, the execution time can vary greatly depending on any cache hit.

Conventionally, there is also known a CPU having a built-in wait generator capable of setting a desired wait time to read / write the memory. But,
The range of wait time that can be set to this wait generator is limited, so that it is not possible to set a wait time longer than the limit, and it is difficult to use it directly for devices that handle addresses and data serially. there were.

The present invention solves such a problem of the prior art. By using a relatively simple hardware configuration, an inexpensive and highly accurate access timing can be provided for a device having a relatively low access speed. It is intended to be able to generate.

[0009]

A low-speed device access control method according to the present invention is an access control method for accessing a device having a relatively low access speed by a CPU, wherein the CPU has an internal weight generator as the CPU. Data wait means for setting a predetermined wait time in a specific address area by setting the wait generator, and for latching data constituting a control signal of the low-speed device at a stage preceding the low-speed device; When a device is accessed, a control signal of the device is sequentially written to the data latch unit, and a time interval between writing to the data latch unit is secured by accessing an area mapped by the weight generator by address setting. Specially To.

With this configuration, it is possible to generate inexpensive and highly accurate access timing for a device having a relatively low access speed with a relatively simple hardware configuration.

A low-speed device access control device for implementing this method includes a CPU having an internal wait generator, a device having an access speed sufficiently lower than the operation speed of the CPU, and a preceding stage of the low-speed device. Data latch means for outputting a control signal of the device, data buffer means for temporarily storing data to be written to or read from the low-speed device, and the data latch means and the data buffer under the control of the CPU. Control logic means for controlling the means, wherein when accessing the low-speed device, the CPU sequentially writes a control signal of the device to the data latch means, and performs an address-mapped area by setting the wait generator. By accessing Characterized in that to ensure the time interval of writing to the serial data latch means.

[0012] Preferably, the CPU accesses the data buffer means at the time of continuous data writing to the low-speed device via the control logic means to determine whether next writing to the low-speed device is possible. Watch out. Thus, in the continuous data writing, the next data writing start timing subsequent to one data writing can be advanced.

More specifically, the CPU supplies a control command, a clock and an address to the low-speed device in a bit serial manner, and reads and writes data in a bit serial manner through the control logic and data latch means. Before and after the writing of the control command, the clock, and the bit value of the address, the address area of a predetermined wait time to which the address is mapped by the setting of the wait generator is accessed.

The control signal supplied to the low-speed device via the data latch means includes, for example, at least a chip select signal, a clock signal and an address signal.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a low-speed device access control device according to an embodiment of the present invention. The CPU (Central Processing Unit) 101 executes processing in accordance with instructions (instructions) stored in a program code ROM (Read Only Memory, Read Only Memory) 103. The control ASIC (ASIC: control logic means) 102 includes a ROM 103, an EE
Upon receiving an access request to the PROM 104 (electrically erasable programmable ROM) or the like, it controls a control signal to each device to execute the request. The low-speed device in this embodiment is an EEPROM
104.

The control ASIC 102 and the CPU 101
DRS (address) [a31: 2], ADS (address stro
be), BLAST (burst last), PCLK (process clo
ck), W / R (write / read), and DATA [d31: 0]. Note that [a3
1: 2] is a total of 30 signals (30 bits) from 2 to 31, and [d31: 0] is 0.
To 32 in total (32 bits). Hereinafter, the same description is used to indicate a bus width or a specific signal line.

ADRS [a31: 2] is a 30-bit address bus, and DATA [d31: O] is a 32-bit data bus, which are used for transmitting addresses and data, respectively. The ADS signal is a signal notifying that a CPU cycle has started. The BLAST signal is a signal notifying the end of the CPU cycle. Usually BLAST
When the signal becomes low (active), the external device can know that the CPU 101 has completed the access. W
The / R signal is active low when the CPU 101 is in a read cycle operation, and is active high when the CPU 101 is in a write operation. The PCLK signal is a system clock, and read data on the DATA bus is captured at the rising edge of PCLK.

The ROM 103 stores instructions to be executed by the CPU 101 and a minimum number of data structures necessary for initializing the system. RO
If the access speed of M103 matches the access cycle of CPU 101, the processing performance of the entire system is improved.

In this embodiment, as shown in FIG.
The address space 20 of the PU 101 is 0000 0000
To FFFF to FFFF, and the space is divided into 256 Mbyte regions (Regions).
The area is divided into six, and the attribute of each area is stored in the memory area configuration table 30.
Table entry 32 (memory area configuration register MC
ON0 to MCON15).

FIG. 3 shows the internal structure of each table entry 32.
It is shown enlarged. The relevant parts in the present embodiment are 5 bits of bits 3-7 and 5 bits of bits 12-16. The number of read waits and the number of write waits from 0 to 31 clocks can be set, respectively. it can.

Returning to FIG. 1, signals for controlling the chip select (RCS) and the output enable (ROE) of the ROM 103 are directly supplied from the control ASIC 102, and the address (ADRS) and data (DATA) are directly supplied from the CPU 101. .

The EEPROM 104 stores system information and the like.
, And various information is written and read in places where there is not much real-time property. Therefore, there is no need to increase the access speed, and the device is usually a low-speed device.

The data latch (DLATCH) 105 is E
This is a latch circuit that outputs a control signal for performing a read operation and a write operation to the EPROM 104. The data is C
A control signal DLATCH directly supplied from the PU 101 and for performing a latch operation is supplied from the control ASIC.
DATA [d at the rising edge of the DLATCH signal
2: 0] are output as CS, SK, and DI signals, respectively, and the output state is maintained until the next rise of the DLATCH signal. The read data buffer (DBUFFER) 106 controls the control ASIC 10
While the DOE signal from 2 is low (while asserted low), it outputs DO data on the DATA bus.

When writing data to the EEPROM 104, the DLATCH 105 controls the CPU 101 and the control A
In response to the access request from SIC102,
To set the CS signal of the ROM 104 to high, the corresponding d2 bit of the data bus is set to 1 and DLATCH1
05 is performed. Next, dummy write or read is performed for the address space set by MCON0, and a CS setup time is secured. This time is CP
It is generated accurately by the weight generator hardware inside U. Next, in order to set data to be written in the EEPROM 104, 1 or 0 is set to the d1 bit of the data bus, a write operation is performed on the DLATCH 105, and a dummy write or read is performed on the address space set by the MCON1. Perform DI setup time. Next, in order to make SK high, d0 bit of the data bus is set to 1 and DLATCH1 is set.
A write operation is performed on the address space set by MCON0, and then a dummy write or read is performed on the address space set by MCON0 to secure a DI hold time. By repeating such a sequence 25 times in this embodiment,
16-bit data is written. The details are once for writing the start bit, twice for writing the 2-bit write command, and 6 times for writing the 6-bit address.
16 times for writing 16-bit data, a total of 25 times. This situation is shown in the timing chart of FIG.

In order to write the next 16 bits, MC
Dummy write or read is performed to the address space set in ON1, and a low time of the CS signal is secured. Next, 1 is set to the d2 bit of the data bus to make the CS signal high, and a write operation is performed on the DLATCH 105. Next, to determine whether writing is possible, DO
CPU1 to read the status output to
01, a read request is issued from the control ASIC 102 to the DBUFFER 106 by the DOE signal. At that time, in order to secure the output confirmation time, the cycle MCON0
Dummy write or read is performed to the address space set in the above, and while the DOE signal is low, the status information is DO
The signal is output to the d0 bit of the data bus.
If the d0 bit is low, the write is being executed, and if it is high, the next write is waiting. Data is written in the above sequence flow. RE like this
The ADY / BUSY sense operation will be described later in detail with a specific example.

When reading data from the EEPROM 104, the DLATCH 105 is controlled by the CPU 101 and the control AS.
In response to the access request from the IC 102, first, the d2 bit of the data bus is set to 1 to make the CS signal high, and a write operation is performed on the DLATCH 105.
Next, dummy write or read is performed for the address space set by MCON0, and a CS setup time is secured. Next, in order to make the SK signal high, d0 of the data bus is used.
The bit is set to 1, a write operation is performed on the DLATCH 105, and then a dummy write or read is performed on the address space set by the MCON1, thereby securing a data output delay time. Next, to read the data,
PU101, control ASIC102 to DBBUFFER1
In response to the DOE signal 06, a read request is issued.
While the DOE signal is low, data is output to the d0 bit of the data bus through the DO signal, and the data is read at the read timing of the CPU 101. Data is read in the above sequence flow. By repeating this sequence 25 times, 16-bit data is read. The breakdown is once for writing the start bit,
Two times for writing a bit read command, six times for writing a 6-bit address, and sixteen times for reading 16-bit data, for a total of 25 times. This is shown in the timing diagram of FIG.

As described above, according to the embodiment of the present invention, a very simple hardware configuration allows a low-speed device, that is, the EEPROM 104 in this case,
ATCH 105, DBUFFER 106, and memory area configuration registers (MCON0-MC
By using the weight generator by ON15),
Access timing can be generated.

Hereinafter, the present embodiment will be described more specifically.

FIG. 7 shows an example of the specification data of the EEPRO 104. FIG. 8 shows a waveform portion indicated by each parameter.

Now, the RE in the area configuration table 20 shown in FIG.
GlON5 (address range 5000000-5FFF
Assume that a port address for activating the DLATCH signal and the DOE signal is assigned to (FFFF). D
The LATCH signal port address is the control ASIC 102
Is decoded to 5000 0000H, and CS, SK, and DI bits are assigned to DATA for d2, d0, and d1, respectively. The DOE signal port address is decoded to 5000 0001H by the control ASIC 102, and d0 bit is allocated to DATA. The timing time of the EEPROM 104 (FIG. 7)
CS setup time tcss, data setup time tds, clock pulse width tskh, tskl, C
S hold time tcsh, CS deselect time tcd
The dummy read area 1 which is an area for securing the s, 1 data output delay time tpd1) is set to REGION6 (address range 60000000-6FFFFFFF), and the dummy read area 2 is set to REGION7 (address range 70000000-7FFFFFFF). I do. Area table entry 3 of ENTRY6 in FIG.
2 Nrad bits, and 8 clocks in the dummy read area 1 (CPU operation clock is 33 MHz, so PCL
One clock of K is about 30 ns and 30 * 9 = 270 ns)
Set the wait time of. Similarly, 13 clocks (similarly, 30 * 1) are stored in the dummy read area 2 of ENTRY7.
4 = 420 ns). Thus, the timing time of the EEPROM 104 is created.

Here, an outline of the operation of the CPU will be described.

FIG. 11 shows the basic operation timing of the CPU, and shows the read / write operation when there is no wait state (the setting of N * ad, N * dd, Nxda of the weight generator is 0). FIG.

First, in an A (address) cycle, an address and a control signal are output to each bus, a read operation or a write data output operation in a D (data) cycle is performed, and then the bus cycle is terminated. Since the CPU clock PCLK is 33 MHz, 2PCLK * 30
The bus cycle is completed when ns = 60 ns.

FIGS. 12 and 13 are timing charts at the time of write and read operations, respectively, when the wait state includes three clocks. Nwad and Nrad of the area configuration table entry at the top of the figure are 3
It can be seen that (binary value 00011) is set.

Next, an outline of the access operation of the EEPROM 104 will be described. The EEPROM 104 has a 64 × 16-bit configuration and is a 1-kbit EEPROM capable of performing serial read and write operations.

FIG. 4 shows the EEPRO according to the present embodiment.
5 is a flowchart at the time of a basic write operation of M104.
FIG. 14 is a timing chart corresponding to the write operation of the EEPROM 104. An outline of the operation will be described with reference to FIGS.

First, the CPU stores the address 5000 000
The CS bit of 00H is written with 1 to make the CS signal H (S1).

Next, in order to secure the tCSS time of the EEPROM 104, the address 600000 of the region 6
00H is dummy read (S2). Next, in order to write data, the DI of address 5000 0000H
Data 0 or 1 is written to the bit (S3).

Again, the address 60000 of region 6
000H is dummy read and t of the EEPROM 104 is read.
The DS time is secured (S4).

Next, S of the address 5000 0000H
Write 1 to the K bit and set the SK signal to H (S
5).

The address 6000 of region 6 again
000H is dummy read and t of the EEPROM 104 is read.
The SKH time is secured (S6).

Next, S of address 5000 0000h
Write 0 to the K bit and set the SK signal to L (S
7).

Again, the address 60000 of region 6
000H is dummy read and t of the EEPROM 104 is read.
The SKL time is secured, and the writing of 1-bit data (start bit, command, data) is completed (S8).

Thus, the start bit, command,
By inserting a dummy access in a predetermined area before and after an address and data write operation, an appropriate wait time can be secured.

FIG. 5 shows an EEPRO according to this embodiment.
5 is a flowchart at the time of a read operation of M104. FIG.
FIG. 5 is a timing chart corresponding to the read operation.
The operation outline of FIGS. 5 and 15 will be described.

After setting the start bit, the read command, and the read address (S9), the address 500000
The SK signal is set to H by writing 1 to the SK bit of 0H (S10). Next is the region address 7000
000H is dummy read and t of the EEPROM 104 is read.
PD1 time is secured (S11). Next, in order to read data, the DOE port of the address 50000001H is read (S12). CPU is CPU in D cycle
The data of the EEPROM 104 coming from the bus d0 is read (S13). After that, 5000 of addresses
By writing 0 to the SK bit of 0000H, the SK signal is set to L (S14), and the address 6000 of the region 6 is set.
0000H is dummy read and the EEPROM 104
TSKL time is secured (S15), and 1-bit data reading is completed.

FIG. 6 shows an EEPRO according to this embodiment.
R before the next write operation after the write operation of M104
6 is a flowchart of an EASY / BUSY sensing operation. FIG. 16 is a timing chart at that time. Figure 6
The operation outline of FIG. 16 will be described.

After setting the start bit, the read command, and the read address (S16), the address 5000 00
0 is written to the CS bit of 00H, and the CS signal is set to L (S17). Next, the address 6000 of region 6
0000H is dummy read and the EEPROM 104
TCDS time is secured (S18). Then address 50
Write 1 to the CS bit of 00 0000H,
The signal is set to H (S19). Next, address 5 is used to check whether the next block can be written.
000 0001H DOE port is read (S2
0). At this time, if d0 is 0, writing is not possible, so the CPU is in a waiting state (the CPU polls the d0 bit) until d0 becomes 1. Thereafter, if it is confirmed by polling that d0 is 1 (S21), the state in which the next writing can be performed is established.

Although the preferred embodiment of the present invention has been described above, various modifications and changes are possible. For example,
The specific various numerical values given in the above description are merely examples for explanation, and the present invention is not limited to them.

[0051]

According to the present invention, a high-precision and inexpensive low-speed device access control method and apparatus can be obtained with a simple hardware configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a low-speed device access control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an address space and a memory area configuration table of a CPU according to the embodiment of the present invention.

FIG. 3 is an enlarged view showing an internal configuration of each table entry of the memory area configuration table shown in FIG. 2;

FIG. 4 is a flowchart at the time of a basic write operation of the EEPROM according to the embodiment of the present invention.

FIG. 5 is a flowchart at the time of a read operation of the EEPROM according to the embodiment of the present invention.

FIG. 6 illustrates a READY / B signal after an EEPROM write operation and before a next write operation according to the embodiment of the present invention;
6 is a flowchart of a USY sensing operation.

FIG. 7 is a diagram showing specification data of an EEPROM according to the embodiment of the present invention.

8 is a diagram showing a waveform portion indicating each parameter of the specification data of FIG. 7;

FIG. 9 is a diagram showing a read timing of the EEPROM according to the embodiment of the present invention.

FIG. 10 is a diagram showing data write timing of the EEPROM in the embodiment of the present invention.

FIG. 11 is a timing chart showing a read / write operation when there is no wait state, which is a basic operation timing of the CPU.

FIG. 12 is a timing chart at the time of a write operation when the wait state of the CPU includes three clocks;

FIG. 13 is a timing chart at the time of a read operation when the wait state of the CPU includes three clocks.

14 is a timing chart corresponding to the write operation of the EEPROM corresponding to FIG. 4;

FIG. 15 is a timing chart corresponding to the read operation of the EEPROM corresponding to FIG. 5;

FIG. 16 shows the READY /
FIG. 7 is a timing chart corresponding to a BUSY sensing operation.

[Explanation of symbols]

101 ... CPU 102 ... Control ASIC 103 ... Program Code ROM 104 ... EEPROM 105 ... Data Latch (Data Latch Means) 106 ... Read Data Buffer (Data Buffer Means)

Claims (5)

[Claims] 1. An access control method for accessing a device having a relatively low access speed by a CPU, wherein the CPU has an internal weight generator as the CPU.
PU is employed, a predetermined wait time is set in a specific address area by setting the weight generator, and data latch means for latching data constituting a control signal of the low-speed device is provided at a stage preceding the low-speed device. When a low-speed device is accessed, a control signal of the device is sequentially written to the data latch unit, and a time interval between writing to the data latch unit is secured by accessing an area mapped by address setting by the wait generator. A low-speed device access control method. 2. A CPU having an internal weight generator.
A device whose access speed is sufficiently low compared to the operation speed of the CPU; a data latch unit which is arranged in front of the low-speed device and outputs a control signal of the device; and writes or reads to or from the low-speed device Data buffer means for temporarily storing data, and control logic means for controlling the data latch means and the data buffer means under the control of the CPU, wherein the CPU, when accessing the low-speed device,
The control signal of the device is sequentially written to the data latch means, and a time interval between writing to the data latch means is secured by accessing an area mapped by the weight generator by address setting. Low-speed device access control device. 3. The CPU according to claim 2, wherein said CPU accesses said data buffer means during continuous data writing to said low-speed device via said control logic means, and determines whether next writing to said low-speed device is possible. 3. The low-speed device access control device according to claim 2, wherein the low-speed device access control device monitors 4. The CPU supplies a control command, a clock and an address to the low-speed device in a bit serial manner, and reads and writes data in a bit serial manner, via the control logic and data latch means.
3. The method according to claim 2, wherein before and after the writing of the bit values of the control command, the clock and the address, an address area of a predetermined wait time, which is address-mapped by the setting of the wait generator, is accessed.
Or a low-speed device access control device according to 3. 5. The low-speed device access control device according to claim 3, wherein the control signal supplied to said low-speed device via said data latch means includes at least a chip select signal, a clock signal and an address signal.