JP2001290755A - Method for accessing eeprom and electronic device having eeprom - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read and write data from/to a serial EEPROM by using a serial communication function included in a microcomputer. SOLUTION: The serial clock output terminal 27 of the microcomputer 2, the serial data transmitting terminal 28 and the serial data receiving terminal 29 are connected to the clock input terminal 14 of the serial EEPROM 1, the data input terminal 12 and the data output terminal 11 respectively, and one output port 30 of the microcomputer 2 is also connected to the chip select terminal 13 of the EEPROM 1. A chip select signal is outputted from the port 30, and a signal composed of a plurality of blocks is also transmitted from the serial data output terminal 28 by dividing the start bit, an operation code and address data into a plurality of blocks so as to be the number of unit bits of serial communication with the least significant digit of the address data as reference and including '0' in front of a start bit about a block including the start bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for accessing a serial input / output type EEPROM and an electronic device having the EEPROM.

[0002]

2. Description of the Related Art EEPROM (electrically erasable)
programmable ROM: Electrically erasable and writable ROM)
Is a non-volatile memory that can electrically perform writing and erasing, and is widely used for data backup and the like. EEPROMs include a parallel input / output type for inputting / outputting data in parallel and a serial input / output type for inputting / outputting data serially. When connected to a single-chip microcomputer or the like, the interface load is small. A serial input / output type (serial EEPROM) is often used.

FIG. 3 shows such a serial EEPROM.
FIG. 3 is a diagram showing an example of the internal configuration of the device. As shown in this figure, the serial EEPROM 1 has a data output terminal 11,
It has a data input terminal 12, a chip select terminal 13, a clock input terminal 14, a power supply terminal 15, and a ground terminal 16. Reference numeral 21 denotes input data (DI) from the data input terminal 12, a chip select signal (CS) from the chip select terminal 13, and a clock input terminal 1.
4 includes an instruction decoding unit for receiving an instruction (command) included in the input data DI and a timing circuit for generating an operation timing signal based on the serial clock SK. A control unit 22 is an address register for storing address data supplied via the control unit 21; 23 is an address decoder;
Denotes a memory array, 25 reads data from a cell corresponding to the address data in the memory array 24,
Alternatively, a read / write circuit for writing data, 26 is a data register for storing data read from the memory array 24 or data to be written to the memory array 24, and 27 is a read / write circuit for serially outputting read data from the data register 26. This is a buffer circuit that outputs to the data output terminal 11.

[0004] The serial EEPROM configured as described above.
The operation of M will be described with reference to FIG. Here, FIG. 4A shows an example of an instruction set of the EEPROM, and FIG. 4B shows a timing chart during a write operation. Here, this EEP
The description will be made assuming that the ROM has a configuration of 64 words × 16 bits. As shown in FIG.
The PROM instruction is composed of a 1-bit start bit, a 2-bit opcode field, and a 6-bit address field. In the case of a write operation, these are followed by a 16-bit data field. Here, the start bit is set to logic "1" in common for all instructions. When the operation code field is "10", "11", or "01", reading, erasing, or writing is performed on the word specified by the address data A5 to A0 in the address field, respectively. Further, when the operation code field is "00", processing of write enable, write inhibit, erase all addresses, or write data to all addresses is performed according to the value of the upper two bits of the address field.

[0005] Regarding the operation of such an EEPROM,
A description will be given of a write operation as an example. As shown in FIG. 4B, first, the chip select signal CS (chip select terminal 14) is started up, and during execution of the instruction, this CS is held at a high level. Then, the serial clock SK is supplied to the clock input terminal 14.
Thus, the data DI input from the data input terminal 12 is taken in at the rising edge of the serial clock SK. Then, via the data input terminal 12, a start bit "1", a 2-bit operation code (in this case, "01"), a 6-bit write address (A5 to A0), and 16-bit write data (D15
To D0) are sequentially input. Here, the control unit 21 recognizes “1” detected first at the time of capturing the data DI as a start bit, and sequentially captures the captured data as operation code, address data, and data field data. handle. Note that all data of “0” before the first “1” is ignored.

After the transfer of the instruction and the write data is completed, the chip select CS is set to the low level for a predetermined period. From the fall of CS, the EEPROM 1 enters an automatic programming cycle, and writes data (D15 to D0) to the address specified by the address data A5 to A0. At this time, the internal state of the EEPROM 1 can be known by referring to the output DO of the data output terminal 11. That is, a busy / ready signal is output from the data output terminal 11 after the CS is set to a low level for a predetermined period and then to a high level.

Although FIG. 4B shows a timing chart at the time of the write operation, the same operation is performed at the time of the read operation. That is, in the same manner as described above, CS is started, the serial clock SK is supplied,
It supplies data DI consisting of a start bit, an operation code ("10"), and address data. In this case, the data output terminal 12 outputs a one-bit dummy bit "0" from the rising edge of the serial clock SK for reading the address of A0 in the address field, and subsequently reads out the read data from the designated address. D15-D
0 is serially output sequentially. In this case, the serial clock SK is supplied until the transfer of the output data DO from the data output terminal 12 is completed. Similarly, for other instructions, the chip select CS, the serial clock SK, and the instruction data are supplied.

[0008]

As described above, serial EEPROMs are widely used for backing up data in systems using microcomputers or electronic devices. However, as described above, the instruction for the serial EEPROM is composed of a start bit, an operation code, and a write address, and at the time of a write operation, write data further follows. The start bit is 1 bit, the operation code is 2 bits, and the write address is, for example, 6 bits in the case of 64 words, and the write data is 16 bits. Access to the EEPROM cannot be performed.

Normally, a microcomputer or the like is equipped with a serial communication interface so that serial communication can be performed every predetermined number of bits (for example, 8 bits, 16 bits, etc.). However, for the reasons described above, even in a system using a microcomputer equipped with a serial communication function, the function is not used, and the output port of the microcomputer is set to high level / low level by dedicated software. The serial EEPROM is accessed by synchronizing with the serial clock SK and setting the transmission output port to a high level / low level in accordance with the instruction or write data in synchronization with the serial clock SK.

[0010] For this reason, there has been a problem that software is complicated and a program capacity is increased. Further, the communication speed is fixed, and communication with the EEPROM cannot be performed at a high speed in view of the processing speed of the microcomputer. In addition, EEPRO using a dedicated program
Since M is accessed, there is a problem that other processing cannot be performed during communication with the EEPROM.

Therefore, the present invention provides an EEPROM capable of accessing an EEPROM using a serial communication interface normally mounted on a microcomputer or the like.
It is an object to provide an EPROM access method and an electronic device having an EEPROM.

[0012]

In order to achieve the above object, an EEPROM access method according to the present invention has a chip select terminal, a data input terminal, a data output terminal, and a clock input terminal. Serial input / output EEP whose instruction is determined by the operation code and address data input to
A method for accessing a ROM, comprising a serial data transmission terminal, a serial data reception terminal, and a serial clock output terminal for outputting a clock signal, and a serial communication interface for performing serial communication in units of a predetermined number of bits in synchronization with the clock signal. An output port capable of outputting 1-bit data, wherein the output port and the chip select terminal of the EEPROM, the serial data transmission terminal and the data input terminal of the EEPROM, the serial data reception terminal and the EEPROM
Data output terminal, and the serial clock output terminal and the clock input terminal of the EEPROM are connected to each other, a chip select signal is output from the output port, and a bit string including the start bit, the operation code, and the address data is output. A plurality of blocks divided by the predetermined number of bits based on the least significant digit of the address data and including the start bit, a bit having a logical value of 0 is included before the start bit. The plurality of blocks are output from the serial data transmission terminal.

An electronic device having an EEPROM according to the present invention is an electronic device having a microcomputer having a serial communication interface and a serial input / output type EEPROM. A terminal and a serial data receiving terminal are connected to a clock input terminal, a data input terminal and a data transmitting terminal of the serial input / output type EEPROM, respectively, and an output port of the microcomputer is connected to a chip select terminal of the serial input / output type EEPROM. And outputs a chip select signal from the output port and the serial input / output type EEPROM through the serial clock output terminal and the serial data transmission terminal. Is obtained so as to supply the instruction data for.

[0014]

FIG. 1 is a block diagram showing a main configuration of an electronic device having a microcomputer to which an EEPROM access method according to the present invention is applied. 1, reference numeral 1 denotes a serial EE similar to that shown in FIG.
It is a PROM and has the above-mentioned data output terminal 11, data input terminal 12, chip select terminal 13, and clock input terminal 14. Reference numeral 2 denotes a microcomputer, as shown in FIG.
Various components such as an M, a timer, an input / output port, and a serial communication interface 20 are provided. The serial communication interface 20 includes therein a transmission / reception control circuit 21, a timing circuit 22, a transmission register 23, a transmission shift register 24, a reception register 2
5, a serial clock output terminal 27 for outputting a clock signal (SCLK) from the timing circuit 22, a serial data transmission terminal 28 for outputting a serial transmission signal (Sout),
It has a serial data receiving terminal 29 to which a serial signal (Sin) is input. An output port 30 is one of general-purpose input / output ports. The microcomputer 2 has a processing bit width of 8 bits, 1 bit,
Although there are various types such as 6 bits, here, an explanation will be given taking an 8 bit microcomputer as an example.

As shown in FIG.
In the ROM access method, the output port 30 of the microcomputer 2 and the chip select terminal 13 of the EEPROM 1, the serial clock output terminal 27 of the serial communication interface and the clock input terminal 14 of the EEPROM 1, the serial data transmission terminal 28 and the EEPROM 1
And the serial data receiving terminal 29 and the data output terminal 11 of the EEPROM 1 are connected to each other. As described above, in the present invention, each terminal of the serial communication interface 20 mounted on the microcomputer is used for connection with the EEPROM 1.

The serial communication interface 20 normally has a function of performing serial transmission in two modes, an asynchronous mode and a clock synchronous mode. In this case, the serial communication interface 20 has a function of performing clock synchronous serial communication. Make it work. Here, the transmission register 23 and the reception register 25 are readable and writable directly from the CPU.
When transmitting a signal using the serial communication interface 20, the PU performs an initial setting for the transmission / reception control circuit 21 and the timing circuit 22, and then stores transmission data in the transmission register 23 to perform the transmission / reception. A transmission start instruction is sent to the control circuit 21. In response, the transmission / reception control circuit 21 sets the transmission register 23
Is transferred in parallel to the transmission shift register 24,
The contents of the transmission shift register 24 are sequentially read out according to the timing signal generated by the timing circuit 22 and output from the serial data transmission terminal 28. Also,
After the data transfer from the transmission register 23 to the transmission shift register 24 is completed, the transmission / reception control circuit 21 generates a transmission data empty interrupt to the CPU. Further, the timing signal generated by the timing circuit 22 is output from the serial clock output terminal 27 to the outside. Note that when the transmission data empty interrupt occurs, the CPU writes data to be transmitted subsequently to the transmission register, so that serial transmission can be continuously performed. Similarly, at the time of reception, the reception operation is started according to the instruction of the CPU, and the reception data is sequentially input to the reception shift register 26 in synchronization with the timing signal, and when the data fetch into the reception shift register 26 is completed, The received data is transferred to the reception register 25. When the data transfer to the reception register 25 is completed, a reception data full interrupt is generated for the CPU. The CPU detects these interrupts and determines whether to transmit or receive a further signal or end the transmission / reception processing. As described above, since the serial communication interface 20 autonomously executes the serial communication function, the CPU can perform other processing until an interrupt occurs.

A method of accessing a serial EEPROM connected by using the serial communication interface as described above will be described by taking data writing as an example. Here, the EEPROM 1 is 64
It is assumed that the word has a configuration of 16 bits. FIG.
5 is a timing chart showing the timing of a write operation to the EEPROM 1. Before accessing the EEPROM 1, data to be transmitted to the EEPROM 1 is first prepared in a work area or the like in the RAM. As described above, the instruction for the EEPROM includes a start bit of 1 bit, an operation code of 2 bits, and a total of 9 bits of the address field of 6 bits.
Bits, followed by a 16-bit data field. Therefore, the instruction is divided into 8-bit blocks based on the least significant bit A0 of the address field. For a block including a start bit, “0” is added before the start bit, and “00000001” is added. `` 01A5 A4 A3 A2 A1 A
Two 8-bit data "0" are prepared in the work area. That is, the first to seventh bits of the eight bits of the first transmission data are all set to “0”, and the eighth bit is set to “1” (start bit). Then, the operation code (“01” in the case of writing) is stored in the first and second bits of the second transmission data, and the address data A5 to A0 are stored in six bits of the third to eighth bits. I do. Also, 16-bit data (D15-D8, D7-D8) of the data field is used as third and fourth transmission data.
Prepare 0).

Next, "1" is output from the output port 30 and input to the chip select terminal 13 of the EEPROM 1. Then, the transmission data prepared as described above is transmitted serially by 8 bits at a time via the serial communication interface 20. That is, first, the first transmission data "00000001" is written into the transmission register 23, and the transmission / reception control circuit 21 is instructed to start transmission. Thus, the first transmission data stored in the transmission register 23 is transferred to the transmission shift register 24, and the transmission shift register 24 is synchronized with the serial clock generated by the timing circuit 22.
From the serial data output terminal 28. At the same time, the serial clock generated by the timing circuit 22 is output via the serial clock output terminal 27. The transmission register 2
When the transfer of the transmission data from 3 to the transmission shift register 24 is completed, a transmission data empty interrupt is generated. The CPU sequentially writes subsequent transmission data (the second transmission data, the third transmission data, and the fourth transmission data) into the transmission register 23 in the interrupt processing for the transmission data empty interrupt. As a result, the fourth transmission data is transmitted continuously.

In the serial EEPROM 1, as described above, the first transmission data input from the data input terminal 12 is fetched based on the serial clock SK input via the clock input terminal 14. . Here, the control unit 21 of the EEPROM 1 captures the first transmission data, but as described above,
All data of "0" are ignored, and the data of "1" transmitted in the eighth bit is recognized as a start code.
Then, the first and second bits of the subsequently input second transmission data are used as the operation code, and the third to eighth bits are used as address data.
Each is recognized and input to the control unit 21. further,
The third transmission data and the fourth transmission data are stored in the data register 26 as write data. Then, data of the third to eighth bits of the second transmission data is transferred to the address register 22, and the data stored in the data register 26 is written to an address specified by the address data.

As described above, in the present invention, the serial EEPR is added by adding "0" before the start bit so that the number of bits becomes a unit of serial communication.
The OM can be accessed via a serial communication interface. In the above description, the case of writing has been described. However, the case of reading and other instructions is exactly the same, and a detailed description thereof will be omitted. According to the method of the present invention, it is possible to access the serial EEPROM using the serial communication interface 20. Therefore, the program for accessing the EEPROM can be simplified, and the program capacity can be reduced. Also, EEP
Communication with the ROM can be performed at the speed of the serial communication interface. Further, since it is only necessary to transfer transmission data by interruption from the serial communication interface, other processing can be executed even during access to the EEPROM.

In the above description, the serial communication is performed after the chip select CS is activated with the output port 30 set to "1".
Since the PROM 1 ignores all “0” s before the “1” which is first taken in after the chip select CS becomes high level, the timing of setting the output port 30 to “1” is critical. The timing may be any timing before the start bit (the eighth bit in the first transmission) is transmitted.

In the above embodiment, the EEP
Although the case where the ROM has a configuration of 64 words × 16 bits has been described as an example, the present invention is not limited to this.
Other bit configurations such as 8, 128 × 16, 256 × 16, 512 × 16 can be similarly applied. For example, in the case of a structure of 128 words × 8 bits, the address field is 7 bits A6 to A0. In this case, the 7th bit of the first transmitted 8 bit data is used. And the first bit of the operation code is stored in the eighth bit,
All other bits may be set to “0”.

Further, in the above description, a case has been described in which an 8-bit microcomputer is used to perform serial data communication in 8-bit units via the serial communication interface. However, the present invention is not limited to this. The present invention can be similarly applied to a case where a microcomputer having a different number of bits such as a 16-bit microcomputer is used. That is, in this case, it is sufficient to make the block every 16 bits instead of the block every 8 bits as described above. Furthermore, in the above-described embodiment, a case has been described in which a microcomputer is used to connect a serial communication interface built in the microcomputer to a serial EEPROM, but the present invention is not limited to this. Can be similarly applied to a case where the device is connected via a serial communication interface circuit.

[0024]

As described above, the EEPR of the present invention
According to the OM access method and the electronic device having the EEPROM, it is possible to access the serial EEPROM using the serial communication function normally mounted on the microcomputer, and a program for controlling the access to the serial EEPROM is specially prepared. , Data can be easily read and written to the serial EEPROM. Further, since the serial communication function normally mounted on the microcomputer is used, it is possible to use an interrupt from the serial communication function, so that other processing can be executed even while accessing the EEPROM. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing a configuration example of an electronic device to which an access method to an EEPROM of the present invention is applied.

FIG. 2 is a timing chart at the time of a write operation in the EEPROM access method of the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a serial EEPROM.

FIG. 4 is a timing chart for explaining a conventional write operation to a serial EEPROM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Serial EEPROM 2 Microcomputer 11 Data input terminal 12 Data output terminal 13 Chip select terminal 14 Clock input terminal 20 Serial communication interface 27 Serial clock output terminal 28 Data transmission terminal 29 Data reception terminal 30 Output port

Claims (2)

[Claims] 1. A chip select terminal, a data input terminal,
An access method for a serial input / output type EEPROM having a data output terminal and a clock input terminal and having an instruction determined by an operation code and address data serially input following a start bit, comprising: a serial data transmission terminal; A serial communication interface that has a receiving terminal and a serial clock output terminal that outputs a clock signal, and performs serial communication in units of a predetermined number of bits in synchronization with the clock signal, and an output port that can output 1-bit data. The output port and the chip select terminal of the EEPROM, the serial data transmission terminal and the data input terminal of the EEPROM, the serial data reception terminal and the
A data output terminal of an EPROM, a serial clock output terminal connected to a clock input terminal of the EEPROM, a chip select signal is output from the output port, and a bit string including the start bit, the operation code, and the address data Are divided into a plurality of blocks each having the predetermined number of bits based on the least significant digit of the address data, and a block including the start bit includes a bit having a logical value of 0 before the start bit. An EEPROM access method, wherein the plurality of blocks are output from the serial data transmission terminal. 2. A microcomputer having a serial communication interface and a serial input / output type EEPROM
An electronic device comprising: a serial clock output terminal, a serial data transmission terminal, and a serial data reception terminal in the serial communication interface, and a clock input terminal, a data input terminal, and a data transmission terminal of the serial input / output type EEPROM, respectively. And the output port of the microcomputer is connected to the serial input / output EEP.
Connected to a chip select terminal of a ROM, outputs a chip select signal from the output port, and outputs the serial input / output type EE through the serial clock output terminal and the serial data transmission terminal.
An electronic device having an EEPROM, wherein instruction data is supplied to a PROM.