JP2009110335A - Semiconductor device and data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for changing communication conditions of a transmitting/receiving circuit in a short time without burdening a central processing unit. <P>SOLUTION: The semiconductor device includes: changing registers 45, 44 for setting other communication condition data, in addition to communication condition setting registers 42, 44 having initial communication conditions set thereto, and adopts a transmitting/receiving control part 20 storing the values of changing registers in the communication condition setting registers to perform communication by detecting the completion of a transmitting state when the central processing unit 3 gives an instruction to change a communication state from transmission to reception or the like in advance. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for changing the setting of communication conditions in a transmission / reception circuit, for example, a technique effective when applied to changing the setting of communication conditions of a UART (Universal Asynchronous Receiver / Transmitter) in a microcomputer for an IC card.

  An IC card microcomputer (also simply referred to as an IC card microcomputer) that performs security processing such as access control using a personal identification number (PIN), encryption processing, and secret key protection converts a serial signal in an asynchronous manner into a parallel signal and vice versa. Some external interface transmission / reception circuits that perform conversion include, for example, a UART. Patent Document 1 is an example of a document that describes an IC card having a UART.

  As IC card microcomputers are required to increase the amount of processing data and to speed up data processing, it is necessary to follow the external interface capability accordingly. Therefore, some IC card microcomputers in which a central processing unit is mounted together with UART make communication conditions such as transfer rate and transfer protocol by UART programmable by register setting by CPU. When changing the communication condition, the central processing unit must read the required communication condition data by memory access and load the read communication condition data into the UART register for each communication condition setting register. Don't be. At this time, after establishing a communication between the IC card and the terminal device at a slow transfer rate, if the IC card supports high speed, the terminal device requests the IC card to change to high speed transfer. If the IC card approves this, then the terminal device starts a high-speed interface. For this reason, the IC card transmits the approval for the request for the high-speed interface operation to the terminal device until the reception by the high-speed interface from the terminal device is started. A register load must be performed. However, there is a limit to speeding up memory access and register loading, and if data is transmitted in the middle, there is a possibility that data cannot be received normally. On the other hand, it is possible to give approval of the communication condition to the terminal device after changing the communication condition. However, if the approval is delayed, the established communication may be canceled or the interface efficiency may be reduced. There is.

Japanese Patent Laid-Open No. 5-342435

  An object of the present invention is to provide a semiconductor device capable of changing communication conditions of a transmission / reception circuit in a short time without imposing a burden on a central processing unit.

  Another object of the present invention is to provide a data processing system capable of changing communication conditions between processors in a short time without placing a burden on a central processing unit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in addition to the communication condition setting register in which the communication condition is initially set, a separate register for changing the communication condition data that can be set is provided, and an instruction to change the communication state from transmission to reception by the central processing unit. Is preliminarily given, a transmission / reception control unit for performing communication by storing the value of the change register in the communication condition setting register by detecting the end of the transmission state is employed.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, communication conditions can be changed in a short time without imposing a burden on the central processing unit.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings that are referred to with parentheses in the outline description of the representative embodiment merely exemplify what is included in the concept of the component to which the reference numeral is attached.

  [1] The semiconductor device (1) includes a central processing unit (3) and a transmission / reception circuit (16) capable of serial transmission / reception processing according to the setting of the central processing unit. The transmission / reception circuit includes a communication condition setting register (42, 44) in which communication conditions are set by the central processing unit, and a change register (in which setting data by the central processing unit can be transferred to the communication condition setting register). 43, 45) and a transmission / reception control unit (20). The transmission / reception control unit stores the change register setting value in the communication condition register by executing the communication by detecting the end of communication due to the previous communication state when switching of the communication state is instructed. Is possible.

  When changing the communication state, the central processing unit sets a change communication condition in the change register in advance, so that when there is an instruction to switch the communication state, the transmission / reception control unit terminates the previous communication state. The communication condition can be changed by performing inter-register transfer in response. Therefore, it is not necessary for the central processing unit to read new communication condition data from a memory or the like and load the read data into a register in synchronization with the timing at which the communication state is switched. Therefore, when switching the communication state, the communication condition can be changed in a short time without imposing a burden on the central processing unit.

  [2] In the semiconductor device according to [1], the communication condition set in the communication condition setting register by the central processing unit is set in the change register in parallel. Therefore, if the central processing unit does not rewrite part or all of the change register, the communication condition that has not been rewritten even if the communication state is switched can be maintained and maintained in the communication state later. Therefore, when the communication state is switched, whether the communication condition is continued or changed, the same control procedure may be adopted except for whether or not the change register is rewritten.

  [3] In the semiconductor device of [1], the communication condition setting register includes, for example, a communication rate setting register (UECR) in which data specifying a communication rate is set, and a communication protocol setting in which data specifying a communication protocol is set Register (UMR). The change register is, for example, a first change register that allows setting data to be transferred to the communication rate setting register, and a second change register that enables setting data to be transferred to the communication protocol setting register.

  [4] In the semiconductor device of [3], the transmission / reception control unit is configured to switch the first communication state when an instruction to switch the communication state from the first communication state to the second communication state is set in the control register by the central processing unit. In response to the end of the communication, the setting value of the first change register is stored in the communication rate setting register, the setting value of the second change register is stored in the communication protocol setting register, and the second communication Enables data communication by status.

  [5] In the semiconductor device of [4], for example, the first communication state is a transmission state, and the second communication state is a reception state.

  [6] In the semiconductor device according to [5], the transmission / reception circuit is, for example, a UART that performs serial transmission / reception processing of a half duplex system to the outside.

  [7] The semiconductor device according to [6], further including a transfer end flag (TEND) that is operated by the transmission / reception control unit to reflect the end of transmission. The transmission / reception control unit stores the set value of the first change register in the communication rate setting register between the time when transmission is detected and the time when transmission end is reflected in the transfer end flag. Processing for storing the set value of the second change register in the communication protocol setting register is performed, and data reception is awaited.

  [8] The semiconductor device according to [4], including a plurality of first change registers (UMARA, UMARb) and a plurality of second change registers (UEARa, UEARb). The transmission / reception control unit selects the first change register and the second change register that store values in the communication rate setting register and the communication protocol setting register when the communication state is switched according to the setting value of the control register. . New communication condition options that can be adopted when switching the communication state are increased.

  [9] The data processing system includes a first data processor (52), a second data processor (1), and a serial signal line (53) connecting them. The second data processor transmits to the first data processor under the first communication condition, and a response to the first communication condition from the first data processor includes a request for changing to the second communication condition. When the communication condition is transmitted to the first data processor with the second communication condition and a response is returned from the first data processor with the second communication condition, the communication condition is The communication condition is changed from the first communication condition to the second communication condition. The serial signal line connects the first data processor and the second data processor and is used for communication under the first communication condition and the second communication condition. The second data processor includes a central processing unit (3) and a transmission / reception circuit (16) capable of serial transmission / reception processing via the serial signal line in accordance with settings of the central processing unit. The transmission / reception circuit includes a communication condition setting register (42, 44) in which communication conditions are set by the central processing unit, and a change register (in which setting data by the central processing unit can be transferred to the communication condition setting register). 43, 45) and a transmission / reception control unit (20). When the transmission / reception control unit is instructed to switch from the transmission state to the reception state, it detects the end of the transmission state, stores the setting value of the change register in the communication condition setting register, and changes to the reception state. Make it possible.

  When changing the communication state from the first data processor to the second data processor, the central processing unit sets a change communication condition in the change register in advance, so that if there is an instruction to switch the communication state, transmission / reception is performed. The communication condition can be changed by the controller performing transfer between registers in response to the end of the previous communication state. Therefore, it is not necessary for the central processing unit to read new communication condition data from a memory or the like and load the read data into a register in synchronization with the timing at which the communication state is switched. Therefore, when switching the communication state, the communication condition can be changed in a short time without imposing a burden on the central processing unit.

  [11] In the data processing system according to item 10, the first data processor is an IC card microcomputer mounted on an IC card (51) or a subscribing identity module card, and the second data processor is an IC card. It is an IC card terminal device (50) to which a card is attached or a processor of a terminal device to which the SIM card is attached. For example, the data processing system is applied to a mobile terminal system such as a mobile phone. The subscribe identity module card is also simply referred to as a SIM® card.

2. Details of Embodiments Embodiments will be further described in detail. Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. Note that members having the same function are denoted by the same reference symbols throughout the drawings for describing the best mode for carrying out the invention, and the repetitive description thereof will be omitted.

<Microcomputer for IC card>
FIG. 2 is a block diagram of an IC card microcomputer (also simply referred to as an IC card microcomputer) which is an example of a semiconductor device according to the present invention. The IC card microcomputer 1 shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique.

  The IC card microcomputer 1 has data input / output terminals IO1, IO2, a clock input terminal CLK, a reset terminal RES, a power supply terminal Vcc, and a ground terminal Vss. DBUS is an internal data bus, and ABUS is an internal address bus. The input / output circuit (IOP) 2 is externally interfaced bit-serially using a 1-bit terminal IO1. A clock pulse generator (CPG) 5 connected to the clock terminal CLK generates an internal clock CK. The central processing unit (CPU) 3 inputs / outputs parallel data to / from the internal data bus DBUS and outputs an address signal to the internal address bus ABUS. A system controller (SYSCNT) 6 controls an internal operation mode such as reset. Internal buses DBUS and ABUS include a mask ROM (MROM) 10, a random access memory (RAM) 11, a nonvolatile memory (EEPROM) 12, a timer (TMR) 13, a random number generator (RNG) 14, and a pseudo random number generator. (PRNG) 15 is connected. In addition, a UART 16 as a transmission / reception circuit that performs anti-duplex serial transmission / reception processing, a remainder multiplication coprocessor (MULP) 17, a CRC coprocessor (CRCP) 18 that generates and checks a CRC (Cyclic Redundancy Code) code, and A DES coprocessor (DESP) 19 that performs encryption / decryption calculation is connected.

  The MROM 10 is used to store an operation program (encryption program, decryption program, interface control program, etc.) and data of the CPU 3. The RAM 11 serves as a work area for the CPU 3 or a temporary storage area for data. The EEPROM 12 is used for storing security data and the like. When an IC card command is supplied to the input / output circuit 2, the CPU 3 decodes it and causes the CPU 3 to execute a processing program necessary for executing the command. When a reset operation is instructed by the reset signal RES, the IC card microcomputer 1 is initialized, and the CPU 3 starts executing instructions from the top address of the program in the MROM 10. The IC card microcomputer 1 is operated in synchronization with the clock signal CLK. The IC card microcomputer 1 may or may not be authenticated by an ISO / IEC 15408 evaluation / certification organization that can be used for electronic payment services.

《UART》
FIG. 1 shows an example of the UART 16. The UART 16 includes a communication control unit (COMCNT) 20, a register circuit (REGC) 40, and synchronization circuits (SYNC) 30 and 31. The communication control unit 20 is operated in synchronization with the external clock CLK, and the register circuit 40 is operated in synchronization with the internal clock CK. The synchronization circuits 30 and 31 synchronize data exchange between the communication control circuit 20 and the register circuit 40. The register circuit 4 is mapped to the address space of the CPU 3 and can be accessed by the CPU 3 via the data bus DBUS.

  The communication control unit 20 includes a communication control logic (COMLOG) 25, a shift register (USR) 21, a CRC register (UCRC) 22, an etu pulse generator (ETUG) 23, and a flag generator (FLGG) 24. The UART 16 is serially connected to the data input / output terminal IO1 via a 1-bit signal line (not shown), and performs half-duplex serial transmission / reception processing. The shift register 21 shifts serial input data from the data input / output terminal IO1, and shifts data out to the data input / output terminal IO1. The CRC register 22 is a register used for the shift input of the CRC code and the shift output of the CRC code. etu (Basic Time Unit) means a transfer time for one bit in bit serial data, and the etu pulse generator 23 defines how many CLK cycles one etu is. That is, 1 etu indicates the time of 1 data (1 bit data) by the number of clocks. The flag generator 24 operates an internal flag described later.

  The register circuit 40 includes a control register (UCR) 41, a mode register (UMR) 42, a first autoload register (UMAR) 43, an ETU count register (UECR) 44, a second autoload register (UEAR) 45, and a status register (UCSR). ) 46 and a data register (UDR) 47.

  The control register (UCR) 41 has a UA bit, an RN_T bit, a T2R bit, an IE bit, and the like. The UA bit controls the state of UART. 0: Stopped state, 1: Operating state (state where transmission / reception operation can be performed). The RN_T bit sets the transmission or reception mode of the UART 16. 0: means reception mode, 1: means transmission mode. The T2R bit is set when the transmission mode is automatically switched to the reception mode with the T = 0 protocol. 0: Automatic switching off from transmission mode to reception mode, 1: Automatic switching on from transmission mode to reception mode. The IE bit is an interrupt enable bit, and sets a UART interrupt request when the status flag TDRE or the like of the status register (UCSR) 46 is set from 0 to 1. 0: Disable UART interrupt request, 1: Enable UART interrupt request. The interrupt request is supplied to the CPU by an interrupt signal UARTIRQ.

  The mode register (UMR) 42 has T bits and the like. The T bit sets the UART 16 data transfer protocol. 0: T = 0 protocol, 1: T = 1 protocol. Differences in protocol include differences in communication data format, whether or not a parity error is returned to the transmission source, and the like. The first autoload register (UMAR) 43 is a register in which the value of the mode register (UMR) 42 is automatically loaded when the transmission mode is automatically switched to the reception mode by setting T2R = 1.

  An ETU count register (UECR) 44 is a register in which the number of external clocks CLK corresponding to 1 etu, that is, a transfer rate is set. The second autoload register (UEAR) 45 is a register in which the value of the ETU count register (UECR) 44 is automatically loaded when the transmission mode is automatically switched to the reception mode by setting T2R = 1.

  The data register (UDR) 47 stores serial data received from the data input / output terminal IO1 when the UART 16 is set to the reception mode. When the reception of 1-byte serial data is completed, the UART 16 transfers and stores the received serial data from the shift register (USR) 21 to the UDR 47, and completes the receiving operation. Thereafter, the USR 21 can be received. Thus, since the USR 21 and the UDR 47 are double buffers, continuous reception operations are possible. Further, the UDR 47 becomes a read-only register when the UART 16 is set to the reception mode, and therefore cannot be written from the CPU 3. The data register UDR47 is an 8-bit register for storing data to be serially transmitted from the data input / output terminal IO1 when the UART 16 is set to the transmission mode. When the UART 16 detects that the shift register (USR) is empty, the transmission data written in the UDR 47 is transferred to the USR 21 to start serial transmission. If the next transmission data is written in the UDR 47 during serial data transmission of the USR 21, continuous serial transmission can be performed. The UDR 47 can always be read / written by the CPU 3 when the UART 16 is set to the transmission mode.

  The status register (UCSR) 46 has a TDRE bit, a TEND bit, and the like. In the transmission mode, the TDRE (Transmit Data Register Empty) bit is transferred from the UART data register (UDR) 47 to the shift register (USR) 21 of the UART 16 so that the next serial transmission data can be written to the UDR. It shows that. 0: Indicates that valid transmission data is written in the UDR 47. 1: Indicates that there is no valid transmission data in UDR 47. The TEND (Transmit End) bit indicates that there is no valid data in the UDR 47 when the last bit of the transmission character is transmitted in the transmission mode in the UART 16, and the transmission is terminated. The TEND bit is a read-only flag and is operated by the COMCNT 20. 0: Indicates that transmission is in progress. 1: Indicates that transmission has ended.

<Automatic switching from transmission mode to reception mode>
Hereinafter, automatic switching from the transmission mode to the reception mode in the UART 16 will be described in detail. The registers of the register circuit 40 are initialized by the CPU 3 except for the flag operation target by the FLGG 24. When the CPU 3 initializes the UECR 44 in which the transfer rate is set and the UMR 42 in which the transfer mode is set, the register circuit 40 also sets the data set in the UECR 44 in the UEAR 45 and the data set in the UMR 42 Also set to. The CPU 3 can individually initialize the UEAR 45 and the UMAR 43 as necessary according to the initialization control program or the like. When it is necessary to change the transfer rate or / and transfer mode at the time of automatic switching from the transmission mode to the reception mode, the CPU 3 loads data for changing the transfer rate into the UEAR 45, and the CPU 3 transfers the transfer mode to the UMA 43. Load data for change. If the UEAR 45 and the UMAR 43 are not rewritten, the transfer mode and the transfer rate are not changed in the automatic switching from the transmission mode to the reception mode. As described above, the automatic switching from the transmission mode to the reception mode is instructed by T = 0 and T2R = 1.

  FIG. 3 illustrates the operation timing of automatic switching from the transmission mode to the reception mode. T = 0 and T2R = 1 are set, and the transfer rate in the transmission mode is 32 CLK / etu. The value T = 0 is set in the UMR 42, the value T = 1 in the UMA 43, the value 32CLK / etu is set in the UECR 44, and the value 16CLK / et is set in the UEAR 45. In the transmission operation, when the COMLOG 25 detects that there is no next transmission data in the UDR 47 and the last bit is serially output from the USR 21, the COMLOG 25 loads the setting value of the UMA 43 into the UMR 42, and the UEAR 45 The setting value is loaded into the UECR 44, the communication mode is changed to T = 1, the communication rate is changed to 16CLK / etu, the state is changed to a reception state where data can be received, and the reception of data is waited.

  FIG. 4 illustrates a data processing system to which the IC card microcomputer 1 is applied. The data processing system shown in the figure is an IC card system, for example, and a card terminal device 50 and an IC card 51 are exemplified. The card terminal device 50 includes a processor 52 for IC card read / write control. The IC card 50 includes the IC card microcomputer 1, and the UART 16 is connected to the UART 54 of the processor 52 via the serial transmission line 53. The IC card microcomputer 1 is used for authentication processing necessary for using the IC card and security processing for confidential data.

  FIG. 5 illustrates a flowchart for establishing communication between the IC card and the card terminal device. When the IC card is mounted on the card terminal device and the IC card is reset, the IC card returns information on the communication protocol and transfer rate to the card terminal device by ART (Answer To Reset) (S1). For example, the communication rate at this time is 9600 bps which is the minimum of the IC card standard. The card terminal device determines the communication capability of the IC card based on the received ART, and returns the change to the maximum transfer rate at which communication is possible to the IC card (S2). For example, a change from 9600 bps to 384 Kbps is required. When the IC card returns a response to the change request to the card terminal apparatus by ATR (S3), thereafter, commands and data are transferred from the card terminal apparatus at a transfer rate of 384 Kbps (S4). Here, from the time when the IC card microcomputer 1 returns ATR in step S3 to the time when the card terminal device transmits a new command, in short, from the transmission state in which the ATR is transmitted to the reception state in which the command and data in S4 are received. At the time of switching, the transfer rate of the UART 16 must be changed. At this time, as described above, the IC card stores the data for change in the UMAR 43 and the UEAR 45 in advance, and if T2R = 1 is set in the process of S3, the UART 16 responds to the end of transmission of the ATR by S3. Then, the set values of UMAR 43 and UEAR 45 are loaded into the UMR 42 and UECR 44 and the inter-register transfer process is performed autonomously, and during that time, the CPU 3 is not burdened at all. Therefore, after detecting the end of S3, the IC card microcomputer 1 can change the transfer rate by inter-register transfer and immediately shift to the command and data reception waiting state (one reception state) by S4. As illustrated in the operation flowchart of FIG. 6, the CPU 3 does not need to perform memory read and register load operations to shift from the transmission state to the reception state. In this way, the transition from the transmission state to the reception state does not take time, and the burden on the CPU 3 does not have to be changed. For example, if there is no UMAL 43 and UEAR 45, when changing from the reception state to the transmission state, the CPU 3 reads the change data from the memory and loads the read data into the UMR 42 and UECR 44 as illustrated in the operation flow of FIG. Access processing must be performed, and the communication operation is interrupted during that time.

  8 and 9 illustrate in detail the processing flow of the UART 16 when the automatic switching function from the transmission mode to the reception mode (UCRT2R = 1) is used. To start the T2R mode, the CPU 3 first clears the UA bit and the RN_T bit of the UCR 41 to 0, and sets the UART 16 to the stop state and the reception mode (T1). The CPU 3 sets the number of 1 etu cooks in the UECR 44 and determines the initial value of the transfer rate (T2). Initial values are also set in the UEAR 45. When the UECR 44 is automatically changed when the transmission state is changed to the reception state, change data is set in the UEAR 45 (T4). If not changed, the value of UEAR 45 remains the same as the value of UECR 44. Next, the transmission / reception mode is set in the UCR 41 and the UMR 42 (T5). When the UMR 42 is automatically changed when the transmission state is changed to the reception state, change data is set in the UMA 43 (T7). If not changed, the value of UMAR 43 remains the same as the value of UMR 42. Thereafter, the CPU 3 sets UA = 1, RN_T = 1, and T2R = 1 for the UCR 41 (T8). As a result, the UART 16 becomes operable, the transmission mode is set, and an automatic switching operation to the reception mode is instructed after the transmission is completed. As a result, the transmission mode by T2R in FIG. 9 is started.

  In the transmission mode of FIG. 9, after confirming that there is no transmission data in the UDR 47 by the TDRE flag of the USR 46, the transmission data is written to the UDR 47 and the TDRE flag of the USR 46 is cleared to zero. As a result, the data written to the UDR 47 after the end of data transmission during transmission is written to the USR 21, and the next transmission operation is started. This operation is repeated until all data is transmitted (T9 to T12). At the time of the last data transmission, the TEND flag of the UCSR 46 indicating that transmission is in progress is read and polling is performed until the transmission is completed. In the T2R mode, for example, if switching from transmission to reception is performed around 11.5 etu from the start bit of the transmission data, the TEND flag is changed from 0 to 1 in a state where the UART 16 is switched to the reception state (T13, T14). In short, until the TEND flag is changed from 0 to 1, the operation of transferring the value of UMAR 43 to UMR 42 and the value of UEAR 45 to UECR 44 is completed as illustrated in FIG. After the UART 16 is switched to the reception mode, the CPU 3 executes a sleep command, and the IC card microcomputer 1 waits for input of a start bit of reception data in the sleep mode. When the start bit is detected in the sleep state, the IC card microcomputer 1 returns to the scrubbing operation state of the UART 16, and the CPU 3 and the like maintain the sleep state. The UART 16 that has returned to the operating state starts the receiving operation. To restore the CPU 3 after receiving data, the IE bit of the UCR 41 is set to 1 before executing the sleep command by the CPU 3, and a UART interrupt is issued to the CPU 3 after the reception is completed (T4, T15).

  FIG. 10 illustrates the connection relationship between UMR 42 and UECR 44, UMAL 43 and UEAR 45 exclusively. The UMAL 43 and UEAR 45 are respectively accessed by the CPU 3 via the data bus DBUS, and the UMR 42 and UECR 44 are connected to the outputs of the data bus DBUS or UMAL 43 and UEAR 45 via selectors (SEL) 60 and 61. Transfer from the UMAL 43 and UEAR 45 to the UMR 42 and UECR 44 is performed via the selectors 60 and 61 based on the control of the COMLOG 25. Selection of the data bus DBUS and the registers UMR42, UMAL43, UECR45, and UEAR44 by the selectors 60 and 61 is controlled based on an instruction executed by the CPU 3.

  FIG. 11 shows an example in which UMA is composed of UMARa 43A and UMALb 43B, and UEAR is composed of UEARa 45A and UEARb 45B. The UMR 42 can be connected to the data bus DBUS, UMARa 43A or UMARb 43B via the selector (SEL) 62, and the UECR can be connected to the data bus DBUS, UUERa 45A or UEARb 45B via the selector (SEL) 63. There are more choices of transfer rate and transfer protocol that can be selected when switching the communication state. A specific bit of the UCR 41 may be used to instruct the selector 62 to select UMARa 43A or UMARb 43B, and the selector 63 to select UEARa 45A or UEARb 45B. The selection timing is controlled by the COMLOG 25. Selection of the data bus DBUS and the registers UMR42, UMARa43A, UMARb43B, UECR44, UEARa45A, and UEARb45B by the selectors 62 and 63 is controlled based on an instruction executed by the CPU 3. 10 and FIG. 11, illustration of other configurations is omitted, but it goes without saying that other circuit configurations illustrated in FIG. 2 are actually provided.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the semiconductor device is not limited to an IC card microcomputer, and can be widely applied to a microcomputer having no security function, an accelerator, a large-scale integrated circuit having an intelligent function called a system-on-chip, and the like. The circuit module included in the microcomputer is not limited to FIG. The start / reception system transmission / reception circuit may be provided with a clock synchronization transmission / reception function. The transmission / reception circuit is not limited to UART. The register configuration of the UART is not limited to that shown in FIG. The IC card may be a SIM card or the like. A SIM card card terminal device corresponds to a mobile terminal device represented by a mobile phone.

FIG. 1 is a block diagram showing an example of a UART. FIG. 2 is a block diagram of an IC card microcomputer as an example of a semiconductor device according to the present invention. FIG. 3 is a timing chart illustrating the operation timing of automatic switching from the transmission mode to the reception mode. FIG. 4 is a block diagram illustrating a data processing system to which an IC card microcomputer is applied. FIG. 5 is a flowchart showing an operation when establishing communication between the IC card and the card terminal device. FIG. 6 is a flowchart in the case of performing automatic switching from the transmission state to the reception state. FIG. 7 is a flowchart in the case of switching from the transmission state to the reception state when there is no UMAR or UEAR. FIG. 8 is a flowchart for starting the T2R mode when the automatic switching function from the transmission mode to the reception mode (UCRT2R = 1) is used. FIG. 9 is a flowchart of a transmission mode by T2R. FIG. 10 is a block diagram exclusively illustrating the connection relationship between UMR and UECR and UMAL and UEAR. FIG. 11 is a block diagram illustrating a case where a plurality of sets of UMAR and UEAR are provided.

Explanation of symbols

1 IC card microcomputer (IC card microcomputer)
IO1, IO2 Data input / output terminal CLK Clock input terminal RES Reset terminal Internal data bus DBUS
5 Clock pulse generator (CPG)
3 Central processing unit (CPU)
6 System controller (SYSCNT)
10 Mask ROM (MROM)
11 Random access memory (RAM)
12 Nonvolatile memory (EEPROM)
13 Timer (TMR)
16 UART
20 Communication control unit (COMCNT)
40 register circuit (REGC)
30, 31 Synchronization circuit (SYNC)
25 Communication control logic (COMLOG)
21 Shift register (USR)
22 CRC register (UCRC) 22
23 etu pulse generator (ETUG)
24 Flag Generator (FLGG)
41 Control register (UCR)
42 Mode register (UMR)
43 First autoload register (UMAR)
44 ETU count register (UECR)
45 Second autoload register (UEAR)
46 Status register (UCSR)
47 Data register (UDR)
50 card terminal device 51 IC card 52 processor 43A UMARa
43B UMALb
45A UEARa
45B UEARb

Claims (10)

A central processing unit, and a transmission / reception circuit capable of serial transmission / reception processing according to the setting of the central processing unit,
The transmission / reception circuit includes a communication condition setting register in which communication conditions are set by the central processing unit;
A change register that enables the setting data by the central processing unit to be transferred to the communication condition setting register;
Transmission / reception control capable of executing communication by storing the change register setting value in the communication condition register by detecting the end of communication due to the previous communication state when switching of the communication state is instructed A semiconductor device.   The semiconductor device according to claim 1, wherein the communication condition set in the communication condition setting register by the central processing unit is set in parallel to the change register. The communication condition setting register is a communication rate setting register in which data specifying a communication rate is set, and a communication protocol setting register in which data specifying a communication protocol is set,
The change register is a first change register in which setting data can be transferred to the communication rate setting register, and a second change register in which setting data can be transferred to the communication protocol setting register. Item 14. A semiconductor device according to Item 1.   The transmission / reception control unit responds to the end of the first communication state when an instruction to switch the communication state from the first communication state to the second communication state is set in the control register by the central processing unit. Storing a setting value of one change register in the communication rate setting register and storing a setting value of the second change register in the communication protocol setting register to enable execution of data communication in a second communication state; The semiconductor device according to claim 3.   The semiconductor device according to claim 4, wherein the first communication state is a transmission state, and the second communication state is a reception state.   6. The semiconductor device according to claim 5, wherein the transmission / reception circuit is a UART that performs a half-duplex serial transmission / reception process to the outside. The transmission / reception control unit has a transfer end flag that is operated to reflect the end of transmission,
The transmission / reception control unit stores the set value of the first change register in the communication rate setting register between the time when transmission is detected and the time when transmission end is reflected in the transfer end flag. The semiconductor device according to claim 6, wherein a process of storing a setting value of the second change register in the communication protocol setting register is performed and data reception is waited. A plurality of sets of the first change register and the second change register;
The transmission / reception control unit selects the first change register and the second change register that store values in the communication rate setting register and the communication protocol setting register when the communication state is switched according to the setting value of the control register. The semiconductor device according to claim 4. A first data processor;
When a request to change to the second communication condition is included in the response to the first data processor sent from the first data processor under the first communication condition, the approval for the change Is transmitted to the first data processor under the second communication condition and the response is returned from the first communication condition to the second data condition until a response is returned from the first data processor to the first data processor. A second data processor that changes to the communication conditions of
A data processing system having a serial signal line connected to a first data processor and a second data processor for communication according to the first communication condition and the second communication condition,
The second data processor has a central processing unit and a transmission / reception circuit capable of serial transmission / reception processing via the serial signal line according to the setting of the central processing unit,
The transmission / reception circuit includes a communication condition setting register in which communication conditions are set by the central processing unit;
A change register that enables the setting data by the central processing unit to be transferred to the communication condition setting register;
When switching from the transmission state to the reception state is instructed, by detecting the end of the transmission state, the setting value of the change register is stored in the communication condition setting register, and transmission / reception control that can be changed to the reception state A data processing system.   11. The data processing according to claim 10, wherein the first data processor is an IC card microcomputer mounted on an IC card, and the second data processor is a processor of an IC card terminal device to which the IC card is mounted. system.

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