JP2923892B1 - ATM cell insertion system and method - Google Patents

Abstract

An ATM cell insertion method capable of preferentially inserting cells is realized. SOLUTION: A RAM for storing cell data and inserting the read cell data into a transmission path, a write address pointer indicating a write address of the RAM, and a RAM
A read address pointer indicating the read address of the RAM, an address holding unit for holding an address of the RAM in which the cell data is written, and incrementing the write address pointer and the read address pointer by one each time a write operation and a read operation to the RAM are performed. As a result, the FIFO operation is performed, and the data is written into the RAM,
In the case of performing the priority insertion of inserting the cell data that is not read in the priority order into the transmission line, the first address in the RAM 1 of the cell data to be preferentially inserted into the transmission line with reference to the address holding unit. And a control means for setting the confirmed first address as a read address pointer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchronous Transfer Mode) cell insertion method and an ATM cell insertion method. The present invention relates to an ATM cell insertion method and an ATM cell insertion method used for insertion into a position.

[0002]

2. Description of the Related Art Conventionally, this type of ATM cell insertion method generally uses a FIFO (First-In First-Out) type memory, and stores cell data in a memory in the order of a cell insertion request. At the time of writing and reading, when there is an empty cell in the transmission line, the data is read out in the order written in the memory and inserted as a cell on the transmission line.

FIG. 2 is a block diagram showing a main part of an apparatus according to a conventional method.

[0004] The ATM cell insertion system of the present invention uses a RAM
1, a write address pointer 2 indicating a write address of the RAM 1, a read address pointer 3 indicating a read address of the RAM 1, a write address pointer 2
And a control unit 4 for controlling the read address pointer 3 and A
An ATM processing unit 6 that performs TM processing, generates cell data, and issues a priority insertion request for cells on a transmission path.

The cell data and the priority insertion request signal from the ATM processing unit 6 are supplied to the control unit 4. The output is processed by the control unit 4, and the cell data is output to the RAM 1. The control unit 4 controls the write address pointer 2 when outputting cell data to the RAM 1. The control unit 4 detects an empty cell on the transmission line and inserts the cell data written in the RAM 1 into the empty cell. At this time, the control unit 4 controls the read address pointer 3 to read the cell data in the order in which the cell data was written.

[0006]

In recent years, international standardization organizations have been using OAM (Operation, Admission and Ser
vice) As the detailed discussion of the function progresses, OAM cells must be forcibly inserted even if there are no empty cells when the specified VP (Virtual Path) is kept waiting for more than a certain number of cells after the insertion request. Is being demanded. This allows V
Depending on the traffic of P, it is necessary to preferentially insert a cell that has been requested to be inserted later.

[0007] In the conventional example shown in FIG.
It is configured to write cell data to the memory in the order of the cell insertion request, and to read data in the order of writing to the memory when there is an empty cell in the transmission path at the time of reading. Therefore, the cell data once written in the memory can always be read only in the order in which it was written. As a result, even if it becomes necessary to insert a certain cell preferentially after writing to the memory, desired data cannot be read unless all cells written before that are read, that is, forced insertion cannot be performed. There is a problem.

The present invention has been made in view of the above-mentioned problems of the conventional technology. In an ATM device, cells are usually inserted as FIFO on a first-come-first-served basis, but a certain cell in a memory is prioritized. It is an object of the present invention to realize an ATM cell insertion method and method capable of skipping the write order and inserting cells preferentially when it becomes necessary to insert the cells in a random manner.

[0009]

According to the ATM cell insertion method of the present invention, an AT cell inserts a plurality of cell data in which an insertion request to a transmission line occurs at random, into an empty cell on the transmission line.
In the M cell insertion method, a RAM in which cell data is stored and read cell data is inserted into a transmission path, a write address pointer indicating a write address of the RAM, a read address pointer indicating a read address of the RAM, , Where the cell data is written
An address holding unit for holding an address of the AM;
M, a write address pointer, a read address pointer, and an operation of an address holding unit.
Control means for determining the order of insertion of the cell data stored in the transmission line into the transmission path, wherein the control means sets the write address pointer and the read address pointer each time a write operation and a read operation to the RAM are performed. In the case of performing the priority operation of performing the FIFO operation by incrementing by 1 and inserting the cell data written in the RAM and read out in an unordered order into the transmission line preferentially, refer to the address holding unit. The first address of the cell data to be inserted into the transmission line with higher priority in the RAM 1 is confirmed, and the confirmed first address is set in the read address pointer.

In this case, the control means checks the first address when performing the priority insertion, checks the second address currently set in the read address pointer, and replaces the first address with the read address. A second address may be set in the read address pointer after the priority insertion of the cell data by setting the pointer is performed.

Further, the control means writes a predetermined inserted pattern at the address of the RAM where the cell data in which the priority insertion has been performed is stored, and after the priority insertion, stores the second pattern in the read address pointer. When the inserted pattern is confirmed at the time of cell data insertion performed by setting an address, the data may not be inserted into the transmission path.

According to the ATM cell insertion method of the present invention, a RAM for storing cell data and inserting the read cell data into a transmission line, a write address pointer indicating a write address of the RAM, and a read address of the RAM And an address holding unit that holds the address of the RAM in which the cell data is written, and controls the operations of the RAM, the write address pointer, the read address pointer, and the address holding unit. In an ATM cell insertion method for determining an insertion order of cell data stored in a RAM to a transmission line, the write address pointer and the read address pointer are incremented by one each time a write operation and a read operation to the RAM are performed. FIFO When priority insertion is performed, in which cell data written in the RAM and read out in an unordered order is preferentially inserted into the transmission path, the transmission path is preferentially referred to by referring to the address holding unit. The first address of the cell data to be inserted into the RAM 1 is confirmed in the RAM 1, and the confirmed first address is set in the read address pointer.

In this case, when the priority insertion is performed, the first address is confirmed, and the second address currently set in the read address pointer is confirmed.
The second address may be set in the read address pointer after the cell data is preferentially inserted by setting the address in the read address pointer.

Further, a predetermined inserted pattern is written into the RAM at the address where the cell data into which the priority insertion has been performed is stored, and after the priority insertion,
When the inserted pattern is confirmed at the time of cell data insertion performed by setting a second address in the read address pointer, the data may not be inserted into the transmission path.

[Operation] In the present invention configured as described above, the first address of the cell data to be preferentially inserted can be confirmed by providing the address holding unit for holding the address of the RAM. When the priority insertion is not performed, the normal FIFO operation is performed. When the priority insertion is performed, the first address of the cell data to be preferentially inserted confirmed by the address holding unit is set in the read address pointer. Cell data to be preferentially inserted is inserted into the transmission path.

In the case where priority insertion is performed, the first address is confirmed, the second address currently set in the read address pointer is confirmed, and the first address is set in the read address pointer. By setting the second address in the read address pointer after the priority insertion of the cell data according to the above, the state before the priority insertion is performed after the priority insertion is performed.

Further, a predetermined inserted pattern is written at the address of the RAM where the cell data into which the priority insertion has been performed is stored, and after the priority insertion,
When the inserted pattern is confirmed at the time of cell data insertion performed by setting the second address in the read address pointer, the data is not inserted into the transmission path, so that the priority inserted cell is inserted. Data can be prevented from being inserted redundantly.

[0018]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. As shown in FIG. 1, in this embodiment, an ATM processing unit 6, a control unit 4 for controlling writing and reading of a memory, a write address pointer (W-PT
R) 2, read address pointer (R-PTR) 3,
RAM (Random) that stores data as data memory
Access Memory) 1 and address holding unit (ADDR)
5 is comprised. The configuration of this embodiment is different from the conventional example shown in FIG. 2 in that an address holding unit 5 is newly provided, and the operation thereof is changed accordingly. This will be described with reference to FIG.

The control unit 4 controls a write operation to the RAM 1 and the address holding unit 5 and a read operation for inserting cells in response to a request from the ATM processing unit 6, and a read address in a normal read operation. The value of the pointer 3 is incremented by one, and the cell data stored in the RAM 1 is read in the order in which the writing was performed.

When cell data is written to the RAM 1, the cell data is written into the write address pointer 2 by the control unit 4.
When the cell data is written, the write address pointer 3 is incremented by one.

At the time of normal cell data reading, the control section 4 reads cell data from the RAM 1 based on the address indicated by the read address pointer 3 and inserts the cell data into the cell as a cell when detecting an empty cell on the transmission path. After reading the data, the read address pointer 3 is incremented by one. If the read data is an output-completed pattern, the read address pointer 3 is incremented without inserting the read data into the transmission path. Normally, the data is read from the old cell data which has been written, so that the RAM 1 operates as a FIFO.

The address holding unit 5 holds the value of a write address when the control unit 4 writes cell data from the ATM processing unit 6 into the RAM 1. The control unit 4 is indicated by the write address pointer 2 when writing cell data. The stored address is held in the address holding unit 5. The storage location of the address indicated by the write address pointer 2 in the address holding unit 5 is determined by the type of cell data to be written to the RAM 1 (for example, a VPI (Virtual Path Identifier) value,
It is uniquely determined in advance by a VCI (Virtual Channel Identifier) value or the like. In the example shown in FIG. 1, write addresses 05h to 08h corresponding to CELLDATA A to CELLDATA D are stored at addresses 00h to 03h, respectively. The control unit 4 writes the cell data into the RAM 1, stores the value of the write address at that time in the address holding unit 5, and manages the address in the address holding unit 5. This address management is also performed by the ATM processing unit 6 interconnected with the control unit 4.

In the present embodiment, the ATM processing section 6 requests priority insertion of predetermined cell data, and gives the cell data to the control section 4 when it becomes necessary to insert cell data on a transmission line.

When there is a priority insertion request for predetermined cell data from the ATM processing unit 6, the control unit 4 sends the RAM storing the corresponding cell data from the address holding unit 5 to the RAM.
The address 1 is taken out, the address pointer 3 is operated to read the corresponding cell data stored in the RAM 1 and inserted into the transmission line, and thereafter the read address pointer 3 is returned to the original value.

The control unit 4 operates the write address pointer 2 to write a predetermined inserted pattern in the storage location of the cell data read out preferentially, and the inserted address pattern is determined by the read address pointer. When read, the cell data at the next address is read by operating the read address pointer 3 without inserting it into the transmission path.

Now, suppose that the need to output CELL C with priority occurs after writing CELLDATA C to RAM1. At this time, the read address pointer 3 is at the position of CELLDATA A, that is, 05.
h. The ATM processing unit 6 gives the control unit 4 an address value 02h of the address holding unit 5 for CELL C as a priority insertion request signal. The control unit 4 extracts the address 07h in which the CELLDATA C is written from the address holding unit 5, stores the current value 05h of the read address pointer 3 in a holding unit (not shown) inside the control unit 4, and then stores the current value 05h in the read address pointer 3. Give the address 07h and read CELLDATA C from RAM1.
Is read out and inserted on the transmission path. The control unit 4 is CEL
After the output of LDATAC, the current value (undefined) of the write address pointer 2 is stored in the holding unit inside the control unit 4, and the CELLDATA is temporarily stored in the write address pointer 2.
An address 07h from which C is read is given, and a predetermined inserted pattern is written into the RAM 1. After that, the stored original values are given to the write address pointer 2 and the read address pointer 3, and the operation returns to the normal operation. Therefore, the address pointer 3 has 05
h is given.

When data is sequentially read, CELLD
The address 07h from which the ATA C has already been read is also read again, but since the inserted pattern is written there, no data is inserted and no cell is inserted redundantly. .

In the present embodiment configured as described above, while the cells are normally read out in the order written as FIFO and cells are inserted on the transmission line, even after the cell data is once written in the memory, , Only predetermined cell data can be preferentially read.

[0030]

As described above, according to the ATM cell insertion method of the present invention, the FIFO memory is constituted by using the RAM, and the address holding section for holding the write address is provided, so that the desired data can be written even after the data is written. Data is skipped in its original order and can be output with priority.

Therefore, even if it becomes necessary to raise the priority of cell insertion after a cell insertion request, it is possible to immediately take out only desired cells, and thereafter return to the normal operation of inserting cells in the order in which they were written. .

Furthermore, in the present embodiment, when the priority insertion is performed, a predetermined inserted pattern is written so that the cells once inserted by the priority insertion of the cells are not repeatedly inserted. doing.

In the above embodiment, the address holding unit 5
As a storage method, a method of previously specifying a storage location by a VPI value or a VCI value for cell data has been described. However, the address holding unit 5 is configured using an associative memory so that individual cell data can be identified. Part of the cell data may be written. Further, the holding unit inside the control unit 4 can be configured using a buffer or a flip-flop.

[Brief description of the drawings]

FIG. 1 is a diagram showing an ATM cell insertion system of the present invention.

FIG. 2 is a diagram showing a conventional ATM cell insertion method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 RAM 2 Write address pointer 3 Read address pointer 4 Control part 5 Address holding part 6 ATM processing part

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/56

Claims (6)

(57) [Claims] 1. An ATM cell insertion method for inserting a plurality of cell data at which a request for insertion into a transmission line occurs at random into an empty cell on the transmission line, wherein the cell data is stored and the read cell data is stored in the transmission line. A RAM to be inserted; a write address pointer indicating a write address of the RAM; a read address pointer indicating a read address of the RAM; an address holding unit that holds an address of the RAM where cell data is written; Control means for controlling operations of a write address pointer, a read address pointer, and an address holding unit, and determining an order of insertion of the cell data stored in the RAM into a transmission line. Each time a write operation and a read operation to the In the case where the FIFO operation is performed by incrementing the address pointer and the read address pointer by one, and the cell data written in the RAM and read out of the order is preferentially inserted into the transmission path, The first address in the RAM 1 of the cell data to be preferentially inserted into the transmission path is confirmed with reference to the address holding unit,
The ATM cell insertion method, wherein the confirmed first address is set in the read address pointer. 2. The ATM cell insertion system according to claim 1, wherein the control means checks the first address when performing priority insertion and checks the second address currently set in the read address pointer. An ATM cell insertion method, wherein a second address is set in the read address pointer after cell data is preferentially inserted by setting the first address in the read address pointer. 3. The ATM cell insertion system according to claim 2, wherein the control means writes a predetermined inserted pattern into the RAM at the address where the cell data having been subjected to the priority insertion is stored, and The ATM cell insertion method, wherein when the inserted pattern is confirmed at the time of cell data insertion performed by setting a second address in the read address pointer after the insertion, the data is not inserted into a transmission line. . 4. A RAM for storing cell data and inserting the read cell data into a transmission path, a write address pointer indicating a write address of the RAM, a read address pointer indicating a read address of the RAM, And an address holding unit that holds the address of the RAM in which the cell data is written, and controls the operations of the RAM, the write address pointer, the read address pointer, and the address holding unit, and stores the cell data in the RAM. An ATM cell insertion method for deciding an insertion order of cell data into a transmission line, wherein the write address pointer and the read address pointer are incremented by one each time a write operation and a read operation to the RAM are performed.
O operation is performed, and when priority insertion is performed, in which cell data written and read out to the RAM in an unordered order is preferentially inserted into a transmission line, transmission is preferentially performed with reference to the address holding unit. RAM for cell data to be inserted into the path
1. A method of inserting an ATM cell, comprising: confirming a first address in 1 and setting the confirmed first address in the read address pointer. 5. The ATM cell insertion method according to claim 4, wherein when performing priority insertion, the first address is confirmed and the second address currently set in the read address pointer is confirmed.
And after setting the first address in the read address pointer and performing priority insertion of cell data, setting the second address in the read address pointer.
Cell insertion method. 6. The ATM cell insertion method according to claim 5, wherein a predetermined inserted pattern is written at an address of the RAM where the cell data having been subjected to the preferential insertion is stored, and after the preferential insertion, the predetermined pattern is written. An ATM cell insertion method, wherein when the inserted pattern is confirmed at the time of cell data insertion performed by setting a second address in a read address pointer, the data is not inserted into a transmission line.