JPH11261569A - Address management device in shared buffer of atm cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To retrieve an open address and a read address in a shared buffer and to easily execute the management of addresses of the shared buffer by registering a used address and an unused address in the shared buffer that randomly registers an ATM cell on a content address memory(CAM) and utilizing a retrieval function of the CAM. SOLUTION: An address management device of a shared buffer of an ATM cell has a CAM 14 which manages an open address of the shared buffer and a read address of every an output port number and an address retrieving part 13 which retrieves the free address and the read address from the CAM 14 in an address management circuit part 11 of the shared buffer. Its management method has a step which stores an open address and a read address of the shared buffer in one CAM 14 and a step which retrieves the free address or the read address of the shared buffer with an address pointer of the CAM 14 and performs address management of the shared buffer of the ATM cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an asynchronous transfer mode (hereinafter referred to as ATM).
The present invention relates to a method and an apparatus for managing an address of a shared buffer of an ATM cell in the communication system of the above.

[0002]

2. Description of the Related Art Conventionally, an ATM cell shared buffer implemented in an ATM switch or the like has a purpose of reducing the storage buffer capacity of the ATM cell and minimizing cell loss with a small buffer amount due to a statistical multiplexing effect. I have.

[0003] For example, "Large-capacity ATM switch LSI"
Development ”, Shimizu et al., 1997 IEICE General Conference B-
8-22 describes a technique of managing a free address of a shared buffer and a use address by using a buffer that is individually prepared.

FIG. 9 is a block diagram showing an example of a conventional shared buffer address management method. Shared buffer 91
Is a cell storage buffer for storing received cells according to the instruction of the write control unit 96 and reading out the cells according to the instruction of the read control unit 97. The free address buffer 95 manages all free addresses in the shared buffer 91. The read address buffers 92, 93, and 94 are prepared for each output port number for managing the ATM cell, and manage the address of the shared buffer 91 which is "in use" by writing the cell data in the shared buffer 91. In FIG. 9, the number of output port numbers is described as # 1 to #N.

[0005] The write control unit 96 determines the registration address of the received ATM cell in the shared buffer 91 and registers the address used by the registration in the read address buffers 92, 93 and 94. Read control unit 97
Determines the read address from the shared buffer 91 and registers the “unused” address in the free address buffer 95 by reading. The empty address output from the empty address buffer 95 is always registered in one of the read buffers 92, 93, and 94 corresponding to the output port number value when used for writing. The read addresses output from the read buffers 92, 93 and 94 are always registered in the free address buffer 95 when used for reading. Thus, the address of the shared buffer 91 is always managed by the empty address buffer 95 or the read address buffers 92, 93, 94. Further, by using the buffers for managing the addresses in a FIFO (First In First Out) format, the order of the ATM cells read from the shared buffer 91 is maintained.

[0006]

However, the prior art has the following problems.

[0007] The first problem is that once a fraud has occurred in address management, the fraud will persist without disappearing.

The reason is that addresses circulate between an empty address buffer and a read address buffer.

A second problem is that the circuit scale increases as the number of output ports increases. Therefore, when expanding the number of output ports, the circuit configuration must be changed.

[0010] The reason is that a read address buffer is prepared for each output port. Since a read address buffer is prepared for each output port, the buffer capacity increases as the number of output ports increases, which leads to an increase in circuit size.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a method of managing addresses of a shared buffer of ATM cells.

[0012]

An address management method for a shared buffer of ATM cells according to the present invention stores a used address and an unused address of a shared buffer for randomly registering an ATM cell in a content address memory (Content Address).
s Memory: hereinafter referred to as CAM). The address search is performed by using the search function of the CAM, thereby easily managing the address of the shared buffer.

According to the address management method of the present invention for a shared buffer of ATM cells, in a shared buffer type ATM switch or an AAL type 5 frame assembling circuit, an empty address of a shared buffer and a read address are stored in one content address memory. And a step of searching for a free or read address of the shared buffer from the position indicated by the address pointer in the content address memory, and managing the address of the shared buffer of the ATM cell.

Further, in the shared buffer type ATM switch or AAL type 5 frame assembling circuit according to the present invention, the shared buffer address management device comprises: a content address memory for storing an empty address of the shared buffer and a read address; Means for searching for a free or read address of the shared buffer from the position indicated by the address pointer in the memory; and when writing to the shared buffer, the address flag is free and closest to the write pointer prepared for each output port number. A free address is searched, and if no free address is found by the search, the write pointer is initialized. If a free address is found, the corresponding address flag is rewritten from free to in use, and the cell buffer is used. Write a When reading from the shared buffer, the address closest to the read pointer prepared for each output port number and the address flag being used is searched. When the address corresponding to the read pointer is searched, the corresponding address flag is rewritten from being used to being empty,
It is output as a read address of a cell buffer.

According to the present invention, the arriving cell data is A
All are stored in one cell buffer regardless of the connection of the TM cell. The empty address of the cell buffer at the time of storing the cell data and the read address at the time of reading the cell data are easily searched from the CAM by using the address search function. At the time of accumulating the cell data, the address of the cell buffer of the cell data to be accumulated is determined by using the empty address flag as a search key and the empty address closest to the write pointer value prepared for each output port number from the CAM using the address search function. Is read. When reading cell data, the address of the cell buffer to be read is:
Using the output port number of the cell to be read as a search key, the closest address is read from the read pointer value prepared for each output port number. This facilitates the normality management of the storage cell address registration order while using the shared buffer.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a shared buffer type cell switch for executing an address management method in a shared buffer of ATM cells.

Address management circuit 11 for shared buffer
As shown in FIG. 1, the CAM 14 has a CAM 14 that manages a vacant address of a cell buffer 12 that is a shared buffer and a read address for each output port number, and an address search unit 13 that searches the CAM 14 for a vacant address and a read address. doing. The cell buffer 12 is a buffer for temporarily storing ATM cells, and is a shared buffer for sequentially registering received cells regardless of the output port number. The cell multiplexing unit 15 multiplexes the ATM cells in the fixed order of the input ports, and multiplexes the ATM cells with the cell buffer 12 and the switch table 16.
Output to The switch table 16 determines the output port number of the ATM cell from the input cell data,
Output to the address search unit 13. The output port number generation unit 17 generates the output port numbers in a fixed order, and outputs the output port numbers to the address search unit 13 and the cell separation unit 18. The cell separation unit 18 distributes the cell data read from the cell buffer 12 to output ports obtained from the output port number generation unit 17.

Next, details of the configuration of the address management circuit section 11 will be described with reference to FIG. The CAM 14 stores the cell buffer 12 when storing the data in the cell buffer 12 in units of cells.
, An output port number 22 of the reception cell stored in the cell buffer, and data of a vacancy flag 23 indicating use and non-use (vacancy) of the corresponding address. The empty flag 23 indicates that the registered cell buffer address is empty (unused) if the flag value is “0”.
If the flag value is "1", it indicates that cell data is written (in use) at the address of the cell buffer.

The address search unit 13 prepares a write pointer Wp (x) and a read pointer Rp (x) prepared for each output port number in the address management of the CAM 14, and writes the CAM of the CAM that has finished writing for each output port. Address value,
It has a table 24 for managing the address value of the CAM for which reading has been completed.

Next, the operation of the circuit of FIG. 1 will be described with reference to the drawings. ATM cells from multiple input ports are:
In the cell multiplexing unit 15, the cells are multiplexed in a fixed order of the input ports, and are written in the cell buffer 12. The address on the cell buffer 12 where the ATM cell is to be written is determined by searching an empty address of the cell buffer registered in the CAM 14 by the address search unit 13.
The address search unit 13 receives the output port number of the received cell from the switch table 16 and searches the CAM 14 for a free address in the cell buffer closest to the address where the ATM cell to the input output port is already registered. .

FIG. 3 is a flow chart of an empty address search in the address search unit 13. Referring to FIG. 3, the address search unit 13 is the closest to the write pointer (Wp (x) in the figure) prepared for each output port number, and the CAM whose empty flag registered in the CAM 14 is “0”. Address (steps 1S, 2
S, 3S, 4S). If a free address of the cell buffer 12 is not found by the search, it is determined that the cell buffer 12 has overflowed, and the write pointer Wp (x) for the output port number is initialized without outputting the free address. (Steps 8S, 9
S). If a free address is found, the CAM 14
The empty flag 23 of the corresponding address is rewritten to "1", and the registered address 21 of the cell buffer 12 is output as an empty address (steps 5S, 6S, 7).
S).

Reading of cell data from the cell buffer 12 is performed by reading address data of all output ports in a fixed order. The address search unit 13 searches the CAM 14 for an address read from the cell buffer 12 using the output port numbers input from the output port number generation unit 17 in a fixed order as search keys.

FIG. 4 is a flowchart of a read address search in the address search unit 13. Referring to FIG. 4, the address search unit 13 uses a read pointer prepared for each output port number (Rp (x
)) Is searched for the closest CAM address (steps 11S, 12S, 13S, 14S). By search,
If the address of the CAM is not searched, it is determined that the cell buffer 12 underflows the search value.
Initialize Rp (x) for the output port used as the search key (steps 18S, 19S). If the address of the CAM corresponding to the search key is found, CAM1
4 is rewritten to empty “0”,
The registered address 21 of the cell buffer 12 is output as a read address of the cell buffer 13 (steps 15S, 16S, 17S).

The read cell data is transmitted to the cell separation unit 1
At 8, the output ports are sorted according to the fixed order.

Next, another embodiment of the present invention will be described in detail with reference to the drawings. FIG. 5 shows an AAL (ATM Adaptation Layer) type 5 A using this address management method.
It is a block diagram which shows the structure of the frame assembly circuit of a TM cell. Referring to FIG. 5, the address management circuit unit 11
Is a CAM that manages a vacant address of the cell buffer 12 as a shared buffer and a read address for each VPI value.
14 and an address search unit 13 for searching the CAM 14 for a free address and a read address. AT
The M cell frame assembling circuit includes an address management circuit 11 for a shared buffer, an invalid cell discarding unit 51 around the cell buffer 12, a received cell judging unit 52, an assembling request FIFO 53, a read cell judging unit 54, a header A deletion unit 55 and a frame assembly buffer 56 are provided.

The configuration of the address management circuit section 11 in the present embodiment will be described with reference to FIG. As shown in the figure, the CAM 14 stores an address 21 of the cell buffer 12 when storing the ATM cell unit in the cell buffer 12;
It has the VPI value 61 of the received cell stored in the cell buffer and the data of the empty flag 23 indicating whether the corresponding address is used or unused (empty). In the empty flag 23, if the flag value is "0", the registered cell buffer address is empty (unused), and if the flag value is "1", the cell data is written in the cell buffer address. (Used).

The address search unit 13 manages the address of the CAM 14 by using a write pointer Wp prepared for each VPI value.
(x) and a read pointer Rp (x) are prepared, and the address value of the CAM after writing and the address value of the CAM after reading are managed for each reception cell.

Next, the operation of the circuit of FIG. 5 will be described with reference to the drawings. The received cell is discarded by the invalid cell discarding unit 51 except for the user cell, and only the user cell is output to the received cell determining unit 52 and the cell buffer 12. The received cell determination unit 52 determines the received user cell VPI value in the CAM 14
Is output to the address search unit 13 as a registered value to the receiver. When the payload type (PT) is “001”, the received cell is determined to be an EOM (End Of Message) cell, and the VPI value is also output to the assembly request FIFO 53. .

The address search unit 13 searches for an empty address in the cell buffer closest to the address where the ATM cell of the received VPI value has already been written. Is registered. The cell data registered in this way is V
When one frame is accumulated for each PI value, it is read out for frame assembly. The VPI value of the ATM cell is registered in the assembly request FIFO 53 when the EOM cell is received. Therefore, the VPI value is registered every time one frame of cell data is written in the cell buffer 12.

The address search unit 13 is provided with an assembly FIFO
The VPI value is read from 53, and the read address of the ATM cell cell buffer for the VPI value written for one frame is searched. Reading of one frame of cell data for each VPI value is performed until the read cell determination unit 54 monitors the EOM cell. When the EOM cell is monitored, the cell data of the search VPI value is read for one frame, and the reading of the cell data is completed. The cell data read from the cell buffer is assembled into a frame by deleting the cell header in the header deleting section 55 and sequentially registering the cell data in the frame assembling buffer 56.

FIG. 7 is a flowchart for searching for an empty address in the address search unit 13 in FIG. Referring to the figure, the address search unit 13 is closest to a write pointer (Wp (x) in the figure) prepared for each VPI value,
The address of the CAM whose empty flag is “0” registered in the CAM 14 is searched (steps 21S, 22).
S, 23S, 24S). If no empty address is found by the search, it is determined that the cell buffer 12 has overflowed, and the write pointer Wp (x) for the VPI value is initialized without outputting the empty address (step 28S). , 29S). If a free address is found, the free flag 23 of the corresponding address in the CAM 14 is rewritten to "1", and the registered address 21 of the cell buffer 12 is output as a write address (steps 25S, 26S, 27S). .

Reading of cell data from the cell buffer 12 is performed by reading address data of all the received cells in a fixed order. The address search unit 13 searches the CAM 14 for a read address from the cell buffer 12 using the VPI value of the received cell input in a fixed order from the read cell determination unit 54 as a search key.

FIG. 8 is a flowchart of a read address search in the address search unit 13 of FIG. Referring to the figure, the address search unit 13 uses a VPI value of a received cell to be output and a search key in which an empty flag is set to “1”.
Read pointer prepared for each VPI value (Rp in the figure)
(X)), the nearest CAM address is searched (steps 31S, 32S, 33S, 34S). If the CAM address is not found by the search, it is determined that the cell buffer 12 underflows with respect to the search VPI value, and Rp (x) with respect to the VPI value of the received cell used as the search key is initialized (step 38S). , 39
S). When the address of the CAM corresponding to the search key is searched, the corresponding address flag 23 of the CAM 14 is rewritten to empty “0”, and the registered cell buffer 12 is rewritten.
Is output as the read address of the cell buffer 13 (steps 35S, 36S, 37S).

The address search unit 13 is provided with an assembly FIFO
The VPI value is read from 53, and an ATM cell read address for the VPI value written for one frame is searched (step 40S). The reading of the cell data for one frame for each VPI value is performed by the read cell determination unit 5.
4 until the EOM cell is monitored. When the EOM cell is monitored, the cell data of the search VPI value is read for one frame, and the reading of the cell data is completed (steps 41S and 42S).

The read cell data is distributed to each output port in the frame assembling buffer 56 according to the fixed reading order.

In this embodiment, the proposed address management method for the shared buffer of ATM cells is AAL type 5
By applying to the frame assembly circuit in
A circuit that reduces the circuit scale of a frame assembly circuit and facilitates expansion of the number of connections is configured.

[0037]

The first effect is that, when an illegal operation occurs in the management of the address of the shared buffer, the illegal operation of the address management can be easily detected. The reason is that in the address management of the cell buffer, all the address values of the shared buffer are managed by one CAM for both the free address and the read address. By searching the CAM with the address value of the shared buffer, the shared buffer is searched. This is because duplicate use of addresses can be easily detected.

The second effect is that the address management of the shared buffer can be easily performed. Therefore, the circuit configuration can be simplified and the circuit scale can be reduced. The reason is that the search function of the CAM is used for searching for a free address and a read address of the shared buffer.

The third effect is that the circuit and the scale are not changed even if the output port number which is a management parameter of the ATM cell increases. The reason is the accumulated AT
This is because not only the M cell data but also the managed addresses are shared and stored in one CAM regardless of the output port number.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a cell switch of a shared buffer type for executing an address management method in an ATM cell shared buffer according to the present invention.

FIG. 2 is a diagram for explaining in detail a configuration of an address management circuit unit in FIG. 1;

FIG. 3 is a flowchart of a free address search in the address search unit of FIG. 1;

FIG. 4 is a flowchart of a read address search in an address search unit of FIG. 1;

FIG. 5 shows an AAL (ATM Adaptation Layer) according to the present invention.
It is a block diagram which shows the structure of the frame assembly circuit of a type 5 ATM cell.

FIG. 6 is a diagram illustrating in detail a configuration of an address management circuit unit in FIG. 5;

FIG. 7 is a flowchart of a free address search in the address search unit of FIG. 5;

FIG. 8 is a flowchart of a read address search in the address search unit of FIG. 5;

FIG. 9 is a block diagram showing an example of a conventional shared buffer address management method.

[Explanation of symbols]

Reference Signs List 11 address management circuit 12 cell buffer 13 address search unit 14 CAM 15 cell multiplexing unit 16 switch table 17 output port number generation unit 18 cell separation unit 21 address 22 output port number 23 empty flag 24 CAM pointer list for output port number 51 Invalid Cell Discarding Unit 52 Received Cell Judgment Unit 53 Assembly Request FIFO 54 Read Cell Judgment Unit 55 Header Deletion Unit 56 Frame Assembly Buffer 61 VPI Value 91 Shared Buffer 92 # 1 Buffer 93 # 2 Buffer 94 #N Buffer 95 Free Address Buffer 96 Write control unit 97 Read control unit

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[Procedure amendment]

[Submission date] May 21, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention] A in the shared buffer of the ATM cell
Dress management equipment

[Claims]

1. An empty address and reading of a shared buffer
Has content address memory for storing addresses
Buffer in Shared Buffer ATM Switch
The address pointer of the content address memory.
Empty or read address of shared buffer from start position
And means for searching for the address , wherein the means for searching for the address
When writing, write points prepared for each output port number
Free address that is closest to the
Address, and the search does not find a free address.
If not, the write pointer is initialized, and
Address is found, the corresponding address flag
Is rewritten from empty to in use, and the cell buffer is written.
The writing means for outputting as an address and the means for searching for the address may be a shared buffer.
Readout prepared for each output port number
Closest to pointer, address flag in use
Search for an address and search does not find the address
If not, initialize the read pointer and read
If the address corresponding to the overflow pointer is found
Rewrites the corresponding address flag from being used to empty,
Read to output as read address of cell buffer
ATM cell shared buffer
Address management device in the web server.

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an asynchronous transfer mode (hereinafter referred to as ATM).
Address of the shared buffer ATM cells in the communication system
Related to a security management device .

[0002]

2. Description of the Related Art Conventionally, an ATM cell shared buffer implemented in an ATM switch or the like has a purpose of reducing the storage buffer capacity of the ATM cell and minimizing cell loss with a small buffer amount due to a statistical multiplexing effect. I have.

[0003] For example, "Large-capacity ATM switch LSI"
Development ”, Shimizu et al., 1997 IEICE General Conference B-
8-22 describes a technique of managing a free address of a shared buffer and a use address by using a buffer that is individually prepared.

FIG. 9 is a block diagram showing an example of a conventional shared buffer address management method. Shared buffer 91
Is a cell storage buffer for storing received cells according to the instruction of the write control unit 96 and reading out the cells according to the instruction of the read control unit 97. The free address buffer 95 manages all free addresses in the shared buffer 91. The read address buffers 92, 93, and 94 are prepared for each output port number for managing the ATM cell, and manage the address of the shared buffer 91 which is "in use" by writing the cell data in the shared buffer 91. In FIG. 9, the number of output port numbers is described as # 1 to #N.

[0005] The write control unit 96 determines the registration address of the received ATM cell in the shared buffer 91 and registers the address used by the registration in the read address buffers 92, 93 and 94. Read control unit 97
Determines the read address from the shared buffer 91 and registers the “unused” address in the free address buffer 95 by reading. The empty address output from the empty address buffer 95 is always registered in one of the read buffers 92, 93, and 94 corresponding to the output port number value when used for writing. The read addresses output from the read buffers 92, 93 and 94 are always registered in the free address buffer 95 when used for reading. Thus, the address of the shared buffer 91 is always managed by the empty address buffer 95 or the read address buffers 92, 93, 94. Further, by using the buffers for managing the addresses in a FIFO (First In First Out) format, the order of the ATM cells read from the shared buffer 91 is maintained.

[0006]

However, the prior art has the following problems.

[0007] The first problem is that once a fraud has occurred in address management, the fraud will persist without disappearing.

The reason is that addresses circulate between an empty address buffer and a read address buffer.

A second problem is that the circuit scale increases as the number of output ports increases. Therefore, when expanding the number of output ports, the circuit configuration must be changed.

[0010] The reason is that a read address buffer is prepared for each output port. Since a read address buffer is prepared for each output port, the buffer capacity increases as the number of output ports increases, which leads to an increase in circuit size.

An object of the present invention has been made to solve the above problems, the shared buffer ATM cells A
A dress management device is provided.

[0012]

An address management apparatus for an ATM cell shared buffer according to the present invention stores a used address and an unused address of a shared buffer for randomly registering an ATM cell in a content address memory (Content Address).
s Memory: hereinafter referred to as CAM). The address search is performed by using the search function of the CAM, thereby easily managing the address of the shared buffer.

In the ATM cell shared buffer of the present invention,
Address management device, the free address of the shared buffer
Content address memo to store read address
Address of the content address memory
Free or read the shared buffer from the position indicated by the pointer
Means for retrieving a delivery address, and means for retrieving the address.
However, when writing to the shared buffer,
The address pointer closest to the prepared write pointer
Search for a vacant address with an empty lag, and by searching,
If no free address is found, write
Initializes the interface and if an empty address is found
Rewrites the corresponding address flag from empty to in use,
Write to output as write address of cell buffer
The means for searching, and the means for searching, are shared buffers.
Readout prepared for each output port number
Closest to pointer, address flag in use
Search for an address and search does not find the address
If not, initialize the read pointer and read
If the address corresponding to the pointer is found,
Rewrite the corresponding address flag from busy to empty
Read method that outputs as buffer read address
It is characterized by having a step.

The AAL type 5 frame of the present invention
Address management device for shared buffer in assembly circuit
Determines whether the received cell is valid or invalid, and discards only invalid cells.
Invalid cell discard unit to discard and shared buffer to store cells
, The address of the shared buffer, the VPI value of the received cell, and empty
Address memory that stores a set of flags
And writing / reading of the content address memory for each VPI
An address search unit for searching for a read address, and for each VPI
To determine whether the received cell is the last cell of the packet.
The final cell of the packet is determined by the
Request to store the VPI value of the cell determined to be
The FIFO and cells read from the shared buffer are
Read cell determination unit that determines whether the cell is the last cell
And the payload from the cell read from the shared buffer
Take out the header deletion part and the page received from the header deletion part.
Frame assembly bar that assembles erase data into a frame
And a buffer. In addition, the address search unit
For storing the address of the content address memory for each VPI
The content address memory has an inter-table,
The write address of the received cell is stored in the address pointer table.
To the VPI value of the received cell managed by
From the position indicated by the embedded pointer
Search with the search address as the search key, and
Read pointer managed in the pointer table
From the position indicated by, read from the FIFO by the address search unit.
Search key for issued VPI value and empty flag indicating registered
As the end of the packet in the read cell determination unit.
Indicates same VPI value and registered until cell is detected
The empty flag is retained as a search key.
You.

According to the present invention, the arriving cell data is A
All are stored in one cell buffer regardless of the connection of the TM cell. The empty address of the cell buffer at the time of storing the cell data and the read address at the time of reading the cell data are easily searched from the CAM by using the address search function. At the time of accumulating the cell data, the address of the cell buffer of the cell data to be accumulated is determined by using the empty address flag as a search key and the empty address closest to the write pointer value prepared for each output port number from the CAM using the address search function. Is read. When reading cell data, the address of the cell buffer to be read is:
Using the output port number of the cell to be read as a search key, the closest address is read from the read pointer value prepared for each output port number. This facilitates the normality management of the storage cell address registration order while using the shared buffer.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a shared buffer type cell switch for executing an address management method in a shared buffer of ATM cells.

Address management circuit 11 for shared buffer
As shown in FIG. 1, the CAM 14 has a CAM 14 that manages a vacant address of a cell buffer 12 that is a shared buffer and a read address for each output port number, and an address search unit 13 that searches the CAM 14 for a vacant address and a read address. doing. The cell buffer 12 is a buffer for temporarily storing ATM cells, and is a shared buffer for sequentially registering received cells regardless of the output port number. The cell multiplexing unit 15 multiplexes the ATM cells in the fixed order of the input ports, and multiplexes the ATM cells with the cell buffer 12 and the switch table 16.
Output to The switch table 16 determines the output port number of the ATM cell from the input cell data,
Output to the address search unit 13. The output port number generation unit 17 generates the output port numbers in a fixed order, and outputs the output port numbers to the address search unit 13 and the cell separation unit 18. The cell separation unit 18 distributes the cell data read from the cell buffer 12 to output ports obtained from the output port number generation unit 17.

Next, details of the configuration of the address management circuit section 11 will be described with reference to FIG. The CAM 14 stores the cell buffer 12 when storing the data in the cell buffer 12 in units of cells.
, An output port number 22 of the reception cell stored in the cell buffer, and data of a vacancy flag 23 indicating use and non-use (vacancy) of the corresponding address. The empty flag 23 indicates that the registered cell buffer address is empty (unused) if the flag value is “0”.
If the flag value is "1", it indicates that cell data is written (in use) at the address of the cell buffer.

The address search unit 13 prepares a write pointer Wp (x) and a read pointer Rp (x) prepared for each output port number in the address management of the CAM 14, and writes the CAM of the CAM that has finished writing for each output port. Address value,
It has a table 24 for managing the address value of the CAM for which reading has been completed.

Next, the operation of the circuit of FIG. 1 will be described with reference to the drawings. ATM cells from multiple input ports are:
In the cell multiplexing unit 15, the cells are multiplexed in a fixed order of the input ports, and are written in the cell buffer 12. The address on the cell buffer 12 where the ATM cell is to be written is determined by searching an empty address of the cell buffer registered in the CAM 14 by the address search unit 13.
The address search unit 13 receives the output port number of the received cell from the switch table 16 and searches the CAM 14 for a free address in the cell buffer closest to the address where the ATM cell to the input output port is already registered. .

FIG. 3 is a flow chart of an empty address search in the address search unit 13. Referring to FIG. 3, the address search unit 13 is the CAM which is closest to the write pointer (Wp (x) in the figure) prepared for each output port number and whose empty flag registered in the CAM 14 is “0”. Address (steps 1S, 2
S, 3S, 4S). If a free address of the cell buffer 12 is not found by the search, it is determined that the cell buffer 12 has overflown, and the write pointer Wp (x) for the output port number is initialized without outputting a free address. (Steps 8S, 9
S). If a free address is found, the CAM 14
The empty flag 23 of the corresponding address is rewritten to "1", and the registered address 21 of the cell buffer 12 is output as an empty address (steps 5S, 6S, 7).
S).

Reading of cell data from the cell buffer 12 is performed by reading address data of all output ports in a fixed order. The address search unit 13 searches the CAM 14 for an address read from the cell buffer 12 using the output port numbers input from the output port number generation unit 17 in a fixed order as search keys.

FIG. 4 is a flowchart of a read address search in the address search unit 13. Referring to FIG. 4, the address search unit 13 uses the output port number to be output and a search key with the empty flag set to “1” to read a pointer prepared for each output port number (Rp in the figure).
(X)) and search the address of the closest CAM (steps 11S, 12S, 13S, 14S). If the CAM address is not found by the search, it is determined that the cell buffer 12 underflows the search value, and the Rp (x) for the output port used as the search key is determined.
Is initialized (steps 18S, 19S). If the address of the CAM corresponding to the search key is found, CA
The corresponding address flag 23 of M14 is rewritten to empty “0”, and the registered address 21 of the cell buffer 12 is output as a read address of the cell buffer 13 (steps 15S, 16S, 17S).

The read cell data is transmitted to the cell separation unit 1
At 8, the output ports are sorted according to the fixed order.

Next, another embodiment of the present invention will be described in detail with reference to the drawings. FIG. 5 shows an AAL (ATM Adaptation Layer) type 5 A using this address management method.
It is a block diagram which shows the structure of the frame assembly circuit of a TM cell. Referring to FIG. 5, the address management circuit unit 11
Is a CAM that manages a vacant address of the cell buffer 12 as a shared buffer and a read address for each VPI value.
14 and an address search unit 13 for searching the CAM 14 for a free address and a read address. A
The TM cell frame assembling circuit includes an address management circuit 11 of the shared buffer, an invalid cell discarding unit 51 around the cell buffer 12, a received cell judging unit 52, an assembling request FIFO 53, a read cell judging unit 54, A header deletion unit 55 and a frame assembly buffer 56 are provided.

The configuration of the address management circuit section 11 in the present embodiment will be described with reference to FIG. As shown in the figure, the CAM 14 stores the address 21 of the cell buffer 12 when storing the data in the cell buffer 12 in ATM cell units.
And the VPI value 61 of the received cell stored in the cell buffer
And an empty flag 23 indicating the use and unused (empty) of the corresponding address. In the empty flag 23, if the flag value is "0", the registered cell buffer address is empty (unused), and if the flag value is "1", the cell data is written in the cell buffer address. (Used).

The address search unit 13 manages the address of the CAM 14 by using a write pointer Wp prepared for each VPI value.
(x) and a read pointer Rp (x) are prepared, and the address value of the CAM after writing and the address value of the CAM after reading are managed for each receiving cell.

Next, the operation of the circuit of FIG. 5 will be described with reference to the drawings. The received cell is discarded by the invalid cell discarding unit 51 except for the user cell, and only the user cell is output to the received cell determining unit 52 and the cell buffer 12. The received cell determination unit 52 determines the received user cell VPI value in the CAM 14
Is output to the address search unit 13 as a registered value to the receiver, and when the payload type (PT) is “001”, the received cell is determined to be an EOM (End Of Message) cell, and the VPI value is also output to the assembly request FIFO 53. .

The address search unit 13 searches for an empty address in the cell buffer closest to the address where the ATM cell of the received VPI value has already been written. Is registered. The cell data registered in this way is V
When one frame is accumulated for each PI value, it is read out for frame assembly. The VPI value of the ATM cell is registered in the assembly request FIFO 53 when the EOM cell is received. Therefore, the VPI value is registered every time one frame of cell data is written in the cell buffer 12.

The address search unit 13 is provided with an assembly FIFO
The VPI value is read from 53, and the read address of the ATM cell cell buffer for the VPI value written for one frame is searched. Reading of one frame of cell data for each VPI value is performed until the read cell determination unit 54 monitors the EOM cell. When the EOM cell is monitored, the cell data of the search VPI value is read for one frame, and the reading of the cell data is completed. The cell data read from the cell buffer is assembled into a frame by deleting the cell header in the header deleting section 55 and sequentially registering the cell data in the frame assembling buffer 56.

FIG. 7 is a flowchart for searching for an empty address in the address search unit 13 in FIG. Referring to the figure, the address search unit 13 is closest to a write pointer (Wp (x) in the figure) prepared for each VPI value,
The address of the CAM whose empty flag is “0” registered in the CAM 14 is searched (steps 21S, 22).
S, 23S, 24S). If no empty address is found by the search, it is determined that the cell buffer 12 has overflowed, and the write pointer Wp (x) for the VPI value is initialized without outputting the empty address (step 28S). , 29S). If a free address is found, the free flag 23 of the corresponding address in the CAM 14 is rewritten to "1", and the registered address 21 of the cell buffer 12 is output as a write address (steps 25S, 26S, 27S). .

Reading of cell data from the cell buffer 12 is performed by reading address data of all the received cells in a fixed order. The address search unit 13 searches the CAM 14 for a read address from the cell buffer 12 using the VPI value of the received cell input in a fixed order from the read cell determination unit 54 as a search key.

FIG. 8 is a flowchart of a read address search in the address search unit 13 of FIG. Referring to the figure, the address search unit 13 uses a VPI value of a received cell to be output and a search key in which an empty flag is set to “1”.
Read pointer prepared for each VPI value (Rp in the figure)
(X)), the nearest CAM address is searched (steps 31S, 32S, 33S, 34S). If the address of the CAM is not found by the search, it is determined that the cell buffer 12 underflows with respect to the search VPI value, and Rp (x) with respect to the VPI value of the received cell used as the search key is initialized (step 38S). , 39
S). When the address of the CAM corresponding to the search key is searched, the corresponding address flag 23 of the CAM 14 is rewritten to empty “0”, and the registered cell buffer 12 is rewritten.
Is output as the read address of the cell buffer 13 (steps 35S, 36S, 37S).

The address search unit 13 is provided with an assembly FIFO
The VPI value is read from 53, and an ATM cell read address for the VPI value written for one frame is searched (step 40S). The reading of the cell data for one frame for each VPI value is performed by the read cell determination unit 5.
4 until the EOM cell is monitored. When the EOM cell is monitored, the cell data of the search VPI value is read for one frame, and the reading of the cell data is completed (steps 41S and 42S).

The read cell data is distributed to each output port in the frame assembling buffer 56 according to the fixed reading order.

In this embodiment, the proposed address management method for the shared buffer of ATM cells is AAL type 5
By applying to the frame assembly circuit in
A circuit that reduces the circuit scale of a frame assembly circuit and facilitates expansion of the number of connections is configured.

[0037]

The first effect is that, when an illegal operation occurs in the management of the address of the shared buffer, the illegal operation of the address management can be easily detected. The reason is that in the address management of the cell buffer, all the address values of the shared buffer are managed by one CAM for both the empty address and the read address, and the CAM is searched by the address value of the shared buffer, so that the shared buffer is searched. This is because duplicate use of addresses can be easily detected.

The second effect is that the address management of the shared buffer can be easily performed. Therefore, the circuit configuration can be simplified and the circuit scale can be reduced. The reason is that the search function of the CAM is used for searching for a free address and a read address of the shared buffer.

The third effect is that the circuit and the scale are not changed even if the output port number which is a management parameter of the ATM cell increases. The reason is the accumulated AT
This is because not only the M cell data but also the managed addresses are shared and stored in one CAM regardless of the output port number.

[Brief description of the drawings]

A in the shared buffer ATM cells of the present invention; FIG
FIG. 3 is a block diagram illustrating a configuration of a cell switch of a shared buffer type that performs dress management .

FIG. 2 is a diagram for explaining in detail a configuration of an address management circuit unit in FIG. 1;

FIG. 3 is a flowchart of a free address search in the address search unit of FIG. 1;

FIG. 4 is a flowchart of a read address search in an address search unit of FIG. 1;

FIG. 5 shows an AAL (ATM Adaptation Layer) according to the present invention.
It is a block diagram which shows the structure of the frame assembly circuit of a type 5 ATM cell.

FIG. 6 is a diagram illustrating in detail a configuration of an address management circuit unit in FIG. 5;

FIG. 7 is a flowchart of a free address search in the address search unit of FIG. 5;

FIG. 8 is a flowchart of a read address search in the address search unit of FIG. 5;

FIG. 9 is a block diagram showing an example of a conventional shared buffer address management method.

[Description of Signs] 11 Address management circuit 12 Cell buffer 13 Address search unit 14 CAM 15 Cell multiplexing unit 16 Switch table 17 Output port number generation unit 18 Cell separation unit 21 Address 22 Output port number 23 Empty flag 24 For output port number CAM pointer list 51 Invalid cell discarding unit 52 Received cell judging unit 53 Assembly request FIFO 54 Readout cell judging unit 55 Header deleting unit 56 Frame assembling buffer 61 VPI value 91 Shared buffer 92 # 1 buffer 93 # 2 buffer 94 #N buffer 95 free address buffer 96 write control unit 97 read control unit

Claims (6)

[Claims] 1. An address management method for a shared buffer of ATM cells, comprising the steps of: accumulating a free address of a shared buffer and a read address in one content address memory; and sharing from a position indicated by an address pointer of the content address memory. An address management method for a shared buffer of ATM cells, comprising a step of searching for an empty or read address of a buffer, and performing address management of a shared buffer of ATM cells. 2. A method for managing a shared buffer address in a shared buffer type ATM switch, comprising the steps of: accumulating a free address of a shared buffer and a read address in one content address memory; and indicating an address pointer of the content address memory. An address management method for a shared buffer of ATM cells, comprising a step of searching for an empty or read address of a shared buffer from a position, and managing the address of the shared buffer of ATM cells. 3. A method for managing an address of a shared buffer in an AAL type 5 frame assembling circuit, comprising: storing an empty address of a shared buffer and a read address in one content address memory; and an address pointer of the content address memory. Searching for an empty or read address of the shared buffer from the position indicated by (a), and managing the address of the shared buffer of the ATM cell. 4. A step of searching for an empty or read address of the shared buffer, wherein at the time of writing to the shared buffer, an empty address closest to a write pointer prepared for each output port number and having an empty address flag is searched. And if the empty address is not found by the search, the step of initializing the write pointer. If the empty address is found, the corresponding address flag is rewritten from empty to being used, and the cell is rewritten. A step of outputting as a buffer write address; a step of searching for an address which is closest to a read pointer prepared for each output port number when reading from the shared buffer and whose address flag is in use; If not found, read out 4. The method according to claim 1, further comprising the steps of: initializing the interface; and, when an address corresponding to the read pointer is retrieved, rewriting the corresponding address flag from being used to being empty and outputting it as a read address of the cell buffer. Address management method in the shared buffer of the ATM cell. 5. A shared buffer address management device in a shared buffer type ATM switch, comprising: a content address memory for storing a free address and a read address of the shared buffer; and a shared buffer from a position indicated by an address pointer of the content address memory. Means for searching for a vacant or read address, and when writing to the shared buffer, searching for a vacant address closest to the write pointer prepared for each output port number and having the vacant address flag. If the address is not found, the write pointer is initialized, and if an empty address is found, the corresponding address flag is rewritten from empty to in use.
When the address is output as the write address of the cell buffer and read from the shared buffer, the address closest to the read pointer prepared for each output port number and whose address flag is in use is searched. In this case, the read pointer is initialized, and if an address corresponding to the read pointer is searched, the corresponding address flag is rewritten from being used to empty and output as a read address of the cell buffer. Address management device for shared buffer of ATM cells. 6. An address management device for a shared buffer in an AAL type 5 frame assembling circuit, comprising: a content address memory for storing an empty address of a shared buffer and a read address; and a position indicated by an address pointer of the content address memory. A means for searching for an empty or read address of the shared buffer, and when writing to the shared buffer, searching for an empty address closest to the write pointer prepared for each output port number and having an empty address flag, If no free address is found, the write pointer is initialized, and if a free address is found, the corresponding address flag is rewritten from free to in use,
When the address is output as the write address of the cell buffer and read from the shared buffer, the address closest to the read pointer prepared for each output port number and whose address flag is in use is searched. In this case, the read pointer is initialized, and if an address corresponding to the read pointer is searched, the corresponding address flag is rewritten from being used to empty and output as a read address of the cell buffer. Address management device for shared buffer of ATM cells.