JPS5647981A - Operation control system of buffer memory - Google Patents

Operation control system of buffer memory

Info

Publication number
JPS5647981A
JPS5647981A JP12286779A JP12286779A JPS5647981A JP S5647981 A JPS5647981 A JP S5647981A JP 12286779 A JP12286779 A JP 12286779A JP 12286779 A JP12286779 A JP 12286779A JP S5647981 A JPS5647981 A JP S5647981A
Authority
JP
Japan
Prior art keywords
memory
buffer memory
state
data
fifo405
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12286779A
Other languages
Japanese (ja)
Other versions
JPS6213693B2 (en
Inventor
Kunihiko Niwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12286779A priority Critical patent/JPS5647981A/en
Publication of JPS5647981A publication Critical patent/JPS5647981A/en
Publication of JPS6213693B2 publication Critical patent/JPS6213693B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To make the recentering of a memory possible as to a satellite communition system by forcing the buffer memory to be in an overflow state when the buffer memory is placed in an underflow state and by resetting half the memory capacity.
CONSTITUTION: FIFO404 is supplied with data 401 synchronizing with clock 402 and outputs input ready signal 403. During data reading operation, when FIFO405 sends output ready signal 415 of logic 0 at random time to cause an underflow, the supply of readout clock 409 is stopped and the reading operation is stopped. Then, data in FIFO404 and 405 reach the N-th memory cell of FIFO405, which overflows at fixed time to reset the master and then shift-out signal 414 is supplied. As a result, the operation is restarted from the state in which half the memory capacity is full and the other is empty, so that recentering will be performed.
COPYRIGHT: (C)1981,JPO&Japio
JP12286779A 1979-09-25 1979-09-25 Operation control system of buffer memory Granted JPS5647981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12286779A JPS5647981A (en) 1979-09-25 1979-09-25 Operation control system of buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12286779A JPS5647981A (en) 1979-09-25 1979-09-25 Operation control system of buffer memory

Publications (2)

Publication Number Publication Date
JPS5647981A true JPS5647981A (en) 1981-04-30
JPS6213693B2 JPS6213693B2 (en) 1987-03-28

Family

ID=14846589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12286779A Granted JPS5647981A (en) 1979-09-25 1979-09-25 Operation control system of buffer memory

Country Status (1)

Country Link
JP (1) JPS5647981A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61281641A (en) * 1985-06-06 1986-12-12 Nec Corp Data transmitting equipment
JPS62162284U (en) * 1986-03-31 1987-10-15
JPS63236412A (en) * 1987-03-25 1988-10-03 Nec Corp Converting system for speed of digital signal
JPH02502780A (en) * 1988-10-14 1990-08-30 ディジタル　イクイプメント　コーポレーション Method and apparatus for detecting impending overflow and/or underrun in a mutable buffer
JP2005321933A (en) * 2004-05-07 2005-11-17 Fuji Xerox Co Ltd Data input and output device and data input and output method
JP2008065703A (en) * 2006-09-08 2008-03-21 Toshiba Corp Control device and control method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61281641A (en) * 1985-06-06 1986-12-12 Nec Corp Data transmitting equipment
JPS62162284U (en) * 1986-03-31 1987-10-15
JPS63236412A (en) * 1987-03-25 1988-10-03 Nec Corp Converting system for speed of digital signal
JPH02502780A (en) * 1988-10-14 1990-08-30 ディジタル　イクイプメント　コーポレーション Method and apparatus for detecting impending overflow and/or underrun in a mutable buffer
JP2005321933A (en) * 2004-05-07 2005-11-17 Fuji Xerox Co Ltd Data input and output device and data input and output method
JP4569163B2 (en) * 2004-05-07 2010-10-27 富士ゼロックス株式会社 Data input / output device and data input / output method
JP2008065703A (en) * 2006-09-08 2008-03-21 Toshiba Corp Control device and control method

Also Published As

Publication number Publication date
JPS6213693B2 (en) 1987-03-28

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